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The V850 CPU cores
General information
Launched1994; 31 years ago (1994)
Discontinuedcurrent
Common manufacturer
  • Renesas Electronics
    (formerly NEC)
Performance
Max. CPU clock rate32 kHz to 320 MHz
Data width32
Address width32
Cache
L1 cacheconfigurable
Architecture and classification
ApplicationEmbedded,
Mobile equipment,
Air conditioner,
Automotive
Technology node0.8 μm to 40 nm
MicroarchitectureV810 (1991),
V850 (1994),
V850E (1996),
V850E1 (1999),
V850ES (2002),
V850E2 (2004),
V850E1F (2005),
V850E2v2 (FIX ME),
V850E2v3 (2009),
V850E2v4 (2010),
V850E2v3S (2011),
V850E3v5 (2014)
Instruction setV800 Series
Extensions
  • E/E1/E1F/E2/
    E2M/E2R/E2S/E3
Number of instructionsv850: 74
v850e: 81
v850e1: 80 (83)
v850e1f: 96
v850e2: 89
v850e2v3: 98
V850e3v5: FIX ME
Physical specifications
Cores
  • configurable
Products, models, variants
Product code names
  • μPD70P3xxx
  • μPD703xxx
  • μPD70F3xxx
  • R7F70xxxx
Variant
  • V850 Family,
    RH850 Family
History
Predecessor"V80" CISC core

V850 is a 32-bit RISC CPU architecture produced by Renesas Electronics for embedded microcontrollers. It was designed by NEC as a replacement for their earlier NEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas as of 2018.

The V850 architecture is a load/store architecture with 32 32-bit general-purpose registers. It features a compressed instruction set with the most frequently used instructions mapped onto 16-bit half-words.

Intended for use in ultra-low power consumption systems, such as those using 0.5 mW/MIPS, the V850 has been widely used in a variety of applications, including optical disk drives, hard disk drives, mobile phones, car audio, and inverter compressors for air conditioners. Today, microarchitectures primarily focus on high performance and high reliability, such as the dual-lockstep redundant mechanism for the automotive industry; and the V850 and RH850 families are comprehensively used in cars.

The V850/RH850 microcontrollers are also used prominently on non-Japanese automobile marques such as Chevrolet, Chrysler, Dodge, Ford, Hyundai, Jeep, Kia, Opel, Range Rover, Renault and Volkswagen Group brands.

Overview

[edit]

The V850 is the trademark name for a 32-bit RISC CPU architecture for embedded microcontrollers of Renesas Electronics Corporation. It was originally developed and manufactured by NEC Corporation in the early 1990s[1][2] (the copyright mark for the microcode on the package shows 1991) as a branch of the V800 Series[3]: 97, PDF103  and is still being evolved today.[4]

Its base-architecture has been succeeded by the V850 family variants, named V850E, V850E1, V850ES,[5] V850E1F, V850E2, V850E2M, V850E2S, and the RH850 family (V850E2M, V850E2S, and V850E3) CPU cores.

Many compilers and debuggers are available from various development tool vendors.

Real-time operating systems are provided by compiler vendors.

In-circuit emulators (ICE) are provided by many vendors. Legacy proven pod-based types—the JTAG-based N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type—are available.

Application systems

[edit]
Sony Optiarc AD‑7240S employs V850ES core based SoC; SCOMBO 8 in multi-chip packaging (MC-10045)
μPD70F3017GC-25; V850/SA1 marked "EL4" on Quantum Fireball EL51A881
NEC's mobile phone; N504iS employs SoC; based on V850E, the only CPU on it
Factory integrated car audio head unit in dashboard of Toyota Camry
USB 3.0 expansion card for PCIe employed Renesas V850 CPU based LSI

The first V850 CPU core was used in many DVD drives manufactured by NEC's and Sony's Optiarc (later wholly owned by Sony).[6][7] NEC Electronics (currently Renesas Electronics) itself intensively developed application-specific standard products (ASSPs) for SCOMBO Series optical disk drives.[8][9] This first generation of processor core was also used for hard disk drives manufactured by Quantum Corporation (see photo).

In 1997, the V850/xxn product line started with the V850/SA1[10] and the V850/SV1[11] and expanded its application to ultra-low-power products such as "handy camcorders." It has a main and sub internal oscillator amplifier working from 1.8 V to 3.6 V with external crystal or ceramic resonator.[10] Software STOP mode, whose internal watch timer operates with a 32.768 kHz sub-oscillator, typically consumes only 8μA of electrical current.[12][13] In 1998, NEC launched the V850/SB1[14] with IEBus controller, for car audio, an ultra-low-power (3.6 mW@5V/MIPS) and ultra-low-noise (EMI/EMS) 5V product.[15] The V850/SC1[16] was also for car audio.[17] These strategic product line expansions succeeded in increasing the number of devices sold.

The first generation of the V850 core is also used for some NEC mobile phones.[18] It is also used for the programmable-host CPUs of some small form factor GSM/GPRS mobile devices with GPS embedded modem modules.[19]

In the next phase, NEC targeted the automotive industry with a CAN bus controller based on the V850[20] as the V850/SF1.[21] Later on, the automotive industry became the main target of the V850 and RH850.

The V850E core was targeted at system-on-a-chip (SoC) applications as well as standard products,[22][23] and was used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's.[24][25][26][27][28] V850E and V850ES are also used in air conditioning inverter compressors.[29][30][31][32] At this stage, another mass market was its use in car audio.[33] The V850ES core succeeded in the low-power embedded-product line,[34] and is ISA-compatible with the V850E. NEC Electronics (currently, Renesas Electronics) adopted the V850 CPU core for its USB 3.0 controllers.[35]: 11 

Around 2005, several companies started a feasibility study for the FlexRay controller on the V850E platform. Yokogawa Digital Computer (currently DTS INSIGHT) developed an evaluation board named GT200 with a V850E/IA1 and a field-programmable gate array (FPGA), which employs the FlexRay controller developed by Bosch.[36]: 78, PDF80 

The V850E2 core primarily targeted automotive areas,[37] but was also used for NEC's mobile phones.[38]

The V850 family lineup (based on V850E, V850ES, and V850E2 cores) and the Renesas RH850 family (based on the V850E3 core, as of 2018) are mainly employed in automotive applications as well as inter-equipment connectivity and motor-control specific microcontroller units (MCUs).[39][40]

Trademark strategy

[edit]

The V850 is a unregistered trademark but not a registered one.[41] NEC once applied for a trademark to be registered with the Japan Patent Office, but it was rejected,[42][43] as it was a natural extension of the series number. However, this action has been enough to prevent other people or organizations from registering it as a trademark. In addition, Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of one alphabetical with two numerical characters cannot be granted as a registered trademark. It is thus free to use without registration.

One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS).[44]: 3 [45]: 33  Another usage of PHOENIX 3 by Renesas Electronics is the COOL PHOENIX 3, which employs the ARM Cortex-M0 core.[46] PHOENIX 3 is a registered trademark of the 3DO Company as USPTO Reg. 2,009,119.[47]

According to current Renesas Electronics documentation, at least the following strings are regarded as its trademark: "V800 Series", "V850 family", "V850/SA1", "V850/SB1", "V850/SB2", "V850/SF1", "V850/SV1", "V850E/MA1", "V850E/MA2", "V850E/IA1", "V850E/IA2", "V850E/MS1", "V850E/MS2", "V851", "V852", "V853", "V854", "V850", "V850E", and "V850ES".[41][48]

Because the V850 trademark has been used for more than 20 years, most people do not know that the RH850 family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is consequently thought of as being without the legacy software compatibility of the V850.[49][50]

Development methodology

[edit]
V810 mounted on PC-FXGA (in Japanese)[51] Gaming Accelerator board.
Marked as "©NEC 1991."
Nintendo Virtual Boy employed customized V810. 14x20mm2 packge (on left) is marked "©NEC '91, '93."

Because the V850 family[48]: 16  was developed as a branch of the V800 series,[3]: 97, PDF103  the basic CPU architecture is inherited from the V810.[52] The instruction set architecture of the first V850 is drastically modified from that of the V810, but the difference is within a patch level from the GNU Compiler Collection point of view.[53] The main purpose of this change is to implement saturation arithmetic at customers' request.

A v833 CPU, a pin-compatible revision of the v832 CPU.[54][55] This microprocessor was used in car navigation systems during the 2000's, mostly made by Pioneer Corporation and Alpine Electronics.

The detailed design methodology of the V810 is described in this journal.[56] The V850 utilizes these design assets; but the datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.

The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL)[57][58][59] on the Falcon Simulator software, which are NEC's in-house CAD tools. This methodology is the same as that used for the NEC V60.[60] In the late 1980s, the Verilog HDL had not yet been acquired by Cadence Design Systems.[61] FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer named Earth Simulator.[62]

The difference from V60 is that the circuit diagram was written with a schematic editor, not of Calma but of Mentor Graphics, called NETED,[63] a part of the Design Architect product[64][65] on Apollo Computer's workstation, which was the major schematic editor at that moment.[66] It enabled designers to generate netlists, such as EDIF and SPICE, for LVS programs like Cadence's Dracula products, and NEC's in-house Zycad netlist for logic simulation. Later on, this circuit diagram of NETED was able to generate a gate-level Verilog HDL netlist for V850.

Most of the register-transfer-level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis had not yet to be practical. The FDL was precisely divided into datapath and random logic. For the datapath part, the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried for generating gate-level schematic, but it was only about 10% of the total circuit.

In addition, formal verification was also not yet practical, which meant that full regression test by dynamic logic simulation was required for the gate-level netlist to compare with the RTL one. For gate-level logic simulation, NEC's in-house CAD tool V-SIM was usually used.[67] But sometimes a hardware emulator, such as Zycad LE simulation accelerator,[68] was used for this purpose. (Refer to:.[69]: 13  In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.[70])

Architecture

[edit]

Basic architecture

[edit]

The basis of the V810 and V850 has a typical general-purpose registers-based load/store architecture.[71]: 4  There are 32 32-bit general-purpose registers. Register 0 (R0) is fixed as the Zero Register which always contains zero. In the V850, R30 is implicitly used by the sld and sst instructions. 16-bit short-format load/store instructions use element pointer (ep), where the addressing mode comprises the base address register ep and immediate-operand offsets. In V850E or later microarchitectures, R3 is implicitly used by PREPARE/DISPOSE; call stack frame creation; and unwinding instructions, as a stack pointer. Compilers' calling conventions also use R3 as the stack pointer.

The original V850 has a simple 5-stage 1-clock pitch pipeline architecture.[48]: 114–126  This is a significant feature of reduced instruction set computers (RISCs). But the object-code size is about half that of the MIPS R3000,[71]: 5  because the V810 and V850 adopted 16-bit and 32-bit 2-way form-length instruction formats, respectively,[48]: 38–40 [71]: 17 [52]: 29–30  and most of the frequently used instructions are mapped onto a 16-bit half-word. In other words, a 16-bit external bus width is enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipment. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.[72]: 4 

In addition, the instruction set is carefully implemented. For example, to execute a function call with a Jump and (Register) Link instruction,[48]: 61 [71]: 20 [52]: 64  which saves the next program counter (PC) on a register (fixed to R31 in V810), is also one of the RISC techniques to reduce the number of instructions. Return from the function can be accomplished by jmp [Rn] (jmp [R31] in V810) instruction.[48]: 61 [71]: 23 [52]: 65  Typical CISC processors use call and return instructions and push the next PC on their stack memory area.

But V810 and V850 have some microarchitecture differences. The V810 adopts a microprogram operation method for some instructions, such as floating-point arithmetic and bit string operations, while the V850 uses a one-hundred-percent hardwired control method. As a result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets, including the "find first one/zero" (search 1/0; SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.

Though the V800 series adopts a RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt a straightforward load/store architecture.[71]: 4  In addition, the "interlock" mechanism, both for the data hazards and for the branch hazards, are implemented:[71]: 33–35  in other words, an assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. A mixture of hand-assembled codes and C language compiled codes is facilitated by using compiler options, such as "-mno-app-regs" in the Gnu Compiler Collection.[73]

The IN instruction of the V810, which enables unsigned-load from memory-mapped I/O, was removed from the first V850s.[71]: 22 [52]: 63 

Detailed discussions are available in some old journals.[74][75]

Instruction set extensions

[edit]

The V850 series added many instruction set extensions, but all the extensions have backward compatibility.[76] Therefore, older software designed for the previous versions of the V850 work on new V850 cores.

The first generation of the V850 does not have unsigned load instructions, which had been removed from the V810 (where it was implemented with IN.H and IN.B). Then, in the second generation V850E (V850E1) Series, such unsigned functionality was again added (with LD.HU and LD.BU). In addition, the V850E has some other user-friendly "CISCy" extensions, such as call table, switch, and prepare/dispose.[77]: 217 

In 1996, the V853 was announced as the first 32-bit RISC microcontroller with integrated flash memory[78] but its maximum number of "erase and write" cycles was 16.[79]: 37 

In 1998, NEC strategically started to expand the V850 product line, to standard application-specific standard product (ASSP), application-specific integrated circuit (ASIC), and system on a chip (SoC) businesses.[80]

In 2001, NEC launched the V850ES core, which is an ultra-low-power series, but is ISA-compatible with the V850E.[81]

Around 2001, the Java Acceleration IP core for the V850 seemed to be provided to some customers in SoCs[82] but detailed information is only found in some patents.[83][84]

In 2005, NEC Electronics introduced the V850E2 core as the V850E2/ME3 product line with super-scalar architecture.[85]

In 2009, NEC Electronics introduced the V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.[86]

In 2011, Renesas first introduced the SIMD extension for the V850 into the V850E2H core.[76][87] As for the SIMD extension, some academic studies were done on instruction encoding and efficient SIMD code generation.[88] It was later added into the V850G3H, V850G3KH and other H-extension cores before Renesas changed the V850 name to "RH850". Unfortunately, there is almost no publicly available documentation for these cores because Renesas gated them under non-disclosure agreements (NDAs) that were only signed by automotive manufacturers.

Power consumption

[edit]

The original V810 and V850 CPU architecture is designed for ultra-low power applications.

The V810 is described in detail in some journals.[89][90]

According to Renesas's documentation, the power consumption of the V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.[5]: 14, 15 

The V810 was one of the most low-power 32-bit microcontroller products of the early 1990s. It operates at from 2.2 V to 5.5 V with a 5 V 0.8 μm (CZ4) fabrication process.[91] Measured with Dhrystone MIPS, power dissipation is 500 mW at 15MIPS and 40 mW at 6 MIPS, at 5 V and 2.2 V, respectively. This specification can be achieved both by well considered instruction-set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of which are the benefit of a simplified RISC architecture.

This ultra-low-power architecture was succeeded by V850/Sxn product line, which are still being mass-produced after 20 years. Most of the improved chips are produced using a 3.3 V, 0.35μm (UC1) fabrication process, where the CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz (sub-oscillator) to 16.78 MHz (main-oscillator) with internal oscillator amplifier plus external resonator (crystal or ceramic).[10] Its power dissipation is 2.7 mW/MIPS at 3.3 V when made with a 0.35 μm (UC1) fabrication process, and 3.6 mW/MIPS at 5 V with a 0.35 μm (CZ6) fabrication process. "Software STOP" stand-by mode for the mask ROM version of V850/SA1, whose internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator (IDD6), consumes typically only 8 μA electrical current. Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum. (IDD5)[92]: 440, IDD5 [13] Its 1.8 V typical CPU operating current at 32.768 kHz might be 22 μA (40 μA ÷ 3.3 V × 1.8 V), where power dissipation should be 40 μW. It corresponds to 1.0 mW/MIPS (40 μW ÷ 0.032768 MHz ÷ 1.15 DMIPS/MHz ÷ 1000).
The V850/Sxn product line is also tuned for low noise, with both EMI and with EMS. The V850/SB1 and SB2 are especially tuned for low EMI noise with a 5 V internal voltage regulator, which facilitates high sensitivity in receiving RF for car radios.[93]: 41–44 

In 2011, NEC launched the 3rd generation microarchitecture V850ES ultra-low-power series, which achieves 1.43 mW/MIPS at an operating voltage range of from 2.2 V to 2.7 V,[81] but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture. Its "Sub-IDLE" stand-by mode for the mask ROM version of V850ES/SA2 and V850ES/SA3, whose internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator (IDD6), consume typically only 5 μA electrical current. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consumes typically 40 μA, 100 μA at the maximum.[94]: 509  Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA (40 μA ÷ 2.5 V × 2.2 V), where power dissipation should be 68 μW. This is about 1.7 times that of V850/SA1. It corresponds to 1.6 mW/MIPS (68 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000).

The V850ES/JG3-L product line has ultra-low-power variants, the μPD70F3792, 793, and the μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with typical electrical current of 18 μA at 32.768 kHz,[95]: 1002, 1041  which should be 22 μW at 2.0 V (18 μA × 2.0 V ÷ 3.3 V × 2.0 V). This corresponds to 0.52 mW/MIPS (22 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode power consumption, with watch timer, should be typically 3.4 μW at 1.8 V (3.5 μA ÷ 3.3 V × 1.8 V × 1.8 V).[95]: 1002, 1041 

The power consumption of the NA85E2 (V850E2) core is much larger compared with the NU85E (V850E1) core using the same CB-12L (UX4L)[91][96] fabrication process. The reason is that the V850E2x core has a 128-bit instruction prefetch bus and more than one instruction prefetch queue,[97]: 16  while the average instruction length of the V800 series is 16 bits.[71]: 17  It means 16 instructions can be fetched from the memory at once, and the memory and prefetch circuits sleep fors 3 to 7 cycles for dual-pipeline superscalar architecture. This gap enlarges electrical current amplitude differences. In addition, the peak electric current exceeds allowances for the voltage stabilizers of mobile gadgets. As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times that of former generations, although it should be able to take advantage of new fabrication process technologies.[86] Some mobile equipment avoids using dual-instruction execution (dual-pipeline superscalar), adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.

Instruction opcode table

[edit]

Each opcode (operation code) table is from User's Manual: Architecture (refer to external links.).

V810 (obsoleted)

[edit]
  • 1st map opcodes
All opcodes (operation codes) of the hardwired control operation are contained within the first 16-bit half-word of an instruction, from the most significant bit (MSB). A 64-word depth ROM structure with branch condition code table is enough for decoding hardware. If a 16-bit literal operand is required, it is located in the second half-word. Microprogram control operations, bit strings, and floating-point arithmetic instructions are also located in the second 16-bit half-word. As a result, all the instructions have 16-bit and 32-bit 2-way form length. Unsigned load form memory mapped I/O is implemented as the In instruction. Arithmetic and logical instructions are not fully, but relatively, orthogonal.
The V810 does not have saturation arithmetic instructions, but 1 additional instruction in format II, such as SAT which checks flags (Overflow, Sign, Zero, and Half-word) and rewrites the specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.
Bit [12:10]
[15:13, 9] 		000 001 010 011 100 101 110 111 Format
000 X MOV ADD SUB CMP SHL SHR JMP SAR I(R,r)
001 X MUL DIV MULU DIVU OR AND XOR NOT
010 X MOV ADD SETF CMP SHL SHR SAR II(imm5,r)
011 X TRAP RETI HALT LDSR STSR Bit str.

100 0
100 1 		Bcond III(disp9)
BV BZ/BE BN(BS) BLT BNV BNZ/BNE BP(BNS) BGE
BC/BL BNH BR BLE BNC/BNL BH NOP BGT
101 X MOVEA ADDI JR JAL ORI ANDI XORI MOVHI IV/V
110 X LD.B LD.H LD.W ST.B ST.H ST.W VI(disp16[R],r)
111 X IN.B IN.H CAXI IN.W OUT.B OUT.H Float OUT.W VI/VII
NOP is an alias of Non-BR.

V850 (1st Gen.)

[edit]
Bit [7:5]
[10:8] 		000 001 010 011 100 101 110 111 Format
000 MOV NOT DIVH JMP SATSUBR SATSUB SATADD MULH I(R,r)
001 OR XOR AND TST SUBR SUB ADD CMP
010 MOV SATADD ADD CMP SHR SAR SHL MULH II(imm5,r)
011 SLD.B SST.B IV(disp7[ep],r)
100 SLD.H SST.H IV(disp8[ep],r)
101 Bit[0] SLD.W / SST.W Bit[3:0] Bcond IV/III
110 ADDI MOVEA MOVHI SATSUBI ORI XORI ANDI MULHI VI(disp16[R],r)
111 LD.B 2nd Map ST.B 2nd Map JARL Bit[15:14]
SET1/NOT1
/CLR1/TST1		 2nd Map
Extension		 V/VII/VIII
NOP is an alias of MOV R0,R0.
Bit [23:21]
 000 001 010 011 100 101 110 111 Format
[16] 1st Map  Bit[10:5]=111001
0 LD.H VII
1 ST.H VII
[16] 1st Map  Bit[10:5]=111011
0 LD.W VII
1 ST.W VII
[26:24] 1st Map  Bit[10:5]=111111
000 SETF LDSR STSR undef SHR SAR SHL undef IX(R,r)
001 TRAP HALT RETI 1st Map
Bit[15:13]
EI/DI
undef 		Illegal instruction X
01X Illegal instruction —
1XX Illegal instruction —

V850E/E1/ES

[edit]
Bit [7:5]
[10:8] 		000 001 010 011 100 101 110 111 Format
000  —† NOT SWITCH JMP ZXB SXB ZXH SXH I(R,r0)
MOV DBTRAP Bit[4]
SLD.BU
/SLD.HU		 SATSUBR SATSUB SATADD MULH I(R0,r31) / IV
undef I(R0,r) / IV
DIVH I(R,r) / IV
001 OR XOR AND TST SUBR SUB ADD CMP I(R,r)
010 CALLT ADD CMP SHR SAR SHL undef II(imm5,r0)
MOV SATADD MULH II(imm5,r)
011 SLD.B SST.B IV(disp7[ep],r)
100 SLD.H SST.H IV(disp8[ep],r)
101 Bit[0] SLD.W / SST.W Bit[3:0] Bcond IV/III(disp9)
110 ADDI Bit[15:11]
MOV(r=0) 		Bit[15:11]
DISPOSE(r=0) 		ORI XORI ANDI Bit[15:11]
undef 		VI(imm16,R,r)
/VI(imm32,R)
/XIII
MOVEA MOVHI STASUBI MULHI
111 LD.B 2nd Map ST.B 2nd Map Bit[15:14]
SET1/NOT1
/CLR1/TST1		 2nd Map VII(disp16[R],r)
/VIII(imm3,disp16[R])
† NOP is an alias of MOV R0,R0.
Bit [23:21]
[16, 26:24] 		000 001 010 011 100 101 110 111 Format
1st Map  Bit[10:5]=111001
0 XXX LD.H VII(disp16[R],r)
1 XXX ST.H
1st Map  Bit[10:5]=111011
0 XXX LD.W VII(disp16[R],r)
1 XXX ST.W
1st Map  Bit[10:5]=11110X
0 XXX 1st Map  Bit[15:11]  JR(r=0) / JARL (r≠0) V(disp22)
1 XXX 1st Map  Bit[15:11]  PREPARE(r=0) / LD.BU XIII/VII(disp16[R],r)
1st Map  Bit[10:5]=111111
0 000 SETF LDSR STSR undef SHR SAR SHL Bit[18:17]
SET1/NOT1
CLR1/TST1		 IX(R,r)
IX(R,[r])
0 001 TRAP HALT Bit[18:17]
RETI/CTRET
/DBRET
/undef 		1st Map
Bit[15:11]
EI/DI
undef		 undef X
0 010 SASF Bit[17]
MUL(R,r,w)
/MULU(R,r,w)		 Bit[17]
MUL(imm9,r,w)
/MULU(imm9,r,w) 		Bit[17]
DIVH(R,r,w)
/DIVHU(R,r,W) 		Bit[17]
DIV(R,r,w)
/DIVU(R,r,w)		 IX(R,r)
/XI(R,r,w)
/XII(imm9,r,w)
0 011 CMOV(imm5,r,w) CMOV(R,r,w) Bit[18:17]
BSW/BSH
HSW/undef		 undef Illegal instruction XI(c,R,r,w)
/XII(c,imm5,r,w)
0 10X Illegal instruction
1 XXX LD.HU VII(disp16[R],r)

List of the V800 Series CPU cores

[edit]
CPU core Product variants GCC targeting options[98] Remarks
V810[1]
(1991)		 V810 family
(V810, V805
 V820, V821[99])		 Revert patch required.[53]
Available on Planet Virtual Boy.
GCC named gccVB.		 Obsoleted products.
Unsigned & signed load.
μcoded float (single)[100] 1 KB I-cache.
5-stage pipeline.[101]
6.7 mW/MIPS (5 V Product)
V830[102]
(1997)		 V830 family
(V830 — V833[54][102][103])		 ditto Obsoleted products.
High end products.
Multimedia extension.
16 KB on-chip memory.
Multiply accumulate.
Saturation arithmetic
Branch prediction.[104]
V850
(1994)		 V850 family started
V851 — V852[105]
V853,[78][106][107] V854		 none or -mv850 Obsoleted products.
5-stage pipeline.
4.4 mW/MIPS (5 V product)
V850
(1997)		 V850/xxn
(e.g. V850/SA1)		 none or -mv850 Not for new developments.
Signed load.
1.15 Dhrystone MIPS/MHz
Ultra-low power products.
3.6 mW/MIPS (5 V product)
2.7 mW/MIPS (3.3V product)
1.0 mW/MIPS (1.8 V Sub-ope.)
V850E
(1996)		 V850E/MS1,[108][109]
V850E/MS2		 -mv850e Not for new developments.
Unsigned & signed load.
1.3 Dhrystone MIPS/MHz
Standard products.
V850E1
(1999)		 V850E/xxn
(e.g. V850E/MA1[22])
NB85E SoC core[110][111]
NU85E SoC core[110][111]
(Sony's & NEC's best-cellular.)		 -mv850e1 or ‑mv850es Unsigned & signed load.
N-Wire and N-Trace.
Standard products.
SoC Products.
V850ES
(2002)		 V850ES/xxn(-x)
(e.g. V850ES/SA2)		 -mv850es or ‑mv850e1 Unsigned & signed load.
Ultra-low power products.
1.43 mW/MIPS (2.5 V product)
0.52 mW/MIPS (2.0 V Sub-ope.)
Shift to V850E2S requested.
V850E1F
(2005)		 V850E/PH2, V850E/PH3
V850E/PHO3		 Patch required (maybe). H/W float (single precision).
V850E2
(2004)		 V850E2/ME3

NA85E2 SoC core[110][112]
(NEC's long-running cellular.
 Sets life = 2004–2012.)		 -mv850e2 Not for new developments.
Many errata but still alive.
Single insn. executing.
(Dual-executing errata.)
7-stage pipeline.
S/W float.
Standard Products.
SoC Products.
V850E2(v2)
()		 V850E2/xxn
(e.g. FIX ME)

NB85E2 SoC core[110][112][113]		 -mv850e2 Errata cleaned up.
Dual instruction executing.
7-stage pipeline.
S/W float.
Standard Products.
SoC Products.
V850E2M
(2009)
 G3		 V850E2/xxn
(e.g. V850E2/FG4)
RH850/nxn
 -mv850e2v3 and -msoft-float S/W float.
Dual instruction executing.
7-stage pipeline.
2.56 Dhrystone MIPS/MHz
1.5 mW/MIPS
Multi CPU core support.
Memory Protection.
V850E2R
(2010)
 G3R		 V850E2/xxn
(e.g. V850E2/MN4)
RH850/nxn
 -mv850e2v3 H/W float (double precision).
Dual instruction executing.
7-stage pipeline.
2.56 Dhrystone MIPS/MHz
Multi CPU core support.
Memory Protection.
V850E2S
(2011)
 G3K
 		 V850E2/xxn(-x)
(e.g. V850E2/Jx4-L)
(e.g. V850E2/Fx4-L)
RH850xnx		 -mv850e2v3 and ‑msoft‑float S/W float.
5-stage pipeline.
1.9 Dhrystone MIPS/MHz
Multi CPU core support.
Memory Protection.
Ultra-ultra-low power.
Standard products.
 V850ES/xxn pin compat.
Automotive products.
 Shift to RH850 requested.
V850E2H
(2010)[114]
V850E3
(2014)
 G3M
 G3MH, G3KH		 RH850/xnx
(e.g. RH850/C1H)		 -mv850e2v4 and ‑mloop
or
-mv850e3v5 and ‑mloop		 SIMD extension.
64-bit multiple load/store.
Loop extension.
H/W float (double precision).
Memory Protection.
Multi CPU core support.
Automotive products.

[99][103][108][109][1][101][53][105][106][107][110][114]

SoC solutions

[edit]

SoC IP cores

[edit]

In 1998, NEC started to provide the V850 family as an ASIC core, to expand its ASIC business.[115] In addition, both the V850E1 CPU core named Nx85E[116][117] and the V850E2 CPU core named Nx85E2,[118] are also used for expanding its ASIC products business.
Various SoCs utilize this core. In 2003, for example, Dotcast, Inc. used the NU85E core for a set top box receiver of digital datacasting based on the dNTSC (data in NTSC video method[119]). This core is fabricated with CB-10 0.25μm 5-layered-metal process technology.[120]: 9–10 

The NA85E2C core, which is developed using a 1.5 V 150 nm CB-12L (UX4L) fabrication process,[91][96] has many errata (4 pages appendix in preliminary architecture manual,[121]: 230–233  plus a further, 7-page restrictions document[122]), but which doesn't seem to matter, because this is a product with a long lifespan.

NEC also expanded production of a core using a 130 nm CB-130 (UX5) fabrication process,[91] cell-base IC.[123][124]

Synopsys DesignWare IP core for V850E was once announced,[125] but support has been discontinued.[126]

Name Core Cell-base
series		 Power
supply		 Node/
Gate L		 Fab.
proc.
[91] 		Freq.
MHz		 Type ICE Docs.
NA851C V851 CB-9VX 3.3 V 350 nm UC1 33 With peripheral [115][127]
NA853C V853 CB-9VX 3.3 V 350 nm UC1 33 With peripheral [115][128]
NA85E V850E1 CB-9VX 3.3 V 350 nm UC1 Bulk core [116]
NB85E V850E1 CB-9VX 3.3 V 350 nm UC1 66 Bulk core [129][130] [115][117][131]
NB85ET V850E1 CB-9VX 3.3 V 350 nm UC1 66 w/ Trace I/F [129][130] [115][131]
NB85E V850E1 CB-10 2.5 V 250 nm UC2 66 Bulk core [129][130] [131]
NB85ET V850E1 CB-10 2.5 V 250 nm UC2 66 w/ Trace I/F [129][130] [131]
NU85EA V850E1 CB-10VX 2.5 V 250 nm UC2 100 Bulk core [129][130] [131][132][133][134]
NU85ET V850E1 CB-10VX 2.5 V 250 nm UC2 100 w/ Trace I/F [129][130] [131][132][133][134]
NDU85ETV14 V850E1 CB-12L 1.5 V 150 nm/
130 nm		 UX4L w/ Trace I/F [129][130] [131][132][133]
NDU85ETVxx V850E1 CB-12M 1.5 V 150 nm/
130 nm		 UX4M w/ Trace I/F [129][130] [131][132][134]
NA85E2C V850E2 CB-12L 1.5 V 150 nm/
130 nm		 UX4L 200 w/ Trace I/F [112][135] [131][134]
NB85E2C V850E2 CB-12L 1.5 V 150 nm/
130 nm		 UX4L 200 w/ Trace I/F [112][135] [131][134]
V850E2x CB-130L 1.2 V 130 nm/
95 nm		 UX5L

[123][124]
Replaced by ARM946[136][113]

— — CB-90L 1.2 V 90 nm/
 UX6L Replaced by ARM946.[113]
In-house V850E2x UX6LF 1.2 V 90 nm/
 UX6LF Renesas internal use only ???
— — CB-65L 1.2 V 65 nm/
 UX7L Skipped.
Replaced by ARM1156.[113]
— — CB-55L 1.2 V 55 nm/
50 nm		 UX7LS Skipped.
Replaced by ARM Cortex-M3.
— — CB-40L 1.1 V 40 nm/
40 nm		 UX8L Replaced by ARM Cortex-M4.
In-house V850E3 RV40F 1.1 V 40 nm/
40 nm		 RV40F 320 Renesas internal use only ???

FPGA prototyping systems for SoC

[edit]

FPGA prototyping systems for V850E1, V850E2, and V850E2M core-based SoCs were intensively developed to expand the SoC business. They comprised a V850 CPU core LSI (TEG, or Test Element Group) board and FPGA add-ons. Most SoC products were for mobile equipments, because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC.[1][5][101] It is similar to the ARM architecture that is widely used for mobile gadgets.

  • Renesas (NEC): Microssp (2006)[113]
  • Renesas (NEC): Hybrid Emulator (2007)[140]
  • Renesas (NEC): PFESiP EP1 Evaluation Board (2008)[141]
  • Renesas (NEC): PFESiP EP1 Evaluation Board Lite (2008)[142]
  • Renesas (NEC): PFESiP EP3 Evaluation Board (2010): V850E2M CPU core, max. 266 MHz operation[143]

Strategic confusion

[edit]

Around 2011–2014, Renesas Electronics extensively expanded the V850E2 product line,[146][147] but this high-paced expansion brought much confusion. For example, as of 2018, some have requested that V850E2/xxn products be replaced with RH850/xnx ones.[148]

In addition, in 2012 Renesas started to intensively promote the migration from ten-year-old V850ES/Jx3 product lines to the newly produced V850E2/Jx4, such as for Ethernet and USB applications,[149][150] but the newer products are not listed on their website, as of 2018.[39]

Currently,[as of?] Renesas Electronics is designing a "dual" "lockstep" system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM,[151] either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction.

In addition, the NEC V60-V80 has several implementations of UNIX System V port product releases, one of which is "real-time UNIX RX/UX-832"[152] (here, 832 stands for the μPD70832 (V80), not V832). Its multiprocessor implementation is called MUSTARD (Multiprocessor Unix for Embedded Real-Time Systems), which can operate a maximum of 8 processors simultaneously, and its lockstep mechanism was dynamically configurable.[153]

In 2001, both NEC Corporation and Synopsys, Inc., announced they had agreed to promote the V850E as DesignWare IP core.[125][126] But as of 2018, the V850E is not listed on DesignWare libraries.[154]

Lucent Technologies and Texas Instruments once licensed the V850 and V850E SoC cores, respectively,[155][156][157][158] but those devices cannot be found.

In 2006, Metrowerks developed the CodeWarrior compiler for the V850, which was one of the main compilers for the V850,[159] but around 2010, they discontinued support.

Also in 2006, NEC did not give any roadmap for the V850 family as SoC cores.[113] The V850E2 core, developed in 2004, was described as the last, best core for SoC applications. However, NEC introduced ARM9 (arm v5) and ARM11 (arm v6), especially for mobile equipment. This decision suddenly decreased the net profit of LSI devices, because of the royalty for using ARM, and thus price competition with other ARM SoC providers. The sales revenue of "V850 total solutions", such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of V850 devices sold also suddenly decreased, because mobile equipment manufacturer were the major customers of V850E1 and V850E2 cores at that moment.[160]

In 2008, KMC (Kyoto Mictocomputer), which is one of the major and of the first providers of in-circuit emulators for the V850 family, announced "exeGCC" being updated from Rel. 3 to Rel. 4,[161] but it excluded the V850 from this updating list, which added PowerPC and ARM v7. KMC chose SH-4A and ARM v7, instead of V850 and RH850,[162] though it had been working closely with NEC and Renesas Electronics.[159]

The V850 CPU cores run uClinux,[163] but on October 9, 2008, Linux kernel support for the V850 was removed in revision 2.6.27.,[164] because NEC stopped its maintenance.[165][166][167] The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his new job was compiler design and never returned to Linux kernel maintenance.[168] This corporate decision prevented the possibility of porting to Android.[169] As of 2018, Renesas Electronics mainly focuses Linux kernel support on SH3/SH4 and M32R processors. [170][171][172][173][174]

Target software solutions

[edit]

Libraries

[edit]
C runtime startup routine (crt0.S) for the latest v850e3v5 microarchitecture is available.[176][177][178]

Operating systems

[edit]

V850 Operating systems are mostly real-time.

Some operating systems require a memory protection unit (MPU) to divide tasks (or threads) strictly for reliability and safety reasons. In such cases, the v850e2v3 (Gen. 3) microarchitecture, or above, is required.

ITRON based real-time OS

[edit]

ITRON is an open standard specification of real-time OS (RTOS), which is major in Japan. Its specification is defined under the leadership of Ken Sakamura, as a part of TRON project, the initialr I standing for "Industrial". Because the ITRON specification defines interface and skeleton only, each vendor has its own implementation.

  • Renesas:
    • RI850MP Real-time OS for V850E2M Dual Core[182]
    • RI850V4 V2 Real-time OS for RH850 family[183]
    • RI850V4 V1 Real-time OS for V850 family[184]
→ In 2003, on Rel. 1.3, V850 dedicated part bug was fixed.[185]
→ Kernel update history[186]

AUTOSAR, OSEK/VDX compliant real-time OS

[edit]

AUTOSAR is an open systems architecture of operating system for the automotive industry. Its purpose is to standardize electronic control units (ECU) for automotive engines. AUTOSAR is an upward compatible specification of OSEK/VDX, which is also a German consortium established in 1993.

In Japan, this research was started in 2006, as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009.[191] Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is a strategical product of Renesas Electronics. However, its documentation is only available in Japanese, as its main customer is Toyota Motor Corporation.

  • Renesas: RV850 (documents are in Japanese only)[192]
  • ETAS GmbH: RTA-OS RH850/GHS,[193] RTA-OSEK V850E/GHS[194]
  • Mentor Graphics (formerly Accelerated Technology, Inc.): Nucleus OSEK[195]
  • HighTec EDV-Systeme GmbH: EB tresos Safety OS[196]
  • Toppers Project: Open source TOPPERS/AUTOSAR[197]
  • eSOL: eMCOS AUTOSAR profile[198]

Other real-time OS

[edit]
  • SEGGER

Linux

[edit]
On October 9th 2008, Linux kernel support for V850 was removed in revision 2.6.27,[164] preventing the possibility of porting Android.[169]

Middleware packages

[edit]

Various middleware application softwares are provided from various vendors.

  • Renesas: SD Memory Card Control[212]

Software development tools

[edit]

Compilers and assemblers

[edit]

Most of the compilers, for both for the V850 family and the RH850 family, are exactly the same product, and extended ISA targets are controlled by command line options.[213][214]

Compilers for the V850 family and the RH850 family include:

  • Renesas:
    • C Compiler Package for V850 family[220]
      • CA850 C compiler for V850E1 and V850ES (v850e1 and/or v850es, a.k.a. Gen. 1)[221]
      • CX C compiler for V850E2M and V850E2S (v850e2v3, a.k.a. Gen. 3)
    • Software Package for V850 [SP850] for V850E2 (v850e2(v2), a.k.a. Gen. 2)[222]
    • CC-RH C compiler package for G3, G3K(H), G3M(H)[223]
  • HighTec EDV Systeme GmbH: HighTec Development Platform[230][231]

Disassemblers

[edit]

Usually, dis-assemblers are provided as a part of C compiler or assembler packages.

GUI based debuggers

[edit]

GUI based program debuggers are mainly provided for debugging of compiled source codes. Usually, it is used with instruction set simulators or in-circuit emulators.

  • Renesas:
    • ID850: For the combination of CA850 compiler and SM850 instruction set simulator.
    • ID850NW: For the combination of N-Wire based in-circuit emulators.
    • ID850QB: For the combination of probing-pod based emulator IEQUBE2
  • NDK (Naito Densei Kogyo Co. Ltd, Group): Operation started in 1950 as subsidiary of NEC.
    • NW-V850-32
  • GHS (Green Hills Software): Multi: General-purpose debugger.
  • Red Hat, Inc.: Insight (GDB-Tk): GUI front-end tightly combined with GNU Debugger.
  • Mentor Graphics (formerly Accelerated Technology, Inc.): code|lab Developer Suite[239]
  • By N-Wire based in-circuit emulator vendors:
    • KMC (Kyoto Microcomputer) and Midias Lab.: PARTNER[240]
    • Sohwa & Sophia Technologies:WATCHPOINT[241]
    • DTS INSIGHT (formerly YDC, Yokogawa Digital Computer): microVIEW-PLUS
    • Computex: CSIDE

Instruction set simulators

[edit]

Instruction set simulator, in other words, Virtual Platform is provided to perform debugging without equipment's hardware before testing on a real machine.

Automated code reviewers

[edit]

Automated code reviewer, in other words, source code analyzer qualify the level of completeness of written software source code. This method is classified as dynamic code analysis and static code analysis.

Dynamic code analyzers with simulators

[edit]
  • Renesas: TW850
TW850 Performance Analysis Tuning Tool is a general utility to improve effectiveness of software.[245]
  • Renesas: AZ850
AZ850 System Performance Analyzer is a utility for RX850 real-time operating system to evaluate effectiveness of application programs.[246]
  • Gaio Technology: Coverage Master winAMS[247]
Coverage Master winAMS is a source code coverage measurement tool.

Static code analyzers

[edit]
  • GHS (Green Hills Software): DoubleCheck ISA (Integrated Static Analysis) tool[248]
  • Rogue Wave Software, Inc: Klocwork[249]

IDE (Integrated Development Environments)

[edit]

IDE, Integrated Development Environment, is a framework to provide software development functions.

Hardware development tools

[edit]

ICE (In-circuit emulators)

[edit]

Most in-circuit emulators, such as Renesas's IE850 (formerly IECUBE2),[251] can be used for both the V850 family and the RH850 family, but may require firmware updating. The latest "trace function" of the JTAG (N-Wire[252]) based in-circuit emulator is upgraded from the N-Trace (single-ended signaling)[253] to the Aurora Trace (differential signaling).[254]

Full probing pod type

[edit]

Full probing pod type in-circuit emulator is sometimes called full ICE or legacy ICE.

  • Renesas IE850 (formerly IECUBE2)[251]
  • Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.)
    • Asmis brand for custom LSIs.[255]

ROM emulator type

[edit]
  • Lauterbach: ROM Monitor for V850[256]: 5 
  • KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-ET II (obsoleted)[257]

JTAG N-Wire and N-Trace type

[edit]

N-Wire and N-Trace[258][253][259][260] is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller),[261] primarily compiled by Philips N.V. (currently NXP Semiconductors). But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.[262]

  • Renesas
    • E1 Emulator:[263] USB 2.0 based affordable compact housing equipment.
    • PCMCIA N-Wire Card IE-V850E1-CD-NW[264]
  • Computex: PALMiCE3 V850[273]
  • Sohwa & Sophia Technologies: Universal Probe Blue[274] with WATCHPOINT debugger[241]
  • KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-Jet (obsoleted)[275]

Nexus and Aurora trace type

[edit]

Nexus or IEEE-ISTO 5001-2003 is a standard debugging interface for embedded systems.
Aurora is a high speed signal transfer specification. Its data link layer communications protocol is a point-to-point serial links, and physical layer is a high speed differential signaling.

Flash ROM programmers

[edit]

Because the V850 family is developed as a single chip microcontroller, every product integrates non-volatile memory. In its first stage, it was one-time programmable or UV EPROM type, but in V853, V850/xxn Series, and later, it becomes flash memory type.

Gang writers (gang programmers)

[edit]

A gang writer, or a gang programmer, is an old terminology for programmable ROM writers, or programmers. Its name comes from that it steals the binary code from one device, and write it to several others simultaneously. This read device is sometimes called a master device. For mass production use, a dedicated attachment board with "a set of sockets", i.e. "a gang", is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most gang writers accept ASCII-format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.

This method is suitable for mass production.

  • TESSERA Technology Inc.: Stick GANG Writer[278]

Programming service providers

[edit]

Flash ROM programming service providers exist in most countries.

  • Minato Holdings, Inc.
Minato Holdings, Inc. (in Japanese)[279] is a Japanese company that started as an automated test equipment vendor for memory LSIs. Nowadays, it provides flash ROM programming services for various devices, including V850 and RH850, with its own gang writers and full automatic device handler machines.

On board programming with ICE

[edit]

Most JTAG-based in-circuit emulators have an on board flash ROM programming function via a debug port,
which may be according to IEEE standard 1532-2002, a standard for in-system configuration of programmable components.[280]

Direct connection via RS-232C

[edit]

If the target board has a RS-232C connector and a transceiver (driver/receiver) IC, such as ICL32xx,[281] for the UARTx peripheral function of V850 device, flash ROM programming with a directly connected PC might be available (depends on devices[282]: 16–24  ). The Renesas Flash Programmer software V2[283] or V3[284] is required.

Dedicated on board programmer

[edit]

On-board programming is also available via UARTx or CSIx+HS peripherals on V850 devices by using dedicated programmer hardware (depends on devices[282]: 16–24 ).

Ancient PROM writers

[edit]

To program V851[286]: 11, 14–20  and V852,[287]: 11, 14–20  an ancient PROM programmer with dedicated adapter is required.

  • Renesas PG-1500 (obsoleted)
Renesas PG-1500[288] is a programmable ROM writer compatible with 27C1001A[289] devices, UV EPROM, or one-time PROM (OTP). This writer reads a silicon signature[290][291] from each device before programming, by asserting 12.5 V to the A9 (address #9) terminal. It must NOT be used for modern flash ROM burning.

Gray zone tools

[edit]

Some gray zone hacking tools exist for V850 on car dashboards.

  • VVDI PROG.:

Evaluation boards

[edit]
  • Renesas: TK-850: The name is influenced by nostalgia for the TK-80 8080-based training kit.

See also

[edit]

References and notes

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

V850

View on Grokipedia
from Grokipedia
The V850 is a 32-bit reduced instruction set computing (RISC) architecture developed by NEC Electronics for single-chip microcontrollers targeted at embedded control systems.[1] Introduced in 1995 as a successor to the 78K series, it provides a migration path from 8-bit and 16-bit processors while delivering higher cost-performance ratios for real-time applications.[1] The V850 CPU core, derived from the V800 series RISC technology, employs a five-stage pipeline (instruction fetch, decode, execute, memory access, and write-back) that enables most of its 74 instructions to complete in one clock cycle.[1] It features 32 general-purpose 32-bit registers, support for byte, half-word, and word data formats, and specialized instructions for saturation arithmetic, bit manipulation, and fast multiply/divide operations (e.g., 16×16 to 32-bit results in 1-2 clock cycles).[1] The architecture addresses up to 16 MB in program space and 4 GB in data space, with load/store operations, arithmetic/logical functions, and branching capabilities optimized for efficiency.[1] Now maintained by Renesas Electronics following the 2010 merger with NEC Electronics, the V850 family spans multiple generations, including variants like V850E and V850ES, with performance scaling from 20 MIPS to over 300 MIPS at low power levels (e.g., under 0.35 mA in active mode at 1 MHz).[2] It incorporates peripherals such as timers, serial interfaces, and ADCs, making it suitable for automotive applications (e.g., engine control units and ABS systems), office equipment (e.g., hard disk drives and printers), and factory automation (e.g., NC machine tools).[1] The architecture has evolved into the RH850 series as a modern refresh, but V850 remains in use for legacy and specialized embedded designs.

Introduction

Overview

The V850 is a 32-bit reduced instruction set computing (RISC) central processing unit (CPU) architecture developed by NEC Electronics (now Renesas Electronics) for embedded microcontrollers. Introduced in 1995, it serves as a successor to the 78K series, providing a performance upgrade of approximately 15 times while maintaining compatibility as a migration path for existing designs.[3] Key features include a load/store architecture with 32 general-purpose registers (r0 to r31) and a Harvard design utilizing separate instruction and data buses. It supports a linear 4 GB address space for data and up to 16 MB for program memory, enabling efficient handling of embedded tasks. The architecture incorporates a five-stage pipeline—fetch, decode, execute, memory access, and writeback—that allows most instructions to complete in one clock cycle, emphasizing real-time processing with deterministic response times.[3] Later variants operate at clock speeds up to 100 MHz, delivering high performance for resource-constrained environments. The V850 has been widely positioned in the microcontroller market for its reliability and low power consumption, finding extensive use in automotive, industrial control, and consumer electronics applications. It has evolved into enhanced variants such as the V850E and V850ES to address advanced requirements.[4][5]

History and Development

The V850 architecture originated from NEC Electronics' efforts in the early 1990s to advance beyond its 8/16-bit 78K microcontroller series, aiming for a scalable 32-bit RISC design suitable for embedded applications requiring higher performance and real-time processing. Developed as part of the broader V series evolution from the V800 family, the initial V850 core was announced in 1994 to address growing demands for efficient, low-power computing in consumer and industrial systems.[6][7] Key milestones marked the architecture's progression: the first single-chip V850 microcontroller was introduced in April 1996 with the V850E variant, enhancing performance through refined RISC principles for broader compatibility and efficiency. In 1998, the V850ES series added on-chip debug support, facilitating easier development for complex embedded designs. The V850E2 core followed in 2005, introducing superscalar capabilities for up to 1.6 times the performance of prior generations, while variants like V850E2S emerged in the late 2000s and early 2010s to support scalable integration in system-on-chips. These enhancements emphasized functional safety, with later generations analyzed for ISO 26262 compliance to meet automotive standards.[8][5][5] Corporate transitions shaped the V850's trajectory: NEC's microcontroller business merged into Renesas Technology in 2002 following the integration of Hitachi and Mitsubishi semiconductor operations, and in 2010, NEC Electronics fully merged with Renesas Technology to form Renesas Electronics, which continued V850 development under a unified portfolio. Design motivations centered on RISC simplicity for maximum performance with minimal hardware complexity, enabling real-time capabilities and alignment with emerging standards like AUTOSAR through verified MCAL drivers in V850E2 series. Renesas maintains ongoing support for V850 as of 2025, including compilers and emulators for legacy and new implementations.[9][10][5][11]

Architecture

Core Design

The V850 core employs a 5-stage superpipeline architecture consisting of instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM), and writeback (WB) stages, enabling most instructions to execute in a single clock cycle while processing up to five instructions concurrently across the pipeline.[1] Branch instructions are resolved in the ID stage, typically requiring two clock cycles, with no advanced dynamic branch prediction; instead, the architecture relies on static prediction and pipeline flushes for control transfers.[12] Hazard resolution is handled through hardware interlocks that detect data and structural dependencies, inserting stalls as needed—such as a two-cycle delay for load-use hazards—to prevent incorrect execution without software intervention.[1] The register file comprises 32 general-purpose 32-bit registers labeled r0 to r31, which serve as the primary storage for operands and addresses in the load/store RISC design. The r0 register is fixed as a zero register, always reading as 00000000H to simplify operations like clearing or masking.[12] Among these, dedicated roles are assigned to specific registers for system functions: r3 acts as the stack pointer (SP) for managing function calls and interrupts, r4 as the global pointer (GP) for efficient access to global data, r30 as the element pointer (EP) for structured data operations, and r31 as the link pointer (LP) for return addresses. In addition to the general-purpose registers, the core includes the program counter (PC), which holds the address of the current instruction, and various system registers such as the program status word (PSW) for flags and interrupt enable bits.[1] The memory model follows a Harvard architecture, separating instruction and data accesses to optimize performance, with a 32-bit linear address space supporting up to 4 GB for data and typically 16 MB to 64 MB for program memory depending on the implementation.[1] Memory is byte-addressable in little-endian format, allowing aligned accesses to bytes (8 bits), halfwords (16 bits), and words (32 bits), with unaligned accesses generating exceptions to ensure data integrity.[12] Addressing modes include register-direct, immediate, PC-relative, and register-indirect with displacement, where the effective address for based modes is calculated as the contents of a base register plus a signed offset. Some variants unify the address spaces for simplified programming, but the baseline maintains separation for efficiency.[1] Interrupt handling in the V850 core supports vectored interrupts for both maskable (via external INT pins or internal peripherals) and non-maskable (NMI) types, with the processor automatically saving the PC and PSW to dedicated registers (EIPC/EIPSW for maskables, FEPC/FEPSW for NMIs) before jumping to the handler address.[12] Maskable interrupts are controlled by the PSW's ID bit and an external interrupt controller, while NMIs have higher priority and cannot be disabled, ensuring critical response. The architecture achieves low-latency handling through direct vectoring and minimal pipeline disruption, typically acknowledging interrupts within a few cycles after enabling.[1] Clock and reset mechanisms integrate support for an internal high-speed oscillator (typically around 8 MHz) as a fallback clock source, allowing the core to operate independently of external crystals during startup or clock failures.[13] Power-on reset (POR) initializes the PC to 00000000H and PSW to 00000020H (with interrupts disabled), clearing the register file and stabilizing the pipeline before execution begins, while external reset pins provide manual control.[12] Watchdog timer integration enables periodic refresh to prevent hangs, generating an internal reset signal on overflow if not serviced, often configurable in reset or interrupt modes for reliability in embedded environments.[14] For based addressing modes, the effective address $ EA $ is computed as:
EA=rb+disp EA = r_b + \text{disp}
where $ r_b $ is the 32-bit base register value and disp is a signed offset of 16 bits (disp16) for short formats or effectively 32 bits via combinations in extended modes.[1]

Instruction Set

The V850 instruction set architecture (ISA) is a load/store RISC design featuring a total of 74 base instructions, optimized for embedded applications with support for both 16-bit and 32-bit instruction lengths to balance code density and performance.[1] All instructions execute in a 5-stage pipeline, typically completing in one clock cycle per stage, and operate on 32 general-purpose registers while adhering to a Harvard architecture separating program and data spaces.[3] The ISA emphasizes simplicity and efficiency, with no condition codes updated by arithmetic operations unless explicitly specified, enabling compiler-friendly optimizations. Addressing modes in the V850 ISA include register-direct for fast operand access, immediate values embedded in the instruction (up to 16 bits), PC-relative for branches and jumps (displacements of 9 or 22 bits), and register-indirect with scaling support via based addressing. Based addressing comes in two types: Type 1 uses an arbitrary register plus a 16-bit displacement for general memory access, while Type 2 employs the stack pointer (r30) with 7- or 8-bit displacements for stack-relative operations; bit addressing extends based modes to target individual bits in memory.[1] These modes facilitate efficient load/store operations without complex indexing hardware, supporting byte, halfword, word, and doubleword data sizes. Key instruction categories encompass arithmetic operations such as ADD (add register to register), SUB (subtract), and MULH (16x16 multiply producing 32-bit high result); logical instructions including AND, OR, and SHL (logical shift left); branch instructions like BR (unconditional PC-relative jump) and conditional variants (e.g., BNE for branch if not equal); and load/store instructions such as LD.W (load word from memory to register) and ST.W (store word from register to memory).[3] Bit manipulation instructions like SET1 (set bit in memory) and TST1 (test bit) provide direct support for peripheral control common in embedded systems. The ISA organizes these into 10 formats, with 16-bit formats for simple register-register or short immediate operations and 32-bit formats for extended immediates or three-operand instructions. Opcode encoding uses a 32-bit word-aligned structure, with major fields allocating 4 to 6 bits for the primary opcode, 5 bits each for source and destination registers (r0 to r31), and the remainder for immediates, displacements, or sub-opcodes. For instance, Format I (16-bit register-register arithmetic) dedicates bits 15-10 to the opcode and bits 9-4/4-0 to registers, while Format VI (32-bit three-operand with immediate) uses bits 31-26 for opcode, bits 25-21 and 20-16 for registers, and bits 15-0 for a 16-bit immediate. The following table illustrates encoding examples for select arithmetic operations in Format I and VI:
InstructionFormatEncoding (Binary, MSB to LSB)Description
ADD r1, r2I (16-bit)00111 r1(5bits) r2(5bits)Adds r1 to r2, result in r2
SUB r1, r2I (16-bit)00110 r1(5bits) r2(5bits)Subtracts r1 from r2, result in r2
ADDI #imm16, r1, r2VI (32-bit)11010 r1(5bits) r2(5bits) imm16Adds 16-bit immediate to r1, result in r2
These encodings ensure dense packing while maintaining RISC orthogonality.[1] Exception handling is supported through dedicated instructions including TRAP #n (software exception with vector n, triggering an interrupt-like handler), EI (enable interrupts by clearing the ID flag in PSW), and DI (disable interrupts by setting the ID flag). The RETI instruction restores the program counter and processor status word from exception registers (EIPC/EIPSW for general exceptions or FEPC/FEPSW for fast interrupts), ensuring atomic context switching.[3] The V850 ISA maintains backward compatibility across family generations, allowing software developed for earlier cores to run on later implementations without modification, and evolved from the V810 architecture as its primary precursor, which was phased out in the 1990s in favor of V850 enhancements.[1]

Variants and Extensions

The V850 architecture evolved through several generations, each introducing enhancements to performance, integration, and functionality while maintaining upward compatibility at the object code level. The first generation, introduced in 1994, featured the base RISC core with a 5-stage pipeline and operated at speeds up to 20 MHz, delivering approximately 23 MIPS.[15] This core emphasized high cost-performance for embedded applications, supporting 74 instructions including load/store operations, arithmetic, and basic multiply/divide capabilities.[16] In 1996, the V850E variant enhanced the pipeline for better throughput and added support for instruction and data caches to reduce memory access latency, with clock speeds reaching up to 50 MHz.[17] These improvements enabled more efficient handling of complex tasks in microcontrollers, while preserving the 32-bit RISC foundation with 32 general-purpose registers.[12] The V850ES, launched in 1998, built on this by incorporating a JTAG debug interface and real-time trace capabilities for improved development and debugging in embedded systems.[18] Operating at up to 34 MHz, it also prioritized low EMI noise and included DMA support for data transfer efficiency.[15] The V850E1 and V850ES1 variants, introduced in the early 2000s, refined multiplier units for faster 16×16 and 32×32 operations (completing in 1 clock cycle) and integrated advanced DMA controllers to offload CPU tasks.[12] Clock speeds scaled to 150 MHz, yielding up to 215 MIPS, with non-blocking load/store instructions to minimize pipeline stalls.[15] By 2005, the V850E2 introduced a dual-issue superscalar pipeline, allowing up to two instructions per cycle (IPC of 2), and supported clock speeds up to 200 MHz along with an optional floating-point unit (FPU) for numerical computations.[19] This generation featured a 7-stage pipeline and 128-bit instruction fetch for higher throughput in demanding applications.[15] The V850E2S, released around 2010, offered a scalable core optimized for system-on-chip (SoC) designs, with security extensions including memory protection mechanisms and support for AES encryption in associated microcontroller variants.[20] It maintained the superscalar architecture while adding processor protection for system registers and enhanced exception handling via PSW bits for trusted execution environments.[20] Additional extensions across variants include optional SIMD instructions for signal processing tasks, introduced in later models like the V850E2H, and peripheral integrations such as CAN and Ethernet controllers in MCU implementations for networking and automotive use. Performance across these variants can be estimated using the formula MIPS = clock speed (in MHz) × IPC, where IPC reaches up to 2 in the V850E2 and later due to dual-issue execution; for example, the V850E2 at 200 MHz achieves approximately 400 MIPS under optimal conditions.[15]

Power Efficiency Features

The V850 architecture incorporates several mechanisms to achieve low power consumption, essential for embedded systems in battery-operated and automotive applications. Central to these is dynamic frequency scaling, enabled through multiple clock sources including a main oscillator (typically 4 to 16 MHz), a sub-oscillator (32.768 kHz), and internal low-speed (240 kHz) and high-speed (8 MHz) options, allowing the CPU clock to vary from as low as 32 kHz up to 100 MHz in later variants. Clock gating is implemented in standby modes to halt clock signals to the CPU and peripherals, preventing unnecessary switching activity and reducing dynamic power dissipation. These features follow the fundamental power equation for CMOS circuits, $ P = C V^2 f $, where $ P $ is power, $ C $ is effective capacitance, $ V $ is supply voltage, and $ f $ is frequency; by minimizing $ f $ and gating clocks, the V850 optimizes energy use without compromising functionality.[21][22] Standby and sleep modes further enhance efficiency, including IDLE modes that stop the CPU and peripheral clocks while maintaining the main oscillator (consuming 1.6 to 3.3 mA typically), STOP mode that halts the main oscillator and relies on the sub-clock (7.5 to 15.5 µA), and sub-IDLE mode for ultra-low operation (20 to 25 µA). Wake-up is facilitated by interrupts, non-maskable interrupts (NMI), or watchdog timers, ensuring rapid resumption from low-power states. Power domains separate the core supply from peripherals and I/O ports, allowing independent voltage scaling (typically 2.2 to 5.5 V) and reducing overall leakage; this design also mitigates noise through dedicated capacitance insertion. In active mode, power draw is approximately 0.35 mA/MHz, translating to 1 to 2 mW at 1 MHz under 3 V conditions, while standby modes achieve less than 1 µA, representing a significant improvement over predecessors like the 78K series, where V850 variants offer about one-fifth the consumption at equivalent performance (e.g., 1.1 mA/MIPS versus 9.2 mA/MIPS).[21][22][2] Architectural techniques contribute to power savings by minimizing execution stalls and overhead. Later generations, such as the V850E2, include dedicated loop instructions (e.g., counter-based CT0/CT1) that enable near-zero-overhead looping for repetitive tasks common in embedded control. These optimizations ensure high instructions-per-cycle efficiency, indirectly lowering power by shortening active execution time. For automotive use, the low-power modes comply with functional safety standards like ISO 26262, supporting reliable wake-up and reduced energy in always-on systems such as engine control units. Overall, these features enable active power in the 10 to 50 mW range at low frequencies (e.g., 38 mW at 20 MHz and 2.5 V), a roughly 50% reduction compared to equivalent 78K implementations in similar applications.[23][22][2]

Applications and Implementations

Embedded Systems

The V850 architecture has been extensively applied in automotive embedded systems, particularly in engine control units (ECUs) and body control modules, where its real-time processing capabilities support critical functions such as antilock braking systems (ABS) and dashboard controls.[12][5] For instance, V850 processors were integrated into Toyota Camry ECUs during the 2000s, enabling reliable electronic throttle control and other vehicle dynamics management.[24] Certain V850 variants, such as the P-series, have undergone analysis for compliance with ISO 26262 functional safety standards, supporting Automotive Safety Integrity Levels (ASIL) up to B and D in safety-critical applications.[5] In industrial embedded systems, V850-based devices power factory automation equipment, including industrial robots and numerical control (NC) machines, providing deterministic real-time performance essential for tasks requiring sub-millisecond response times, such as motion control in motor drives and programmable logic controllers (PLCs).[12] These implementations leverage the architecture's low-power RISC core to ensure reliable operation in harsh environments, contributing to efficient production lines in manufacturing settings.[25] Consumer electronics represent another key domain, with early adoption by NEC in office equipment like copiers, printers, and facsimiles, where V850's balanced performance and power efficiency facilitated compact, high-speed document handling systems.[12] In audio-visual (AV) equipment, the architecture supported embedded control for multimedia devices, emphasizing seamless integration in home and professional setups.[25] Applications in medical and aerospace sectors utilize V850's low-power features for sensor interfaces and monitoring systems, such as portable diagnostic devices and avionics peripherals, where reliability and energy efficiency are paramount.[25] During the 2000s, Renesas MCU families including V850 held a significant position (nearly one-third worldwide) in the Japanese and Asian automotive markets, though adoption declined after 2015 as Renesas shifted focus to the successor RH850 family.[26][25]

SoC and IP Cores

The V850 architecture is commonly integrated into system-on-chip (SoC) designs as a central processing core combined with essential peripherals to form single-chip microcontrollers suitable for embedded applications. These SoCs typically incorporate the V850 CPU alongside components such as analog-to-digital converters (ADC), pulse-width modulation (PWM) timers, controller area network (CAN) interfaces, and Ethernet controllers, enabling efficient handling of real-time control tasks in compact packages. For instance, the V850E2/Mx4 series features a DMA controller, timer arrays for PWM generation, UART and CSI serial interfaces, CAN modules, ADCs, and USB controllers, all unified on a single die to support data-intensive operations without external dependencies.[25] Similarly, variants like the V850E2/ML4 include dedicated Ethernet controllers for network connectivity, facilitating TCP/IP stack implementation directly on the chip.[27] Licensable V850 IP cores, particularly the V850E and V850E2 variants, are available as soft cores for integration into custom ASICs, providing designers with a reusable RISC processor block that supports standard bus interfaces such as AMBA AHB for seamless connectivity with peripherals and memory subsystems. These IP blocks are offered by Renesas (formerly NEC Electronics) with configurable hardware and software macros, allowing adaptation to specific SoC requirements while maintaining compatibility with the V850 instruction set. In automotive SoCs, the V850ES/SJ3 core exemplifies this integration, pairing the processor with IEBus interfaces, serial communication units, timers, ADCs, and DACs for vehicle network management.[28][29] Furthermore, these SoCs often include on-chip flash memory capacities up to 2 MB, as seen in high-end V850E2/MN4 models, which utilize scaled-down processes for enhanced density and performance.[30] Customization of V850-based SoCs spans multiple semiconductor process nodes, from 0.18 µm for legacy designs to advanced 40 nm technologies, enabling scalability in power consumption and die size for diverse applications. The cores support parameterizable features like bus width, address mapping, and the number of master/slave interfaces, facilitating tailored implementations. For validation, HDL models of the V850 IP are compatible with FPGA platforms from Xilinx and Altera (now Intel), allowing pre-silicon prototyping and system-level testing via synthesizable Verilog or VHDL representations.[28] The development workflow for custom V850 SoCs follows a standard ASIC path, starting from register-transfer level (RTL) design, through simulation and verification using provided test benches and JTAG debug support, to physical design and tape-out at GDSII stage, supported by Renesas' MICROSSP infrastructure for rapid integration.[28]

Specific Device Examples

The V850 architecture has been implemented in various microcontroller products tailored for specific applications, with notable examples including the V850E2/PJ series for automotive control systems. These devices feature dual-core lockstep operation for functional safety, supporting up to 128 MHz CPU clock speed, 1 MB flash memory, and 80 KB RAM, along with integrated CAN and FlexRay interfaces for vehicle networking.[31][32] For industrial applications, the V850ES/Fx3 series provides Ethernet connectivity and is designed for real-time control, offering up to 80 MHz operation, 256 KB flash, and peripherals such as timers and serial interfaces, though it is now recommended only for existing designs.[33][34] The V850E2S/MA1 series targets low-pin-count sensor applications with ultra-low power consumption, operating at 48 MHz, featuring minimal I/O pins and optimized for battery-powered devices in embedded sensing.[35][36] Earlier lines include initial V850 variants without the "E" enhancement, which lacked advanced power management and were phased out by the early 2000s.[7]
Device SeriesClock SpeedMemory (Flash/RAM)Key PeripheralsProcess Node
V850E2/PJUp to 128 MHz1 MB / 80 KBCAN, FlexRay90 nm
V850ES/Fx3Up to 80 MHz256 KB / 24 KBEthernet, UART130 nm
V850E2S/MA148 MHz256 KB / 16 KBTimers, ADC90 nm
As of 2025, V850-based devices remain in production for legacy support and maintenance of existing systems, but Renesas recommends transitioning to the RH850 family for new designs due to enhanced performance and functional safety features.[34][5]

Software Ecosystem

Operating Systems and Middleware

The V850 architecture, primarily targeted at embedded applications, relies on real-time operating systems (RTOS) designed for deterministic performance and low resource overhead. Renesas provides the RI850V4, a μITRON4.0-compliant RTOS optimized for V850-based microcontrollers, which includes core features such as task management for scheduling multiple processes and semaphore mechanisms for synchronization and resource control.[37][38] Third-party RTOS options include SEGGER's embOS, a priority-based multitasking kernel ported to V850, V850E, and V850E2 cores, offering compact footprints suitable for resource-constrained embedded devices.[39] Middleware for V850 encompasses communication and storage solutions, such as TCP/IP protocol stacks for networked applications and CAN drivers for automotive bus interfacing, all provided by Renesas to operate within the limited memory of V850 MCUs. File system support includes FAT-compatible implementations for managing data on flash or external storage.[40][41] Software for V850 emphasizes compliance with safety standards, including MISRA C guidelines for code quality in automotive development and functional safety certifications aligned with ISO 26262 for risk reduction in vehicle systems.[42] Integration is facilitated through board support packages (BSPs) from Renesas and vendors like SEGGER, which handle hardware initialization, peripheral drivers, and OS bootstrapping for specific V850 evaluation boards and MCUs.[43][41]

Libraries and Development Frameworks

The V850 architecture benefits from a range of standard libraries integrated into its development toolchains, primarily provided by Renesas and third-party compiler vendors. The C runtime library (CRT), included in compilers such as the CA850 from Renesas and the IAR Embedded Workbench for V850, offers essential functions for embedded applications, including mathematical operations like sine and cosine computations via sin() and cos(), as well as string manipulation routines for memory-efficient handling of character data.[44][45] These libraries are optimized for the V850's 32-bit RISC core, ensuring low overhead in resource-constrained environments. Renesas also supplies peripheral-specific libraries tailored for V850 variants, which abstract hardware interactions for timers and I/O ports to simplify application development.[46] Real-time libraries for V850 emphasize deterministic operation in embedded systems, with Renesas providing interrupt handling routines and DMA APIs through its peripheral macro driver packages. For instance, the V850ES/Fx2 peripheral macro driver includes APIs for configuring interrupt sources, such as timer-triggered events, allowing developers to register handlers that respond to flags set by hardware or software triggers.[47] DMA control libraries, detailed in application notes for V850E2/ML4 devices, enable efficient data transfers without CPU intervention, using functions to set up channels triggered by peripherals like timers, thus supporting real-time data acquisition in applications such as signal processing.[48] In automotive contexts, V850 supports AUTOSAR-compliant frameworks through Renesas' basic software (BSW) modules, which include communication (COM) stacks for CAN bus messaging and non-volatile RAM (NVRAM) managers for persistent data storage. These modules, part of the microcontroller abstraction layer (MCAL), are available as standalone packages or integrated stacks for V850E2 series devices, facilitating compliance with ISO 26262 safety standards by providing standardized interfaces for ECU software.[5] Device drivers for V850 peripherals are typically implemented via Renesas-supplied APIs, covering components like analog-to-digital converters (ADC), timers, and UART interfaces. For UART communication on V850ES/Jx3-L devices, the asynchronous serial interface A (UARTA) driver uses APIs such as UARTA_Init() to configure baud rates and UARTA_SendData() for transmission, enabling reliable serial data exchange with external devices. Similar APIs exist for ADC modules, where functions like ADC_StartConversion() initiate analog sampling triggered by timers, and for timer units, allowing precise interval-based operations essential for real-time control.[49] Portability across Renesas architectures is enhanced by migration tools and compatibility layers designed for transitioning from older 78K series to V850. Renesas' development environment migration guides provide option mappings between compilers like CA78K0 (for 78K) and CA850 (for V850), including code conversion utilities that handle differences in instruction sets and memory models to minimize porting efforts.[50] Open-source support for V850 is limited but includes GCC toolchains ported by Renesas and community efforts, offering a free alternative for building and linking libraries without proprietary dependencies. The Renesas V850 GCC toolchain (version 14.01) supports ELF object formats and includes runtime libraries compatible with standard C functions, enabling developers to compile peripheral drivers and real-time code on open platforms.[51]

Compiler and Debugger Tools

The primary compilers for the V850 architecture are provided by Renesas through the C Compiler Package for V850 Family, which includes the CA850 compiler and assembler package as well as the CX compiler. The CA850 supports ANSI-compliant C (C89 and a subset of C99) for developing ROM-based embedded systems, featuring optimizations that reduce code size and improve execution speed through techniques such as loop unrolling and dead code elimination.[11] It integrates with the CS+ integrated development environment (IDE) for seamless project management and supports command-line usage. Additionally, an open-source port of the GNU Compiler Collection (GCC) is available for V850, enabling C/C++ compilation with standard GCC options, including optimization levels from -O0 (no optimization) to -Os (optimize for size), allowing developers to balance performance and memory constraints in embedded applications.[52] Assemblers for V850 are bundled within the Renesas toolchain, notably the AS850 assembler in the CA850 package, which handles V850-specific inline assembly and generates object files compatible with the linker. This tool supports the full V850 instruction set, including extensions for variants like V850E, and facilitates low-level programming for performance-critical sections. The GNU Assembler (as) from the Renesas-provided GCC port also supports V850 assembly, offering cross-platform compatibility for generating ELF-format object code.[11][52] Disassemblers for V850 binary analysis are integrated into Renesas' CS+ IDE, which includes utilities for opcode decoding and reverse-engineering executable files to reveal instruction sequences and memory layouts. These tools enable detailed examination of compiled binaries, supporting tasks like firmware verification and optimization review without hardware access. The GNU Binary Utilities (objdump) in the V850 GCC port provides similar disassembly capabilities, outputting human-readable assembly from object files with options for symbol table inclusion.[53][52] Debugging software for V850 primarily revolves around Renesas' CS+ IDE paired with the E1 on-chip emulator, a GUI-based tool that supports source-level debugging features such as breakpoints, watchpoints, and real-time variable monitoring. This setup allows non-intrusive execution tracing and memory inspection during development. The GNU Debugger (GDB) port for V850, available through Renesas' open-source toolchain, offers command-line and graphical interfaces for stepping through code, examining registers, and handling interrupts, often integrated with Eclipse-based environments like e² studio.[54][55][52] Instruction set simulators (ISS) for V850, such as the one embedded in CS+, provide cycle-accurate modeling of the processor core, peripherals, and interrupts, enabling software validation without physical hardware. These simulators support full-speed execution simulation and performance profiling to predict timing behaviors in embedded systems.[53] Code analyzers for V850 include static tools like PC-Lint, which integrates with the CA850 and GCC compilers to detect potential issues such as uninitialized variables and type mismatches through linting of source code. Dynamic analysis is facilitated via simulator traces in CS+, capturing runtime execution paths and memory accesses for post-simulation review and bug identification.[11][53]

Hardware Development Support

Evaluation and Prototyping Tools

Renesas provides evaluation boards for V850 development through its Starter Kit series, designed to facilitate initial assessment of microcontroller features and performance. The Starter Kit for V850E2/FG4-L, for instance, integrates an onboard E1 on-chip debugger via a 14-pin connector for seamless debugging and flash programming, alongside user-friendly peripherals such as multiple LEDs—including a high-brightness white LED, four blue LEDs, and an RGB LED—for visual output testing, and a potentiometer serving as an analog input sensor on the ADAA0I0 channel.[56] These components enable developers to prototype basic embedded applications without additional hardware, supporting power supply from the debugger or external sources up to 5V. Similarly, the V850E2/Px4 Starter Kit offers comprehensive peripheral integration for automotive-oriented evaluation, featuring a Nexus debug interface through a 20-pin connector compatible with tools like MiniCube, eight LEDs connected to port P2 for status indication, a 2x12 character LCD for display testing, four push buttons for input simulation, and two potentiometers for analog-to-digital conversion benchmarking on channels 21 and 22.[57] It also includes communication interfaces such as dual CAN, LIN, UART, dual FlexRay, SPI, and SENT, with flexible power options including 12-15V input and switchable I/O voltages, allowing for hardware-software co-verification in motor control and network scenarios.[57] V850 evaluation tools incorporate standard debug features like JTAG and Nexus interfaces for real-time monitoring and control, with trace ports enabling performance analysis through signal capture and event tracing.[58] These interfaces support use cases such as peripheral benchmarking—e.g., assessing CAN or LIN throughput—and hardware-software co-verification by allowing synchronized execution traces during integrated system testing.[59] The QB-V850MINI, for example, leverages Nexus for broad compatibility across V850E2 variants, facilitating trace-based validation without disrupting target operation.[60] By 2025, all V850 evaluation boards are fully discontinued with no availability through major Renesas distributors like DigiKey and Avnet. Support is limited to technical documentation, and Renesas recommends migration to RH850 series tools for new designs.[61][62]

Emulation and Programming Devices

In-circuit emulators (ICE) for the V850 architecture provide essential hardware support for debugging embedded systems, enabling real-time monitoring and control without fully intruding on the target application's execution. Renesas offers full-spec emulators such as the IECUBE and IE850 series, which connect to V850 microcontrollers via JTAG or N-Wire interfaces for non-intrusive access. These tools support features like breakpoint setting, register inspection, memory mapping, and performance measurement, allowing developers to analyze system behavior in situ. For instance, the IECUBE delivers high-performance debugging with self-testing capabilities to detect hardware faults, while the IE850 adds versatility through interchangeable emulation pods compatible with V850E2M variants.[63][64] Note that these emulators are discontinued products, with support limited to documentation; migration to RH850-compatible tools is recommended for ongoing development.[61] Trace capabilities in V850 emulation hardware facilitate detailed program flow analysis by capturing execution histories. The IE850 emulator incorporates Nexus and Aurora trace protocols, supporting buffer sizes up to 512 KB (expandable to 2.25 GB with optional memory boards) for instruction and data tracing. This enables coverage analysis and time measurement, critical for optimizing real-time embedded applications where cycle-accurate profiling is required. ROM emulators, integrated within these ICE pods, allow substitution of the target MCU with emulation memory for rapid prototyping and testing of code before final hardware integration.[64][65] Programming devices for V850 focus on efficient flash memory management, supporting erase, program, and verify operations for on-chip NOR flash common in these MCUs. The Minicube (QB-V850MINI series) serves as a compact, USB-based tool that combines on-chip debugging with flash programming, ideal for in-system updates and small-scale development.[66] Similarly, the E1 and E20 emulators, when used with Renesas Flash Programmer (RFP) software, provide dedicated programming functions via JTAG/N-Wire, handling full flash cycles for V850 devices in both development and production environments.[67] For mass production, standalone programmers like the PG-FP5 enable socket-based flashing of V850 MCUs, with support for verify operations to ensure data integrity post-programming.[68] These programming tools are also discontinued, with Renesas advising transition to newer platforms.[61] Early non-flash V850 variants relied on legacy PROM writers for programming external or on-chip programmable read-only memory, though these have largely been supplanted by flash-based solutions in modern tools. Integration of emulation and programming hardware with IDEs, such as CS+, streamlines workflows by automating debug-flash cycles, from code download to verification, reducing development time for V850-based systems.[69]

Integration with FPGA Systems

The integration of V850 microcontrollers with field-programmable gate arrays (FPGAs) enables enhanced system flexibility, particularly in prototyping, peripheral expansion, and high-speed processing tasks that complement the V850's embedded RISC capabilities. This approach leverages FPGA reconfigurability to implement custom interfaces, bridges, or accelerators alongside V850 cores, facilitating rapid development of system-on-chip (SoC) designs without full ASIC fabrication. Such integrations are common in automotive, industrial, and signal processing applications, where FPGAs handle parallel or timing-critical operations while the V850 manages control logic.[70] A prominent example involves embedding the V850's PCI host bridge macro into an FPGA to provide PCI Rev. 2.1 connectivity at 33 MHz. This macro, designed for V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 devices, interfaces the V850 CPU bus (32-bit width) with external PCI devices, such as IDE controllers or hard disk drives, while supporting SDRAM memory access (up to 64 MB in configurations with two 16M × 16 devices). In a typical setup using an Altera EP20K200EQC240-1X FPGA, the FPGA decodes chip-select signals from the V850, manages bidirectional PCI signals (e.g., AD[31:0], CBE[3:0], FRAME#), and handles interrupts from up to three PCI sources. Burst transfers of up to eight doublewords (256 bits) are supported, with adjustable SDRAM latencies up to 7,650 ns to optimize performance; evaluation boards incorporate this for PIO and DMA modes in storage applications, achieving efficient data transfers like 4096-byte sectors. Design considerations include 3.3-V PCI I/O standards and equal-length wiring for signal integrity.[70] In signal processing contexts, V850 devices preprocess data in software before offloading to FPGAs for high-speed operations. For instance, in single-sideband (SSB) audio transmission, the V850E/ME2 (running at 147.456 MHz) performs initial up-sampling and filtering of audio at 24.414 kHz to 781 kHz, then transfers samples to an FPGA clocked at 100 MHz for final comb filtering and direct digital synthesis (DDS) modulation, reducing V850 execution time to approximately 11.8 µs per frame. This hybrid architecture minimizes FPGA resource usage by avoiding complex multipliers in favor of simple averaging filters post-up-sampling. Similar partitioning applies to DTMF tone generation and detection, where the V850 handles Goertzel algorithm-based decoding (processing 14,080 samples in 33 ms, or ~2% CPU utilization at 150 MHz), delegating modulation to FPGA for real-time output.[44] Custom parallel I/O interfaces further exemplify V850-FPGA synergy in multimedia systems. A reference design pairs a NEC V850 host with a Xilinx Spartan-6 FPGA via a proprietary parallel bus, enabling the FPGA to capture and stream video using IP cores like logiWIN, accelerate 2D graphics with logiBITBLT, or blend video/LCD content via logiCVC-ML. This setup supports applications requiring real-time video processing, where the V850 orchestrates data flow and the FPGA executes parallel tasks, demonstrating scalable integration for embedded video systems without dedicated ASICs.[71] Overall, these integrations support V850-based SoC prototyping by allowing FPGA emulation of peripherals or accelerators, reducing development cycles and enabling verification of complex interactions before silicon commitment. Tools like Renesas evaluation boards facilitate such setups, ensuring compatibility with V850's external bus standards, though with the legacy status of V850, similar integrations are now typically pursued with RH850.[70]

Legacy and Evolution

Obsolete Components

The V810 core, developed by NEC in the late 1980s as part of the V800 series RISC family for data processing applications, served as a predecessor to the V850 architecture but was rendered obsolete by the V850's introduction around 1994 due to the V810's reliance on off-chip memory, which limited its scalability and performance in embedded control systems.[72] Early generations of the V850, particularly non-E variants, lacked enhanced debugging capabilities and improved low-power modes, such as those introduced in the V850E series for better development efficiency and energy management in automotive and industrial applications.[73] Later generations of the V850 incorporated advanced interfaces, including FlexRay in the V850E2/Fx4 series starting around 2010, to support higher-speed deterministic networking required for modern vehicle body and chassis systems alongside continued CAN support.[5] Renesas shifted focus to successors, though limited firmware and software updates for legacy support continued until at least 2024 for repair and maintenance purposes.[74] Migration paths from obsolete V850 components involve Renesas-provided tools and guides, such as compiler migration documentation from the CA850 (V850) to CC-RH (RH850) environments, enabling code porting to the V850E2 or RH850 families while maintaining backward compatibility for interrupt handling and peripheral configurations.[50]

Transition to Successors

The RH850 microcontroller family, introduced by Renesas Electronics in 2012, serves as the direct successor to the V850 architecture, building upon its 32-bit RISC foundation while introducing enhancements for modern automotive and embedded applications.[75][76] The RH850 maintains core compatibility with select V850 variants, particularly those based on the V850E3v5 pipeline, allowing for binary upward compatibility in compatible modes where instruction sets align closely.[77] However, full binary portability is limited due to architectural refinements, necessitating source-level recompilation using updated compilers for broader migration.[50] Key drivers for the transition include the adoption of a 40 nm manufacturing process, which enables higher integration density and supports multi-core configurations for improved scalability in complex systems.[76] Additionally, the RH850 incorporates lockstep CPU cores, where a redundant core runs in parallel to the primary one for error detection, achieving ISO 26262 compliance up to ASIL-D safety integrity levels—essential for safety-critical automotive functions like chassis control and advanced driver assistance systems (ADAS).[76][75] Power efficiency is enhanced through optimized multicore designs and low-leakage transistors, resulting in approximately 20% lower consumption compared to the V850E2 in equivalent workloads, facilitating longer battery life in energy-constrained environments.[78] To ease adoption, Renesas provides dedicated migration tools, including the CC-RH compiler for source code porting from V850's CA850, which handles adjustments for intrinsics, macros, and directives.[50] Peripheral migration is supported via the CS+ integrated development environment, which generates I/O header files (e.g., iodefine.h) and interrupt vector tables, along with the RH850 Smart Configurator for automated device driver code generation.[50][79] These tools minimize manual rework for legacy peripherals, such as CAN controllers, though adaptations are required for RH850-specific features like the RS-CAN module.[80] V850 production began tapering in the mid-2010s, with many variants reaching end-of-life status between 2015 and 2020 as focus shifted to RH850; however, Renesas commits to full support, including repairs and parts availability, through its Product Longevity Program (PLP) for qualifying automotive applications, with some products supported beyond 2024 as of November 2025.[81][74][82]

Market Impact and Challenges

The V850 architecture played a pivotal role in advancing 32-bit RISC microcontrollers for automotive applications, particularly in Japan during the 2000s, where it contributed to Renesas' (formerly NEC) strong position in the embedded market. As one of the leading families alongside M16C and H8S, the V850 lineup helped Renesas capture nearly one-third of the worldwide microcontroller market at its peak, underscoring its influence on automotive electronics such as engine control units and body systems.[26] This penetration was driven by its integration into vehicles from major manufacturers, including Toyota's electronic throttle control systems, which highlighted the architecture's reliability in safety-critical environments.[83] The V850 also supported key industry standards, notably through compliance with OSEK/VDX, an open standard for real-time operating systems in automotive ECUs, facilitating scalable software development across networked vehicle systems.[41] Its adoption in high-volume production influenced the broader ecosystem by promoting standardized middleware, though the architecture's proprietary nature limited global interoperability compared to open alternatives. Despite these successes, the V850 faced challenges prior to the 2002 Renesas merger, including high licensing and development tool costs under NEC, which hindered adoption outside Japan, as evidenced by premium pricing for compilers and emulators that exceeded those of emerging competitors.[84] Intensifying competition from ARM Cortex-M series in the mid-2000s exacerbated these barriers, with ARM's low-cost ecosystem capturing significant share in cost-sensitive non-Japanese markets.[85] As of 2025, the V850 maintains longevity in legacy automotive and industrial systems, with ongoing support through Renesas tools and programmers ensuring compatibility for maintenance and retrofits. Looking ahead, the architecture occupies a niche role in industrial upgrades and older vehicle fleets, increasingly overshadowed by its successor RH850 and ARM-based solutions that offer enhanced performance and broader ecosystem integration.[76][86]

References

  1. [PDF] V850 FAMILYTM - Bitsavers.org
  2. https://www.renesas.com/en/about/newsroom/renesas-electronics-introduces-new-v850-microcontroller-mcu-series-very-low-power-consumption-and
  3. https://www.renesas.com/eu/en/document/mah/v850-familytm-architecture
  4. https://www.renesas.com/en/document/apn/v850eme2-v850e2me3-hardware
  5. https://www.renesas.com/en/about/newsroom/renesas-electronics-introduces-4th-generation-v850-microcontrollers-series-74-individual-devices
  6. [PDF] history-100.pdf - NEC Corporation
  7. https://www.renesas.com/eu/en/document/mah/v850-familytm-architecture?language=en
  8. Cadence And NEC Electronics Develop New Prototype ... - NS Energy
  9. [PDF] NEC Electronics and Renesas Reach a Definitive Agreement - Hitachi
  10. https://www.renesas.com/en/about/newsroom/renesas-electronics-corporation-commences-operations
  11. C Compiler Package for V850 Family
  12. [PDF] V850E1 32-Bit Microprocessor Core Architecture UM
  13. https://www.renesas.com/en/document/apn/32-bit-single-chip-microcontrollers-v850-clock-monitor
  14. https://www.renesas.com/en/document/apn/v850esjg3-watch-dog-timer2infinite-loop-detection-125-ms-intervals
  15. [PDF] V850 Series Product Roadmap - RS Online
  16. None
  17. Next-Generation V850E2M Dual Core Architecture For 32-Bit V850 ...
  18. [PDF] V850ES 32-Bit Microprocessor Core Architecture UM
  19. V850 - Wikiwand
  20. [PDF] V850E2S User's Manual: Architecture
  21. None
  22. [PDF] V850 Series Pamphlet - Rockby Electronics
  23. https://www.renesas.com/en/about/newsroom/renesas-electronics-announces-development-next-generation-32-bit-v850-cpu-core-simd-support-provides
  24. Toyota Case: Inside Camry's Electronic Control Module - EE Times
  25. [PDF] Renesas 32-bit Microcontrollers - Farnell
  26. Slideshow: The most-popular MCUs ever - EDN Network
  27. https://www.renesas.com/en/document/apn/v850e2ml4-ethernet-sendreceive-setup-example
  28. [PDF] Present Status of the Embedded CPU in SoC Design
  29. https://www.renesas.com/en/products/v850es-sj3
  30. Renesas Electronics Introduces V850E2M/MN4 32-Bit All Flash ...
  31. Renesas integrates resolver sensor interface to MCU ...
  32. https://www.renesas.com/en/document/pre/v850e2pj4-e-product-features
  33. Renesas Electronics Introduces 4th-Generation of its V850 ...
  34. https://www.renesas.com/en/products/v850es-fx3
  35. [PDF] Datasheet Search Engine - Octopart
  36. https://www.renesas.com/en/document/apn/v850ema1tm-hardware
  37. https://www.renesas.com/en/document/tnr/real-time-os-ri850v4-v850-mcus-published
  38. https://www.renesas.com/en/document/mat/ri850v4-v2-real-time-operating-system-users-manual-coding
  39. https://www.renesas.com/en/products/automotive-products/autosar
  40. embOS-Classic V850 IAR - SEGGER
  41. https://www.renesas.com/en/design-support/software
  42. [PDF] V850 Series Development Environment Pamphlet - rxelectronics.
  43. Industries | Automotive - IAR
  44. embOS-Classic V850 NEC - SEGGER
  45. [PDF] Digital Signal Processing with V850 and V850E Devices
  46. [PDF] IAR Embedded Workbench
  47. https://www.renesas.com/en/document/tcu/v850-series-c-compiler-package-ca850-ver-270-operating-precautions
  48. https://www.renesas.com/us/en/document/apn/v850-series-peripheral-macro-driver-application-note
  49. https://www.renesas.com/en/document/apn/v850e2ml4-application-note-dma-controller
  50. https://www.renesas.com/en/document/apn/v850-microcontrollers-v850esjx3-l-uart-communication-using-uarta-application-note
  51. None
  52. Download Toolchains | Open Source Tools for Renesas
  53. V850 - Open Source Tools for Renesas
  54. https://www.renesas.com/en/software-tool/simulator-cs-v850-family
  55. https://www.renesas.com/en/software-tool/e1-e20-software-for-other-mcu
  56. https://www.renesas.com/en/document/tnr/e1-chip-debugging-emulator-supports-v850-family-mcus
  57. None
  58. None
  59. https://www.renesas.com/en/document/mat/v850-jtag-ocd-checker-users-manual
  60. https://www.renesas.com/us/en/document/bro/renesas-mpus-mcus-v850-mcu-selection-guide
  61. [PDF] QB-V850MINI, QB-V850MINIL - RS Online
  62. QB-V850 Renesas Electronics Corporation | Evaluation Boards
  63. Renesas Electronics Authorized Distributor | Avnet Americas
  64. IECUBE
  65. IE850
  66. https://www.renesas.com/en/document/mat/product-lineup-ie850-v850e2m-and-option-products
  67. MINICUBE (Discontinued product)
  68. https://www.renesas.com/en/software-tool/e1-e20-programming-function-for-other-mcu
  69. https://www.renesas.com/en/document/mat/pg-fp5-v217-flash-memory-programmer-users-manual-rl78-78k-v850-rx100-rx200-rx61x-rx62x-rx63x-r8c
  70. https://www.renesas.com/en/software-tool/cs
  71. None
  72. Companion Chip Reference FPGA Designs - logicBRICKS
  73. [PDF] NEC Launches Second V-Series Core - CECS
  74. https://www.renesas.com/en/document/mat/ie-v850e1-cd-nw-users-manual
  75. https://www.renesas.com/en/document/gde/list-eol-products-supported-repair-june-2024
  76. Body Bias Optimization for Real-Time Systems - MDPI
  77. https://www.renesas.com/en/about/newsroom/renesas-electronics-unveils-new-generation-rh850-microcontroller-automotive-applications
  78. RH850 Automotive MCU – High Performance Automotive MCUs Microcontrollers
  79. Could anyone please tells me the major differences between the ...
  80. [PDF] Renesas presentation_EV_Seminar
  81. https://www.renesas.com/en/software-tool/rh850-smart-configurator
  82. V850 to RH850 CAN - CAN/LIN - Forum - Renesas Community
  83. https://www.renesas.com/en/support/end-of-life-eol-products
  84. https://www.renesas.com/en/support/product-longevity-program-plp
  85. RH850 - Green Hills Software
  86. Toyota's killer firmware: Bad design and its consequences - EDN
  87. CPU of the Day: NEC 78C11 Sample and the 78K family
  88. https://www.renesas.com/en/software-tool/compiler-licenses
  89. Automotive Microcontroller Market Size ($41.8 Billion) 2030
  90. GreenFlasher V850 and RH850 - The Automotive Expert
  91. https://www.llvm-gcc-renesas.com/en/question/tells-major-differences-rh850-v850-families/
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