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Intel 8089
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The Intel 8089 input/output coprocessor was available for use with the 8086/8088 central processor. It was announced in May 1979, but the price was not available at that time.[1] It used the same programming technique as 8087 for input/output operations, such as transfer of data from memory to a peripheral device, and so reducing the load on the CPU. This I/O processor was available in July 1979 for US$194.20 in quantities of 100 or more.[2] Intel second sourced this coprocessor to Fujitsu Limited.[3]
Because IBM didn't use it in the IBM PC design, it did not become well known; later Intel I/O coprocessors did not keep the x89 designation the way math coprocessors kept the x87 designation. It was used in the Apricot PC and the Intel Multibus iSBC-215 Hard disk drive controller.[4] It was also used in the Altos 586 multi-user computer.[5] Intel themselves used the 8089 in their reference designs (which they also commercialized) as System 86.[6]
Peripherals
[edit]- Intel 8282/8283: 8-bit latch
- Intel 8284: clock generator
- Intel 8286 / 8287 were 8-bit data bus transceivers. Both Intel I8286 and I8287(inverting version) were available for US$16.25 in quantities of 100.[7]
- Intel 8288: bus controller
- Intel 8289: bus arbiter
Literature and datasheets
[edit]
- 8089 Assembler Users Guide; Intel 1979
- 8089 8 & 16-Bit HMOS I/O Processor; Intel 1980
- John Atwood, Dave Ferguson: Debugging Strategies And Considerations For 8089 Systems Archived 2021-08-29 at the Wayback Machine, Application Note (AP-50), September 1979, Intel Corporation.
- Jim Nadir: Designing 8086, 8088, 8089 Multiprocessing System With The 8289 Bus Arbiter Archived 2021-08-29 at the Wayback Machine, Application Note (AP-51), März 1979, Intel Corporation.
- Robin Jigour: Prototyping with the 8089 I/O Processor, Application Note (AP-89), Mai 1980, Order number AFN 01153A, Intel Corporation.
- Hard Disk Controller Design Using the 8089, Application Note (AP-122), Order number 210202-001, Intel Corporation.
- Graphic CRT Design Using the Intel 8089, Application Note (AP-123), Intel Corporation.
References
[edit]- ^ Intel Corporation, "Microcomputer Components: Intel Introduces the 8089 IOP, an I/O processor for the advanced 8088/8086 CPU family, the first of a series of new subsystem components", Intel Preview, May/June 1979, p. 7.
- ^ Intel Corporation, "8089 Price Announcement", Intel Preview, July/August 1979, p. 25.
- ^ Intel Corporation, "NewsBits: Second Source News", Solutions, January/February 1985, P. 1
- ^ "Hardware manual" (PDF). Intel. Retrieved 30 April 2023.
- ^ Review: Altos 586. InfoWorld. 7 November 1983. pp. 89–90. ISSN 0199-6649.
- ^ "Introduction to the System 86/360 and System 86/330A Microcomputer Systems" (PDF). bitsavers. Intel. 1983. Retrieved November 30, 2022.
- ^ "8086 Available for industrial environment". Intel Preview Special Issue: 16-Bit Solutions. Intel Corporation. May–June 1980. p. 29.
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Intel 8089
View on Grokipediafrom Grokipedia
The Intel 8089 is a 5 MHz input/output processor (IOP) announced in March 1979 and developed by Intel as a coprocessor for the 8086 and 8088 microprocessors in the MCS-86 family, designed to handle complex I/O operations independently and offload them from the central processing unit to enhance overall system efficiency in multiprocessing environments.[1][2] Fabricated using HMOS technology in a 40-pin dual in-line package (DIP), it operates on a single +5 V power supply and supports a 20-bit address space, addressing up to 1 MB of system memory and a separate 64 KB I/O address space.[1] The device combines the functionality of a microprocessor with a direct memory access (DMA) controller, enabling high-speed data transfers at rates up to 1.25 MB/s while interfacing with systems via the Multibus architecture in maximum mode.[1]
Architecturally, the 8089 features a common control unit, an arithmetic/logic unit, an execution unit, and a bus interface unit, with two independent I/O channels capable of concurrent operations through time-multiplexing and sharing resources like the channel program register under a priority scheme (levels 1 to 4, with 1 being highest).[1] Each channel includes dedicated registers such as general-purpose registers (GA, GB, GC), a task pointer (TP) for program counter functionality, a parameter pointer (PP), an index register (IX), a byte count register (BC), and a mask/compare register (MC), supporting a programming model compatible with 8086/8088 tools like the ASM-89 assembler.[1] It employs approximately 50 specialized I/O instructions, including MOV for data movement, XFER for transfers, and TSL for table search and load, alongside addressing modes like based, offset, indexed, and auto-increment.[1]
Key features include versatile DMA modes—unsynchronized, source-synchronized, and destination-synchronized—for memory-to-memory, memory-to-port, port-to-port, and I/O-to-I/O transfers, with termination options via byte count, masked compare, or external signals.[1] The 8089 supports programmed I/O, real-time data manipulation (e.g., translation, search, word assembly/disassembly), and interrupt handling compatible with system interrupt controllers.[1] Bus compatibility extends to 8-bit and 16-bit widths with automatic detection, and it incorporates bus arbitration via request/grant lines (RQ/GT) and lock signals for multi-master systems, often paired with components like the 8288 bus controller and 8289 bus arbiter.[1] Operating temperatures range from 0°C to 70°C, with bus cycles requiring a minimum of four T-states and support for wait states via the READY signal.[1]
In practice, the 8089 was targeted at I/O-intensive applications such as real-time control systems and multiprocessing setups, for example in Intel's iSBC disk controllers, where it facilitated dual-channel processing and enhanced separation of CPU and I/O tasks akin to mainframe channel processors.[1]
High-speed DMA capabilities in the channels achieve transfer rates up to 1.25 MB/s at 5 MHz, incorporating programmable intelligence for arithmetic, logic operations, branching, searching, and data translation to minimize CPU involvement in complex I/O tasks.[1] Initialization for systems with multiple 8089 units occurs via linked lists in the System Configuration Pointer Block (SCPB) and System Control Block (SCB), with the host issuing Channel Attention (CA) pulses to start operations.[1]
History and Development
Announcement and Release
The Intel 8089 input/output coprocessor was announced in May 1979 through Intel's Preview magazine, marking it as the first in a series of new subsystem components designed to enhance the 8086/8088 CPU family.[3] This announcement highlighted the 8089's role within the emerging 8086 ecosystem by providing dedicated I/O processing to complement the main processor's computational focus.[4] The device became available for purchase starting in July 1979, with pricing set at US$194.20 for orders of 100 units or more.[3] Intel positioned the 8089 initially as an intelligent direct memory access (DMA) controller, aimed at offloading I/O operations from the host CPU to improve overall system efficiency in microcomputer applications.[4] To support broader production and market reach, Intel established a second-sourcing agreement with Fujitsu Limited, enabling the Japanese firm to manufacture compatible versions of the 8089.[5]Design Context
The Intel 8089 was developed as a key component of Intel's iAPX 86/10 family in the late 1970s, specifically to mitigate I/O bottlenecks that hindered performance in multitasking and real-time microcomputer systems. At the time, the transition from mainframes to more distributed computing architectures demanded efficient peripheral management without compromising the host CPU's execution flow, prompting Intel to create a dedicated I/O processor capable of independent operation alongside the 8086 or 8088 central processors.[6] The core motivation for the 8089 stemmed from the need to offload high-speed DMA transfers, peripheral synchronization, and device interactions from the main CPU, thereby reducing overhead in applications requiring concurrent processing. In 1970s computing environments, where block data transfers and real-time responses were critical for emerging minicomputer and embedded systems, a general-purpose CPU like the 8086 often stalled during I/O operations, leading to inefficiencies; the 8089 addressed this by enabling autonomous I/O channel management, allowing the system to sustain higher throughput without CPU intervention.[7][8] Influenced by Intel's prior coprocessor innovations, such as the 8087 numeric data processor introduced in 1979, the 8089 adapted similar concepts of modular task offloading and bus-sharing protocols to the I/O domain. While the 8087 accelerated arithmetic operations through dedicated hardware, the 8089 repurposed these architectural principles for I/O-specific challenges, integrating seamlessly into the iAPX ecosystem to support distributed processing and reduce overall system design complexity.[6]Architecture
Processor Core and Addressing
The Intel 8089 is a 16-bit input/output processor (IOP) featuring an execution unit and bus interface unit that enable independent instruction fetching, decoding, and execution optimized for I/O tasks such as DMA transfers and device control.[1] Its core supports arithmetic, logical operations, branching, and data manipulation within a dual-channel architecture supporting independent and concurrent channel operations with resource sharing and priority-based interleaving to manage I/O efficiently.[1] The processor operates at a clock speed of 5 MHz, corresponding to a 200 ns cycle time, allowing for internal operations spanning 2 to 8 clock cycles and bus cycles requiring a minimum of 4 clock cycles.[1] The 8089 employs a 20-bit extended addressing scheme for accessing up to 1 MB of system memory space, while utilizing 16-bit addressing to reach 64 KB in the local or I/O space.[1] Addresses incorporate tag bits within pointer registers (such as GA, GB, GC, TP, and PP), where a tag bit value of 0 denotes a 20-bit system address and 1 indicates a 16-bit local/I/O address, enabling seamless distinction between memory and peripheral spaces during operations.[9] This scheme supports addressing modes including based, offset, indexed, and indexed auto-increment, with effective addresses formed by combining segment bases (shifted left by 4 bits) and offsets.[10] The processor supports two operational modes: LOCAL mode, in which it shares the Multibus interface with the host CPU via request/grant lines for coordinated access, and REMOTE mode, which employs a dedicated local bus for I/O operations to enhance parallelism and independence from the system bus.[1] In both modes, the 8089 accommodates 8-bit or 16-bit bus widths, with execution timing influenced by the configuration; for instance, 16-bit buses enable single-cycle aligned word transfers, whereas 8-bit buses or odd-address accesses require additional cycles (up to three for unaligned words), potentially inserting wait states for peripheral compatibility.[1] Memory organization relies on paragraph-aligned segments limited to 64 KB each, where alignment to 16-byte boundaries optimizes access efficiency.[9] Even addresses facilitate faster 16-bit data fetches on compatible buses, completing in one cycle, while odd addresses trigger byte-by-byte mode, doubling the bus cycles needed and impacting overall I/O throughput.[1] This alignment ensures compatibility with the broader 8086 family architecture while prioritizing performance in segmented data handling.[9]Registers and Programming Model
The Intel 8089 Input/Output Processor (IOP) features a dedicated register set optimized for managing I/O tasks through a task-based programming model, with separate registers for each of its two independent channels. This model allows the 8089 to execute user-programmed task blocks concurrently with direct memory access (DMA) operations, offloading I/O processing from the host CPU such as the 8086 or 8088. The registers include 20-bit pointers for addressing in the 1 MB system space or 64 KB local I/O space, and 16-bit control and auxiliary registers for transfer management, enabling flexible data movement and conditional operations.[9][11] The 20-bit pointer registers—GA (source pointer), GB (destination pointer), GC (translation table base), TP (task pointer), and PP (read-only parameter pointer)—support addressing modes with a tag bit to distinguish between 20-bit system addresses (tag=0) and 16-bit local I/O addresses (tag=1, sign-extended). The GA, GB, and GC registers serve as general-purpose pointers for DMA source/destination and data translation via a 256-byte table at GC, while the TP register holds the address of the next task block instruction along with its tag bit, facilitating sequential or branched execution. The PP register points to the Command Parameter Block and remains read-only during task execution to preserve initialization data. After most operations, the upper 4 bits (bits 16-19) of these 20-bit registers are undefined, except during additions where carry propagation may affect them. Indirect addressing is supported through base-plus-offset or base-plus-index modes, such as [GA] or [GB + IX], enhancing flexibility in task block programs.[9][11] The 16-bit registers include IX (index register) for offset calculations with post-auto-increment, BC (byte counter) for tracking byte counts in DMA transfers (decremented by 1 for byte or 2 for word operations), MC (comparison/mask) for pattern matching in conditional jumps and DMA termination, and CC (channel control) for configuring transfer parameters. The CC register's bits define key behaviors: bits 15-14 select the transfer function (e.g., memory-to-memory, port-to-port); bit 13 enables translation mode using the GC table; bits 12-11 control synchronization (none, source, or destination); bit 9 sets lock mode for bus arbitration; bit 8 enables chaining for concurrent task and DMA execution; bit 7 activates single-transfer mode; and bits 6-0 handle termination conditions, including byte count zero, masked compare matches, and external signals. These registers enable the 8089 to interleave task execution with DMA while maintaining channel independence.[9][11] In the programming model, task blocks form the core units of execution, loaded via the TP register from the Command Parameter Block to handle I/O sequences autonomously. Each task block contains 8089 instructions that manipulate registers and perform data transfers, with the TP updated automatically for sequential flow or via CALL/LCALL for subroutine-like chaining (storing return addresses) and MOVP for returns. Chained execution, controlled by the CC chaining bit, allows DMA to proceed in parallel with task instructions, prioritizing based on CC settings to optimize bus usage. Indirect addressing modes using the pointers and IX support complex data structures without explicit loads. The addressing tag bit in TP and other pointers briefly references the underlying mode selection between system and local spaces.[9] Control blocks in system memory orchestrate initialization and channel operations: the System Control Program Block (SCPB) at address 0FFFF6H contains bus width and SCB (subchannel block) pointers; the SCB specifies system options and links to Channel Blocks (CBs); each CB includes a Channel Control Word (CCW) for commands, interrupt control, bus load limits, and priority (P bit), plus a pointer to the Command Parameter Block; and CBs (one per channel, e.g., CB and CB+8) manage subchannel tasks. This hierarchical structure enables the host CPU to configure the 8089 without direct intervention in task execution.[9][11]| Register | Size | Primary Function |
|---|---|---|
| GA | 20-bit | Source pointer for DMA and data addressing |
| GB | 20-bit | Destination pointer for DMA and data addressing |
| GC | 20-bit | Translation table base or general pointer |
| TP | 20-bit | Task pointer for instruction sequencing (with tag bit) |
| PP | 20-bit | Read-only pointer to Command Parameter Block |
| IX | 16-bit | Index for offset-based addressing |
| BC | 16-bit | Byte counter for transfer tracking |
| CC | 16-bit | Channel control for DMA parameters and modes |
| MC | 16-bit | Mask/compare for conditional operations |
Features and Capabilities
I/O Channels
The Intel 8089 I/O Processor features two independent channels, designated A and B, that enable concurrent I/O processing and direct memory access (DMA) transfers, allowing the host CPU to offload I/O overhead while maintaining system efficiency.[1] Each channel operates autonomously, managing interactions with peripherals through memory-based control blocks such as Channel Control Blocks (CBs), Parameter Blocks (PBs), and Task Blocks (TBs), which the host CPU configures to define I/O tasks.[1] This dual-channel architecture supports programmed I/O for direct device communication, as well as DMA transfers between 8-bit and 16-bit data widths in various configurations, including I/O-to-memory, memory-to-memory, and I/O-to-I/O operations.[1] The channels facilitate peripheral synchronization using DMA request signals (DRQ1 and DRQ2) and external (EXT) signals, ensuring coordinated data movement without host intervention.[1] Block transfers, such as page swaps or program loads from disk, are handled efficiently across the 8089's access to up to 64 KB of I/O space, compatible with the 8086 family addressing.[1] Operations are governed by the Channel Control Register (CC), a key component of each channel's register set (as detailed in the processor's programming model), which specifies transfer parameters and modes.[1] The CC register's bits provide precise control over channel behavior, as outlined below:| Bit(s) | Function | Description |
|---|---|---|
| 15-14 | Function Control | Selects transfer type (e.g., port-to-port, memory-to-port).[1] |
| 13 | Translation Mode | Enables data translation using the GC register table during transfers.[1] |
| 12-11 | Synchronization | Configures mode: none, source, or destination synchronization.[1] |
| 10 | Source/Destination Indicator | Specifies transfer direction or source/destination.[1] |
| 9 | Lock | Locks the bus for atomic operations during transfer.[1] |
| 8 | Chaining | Allows task chaining for sequential or priority execution.[1] |
| 7 | Single Transfer | Terminates after one operation.[1] |
| 0-6 | Termination | Sets criteria like byte count expiration or external signals.[1] |