The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips–a northbridge and southbridge, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I⁠/⁠O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset since the release of the Zen architecture in 2017. AMD no longer uses its equivalent for the PCH, the Fusion controller hub (FCH).

The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Under the Hub Architecture, a motherboard would have a two-piece chipset consisting of a northbridge chip and a southbridge chip. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.

As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge and its functions are now eliminated completely: The memory controller, PCI Express lanes for expansion cards and other northbridge functions are now incorporated into the CPU die as a system agent (Intel) or packaged in the processor on an I⁠/⁠O die (AMD Zen 2).

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions, replacing it. The system clock was previously a connection to a dedicated chip but is now incorporated into the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is used only when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets. AMD's chipsets instead use several PCIe lanes to connect with the CPU while also providing their own PCIe lanes, which are also provided by the processor itself. The chipset also contains the Nonvolatile BIOS memory.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

This style began in Nehalem and will remain for the foreseeable future, through Cannon Lake.

Beginning with ultra-low-power Haswells and continuing with mobile Skylake processors, Intel incorporated the southbridge IO controllers into the CPU package, eliminating the PCH for a system in package (SOP) design with two dies; the larger die being the CPU die, the smaller die being the PCH die. Rather than DMI, these SOPs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.^{[needs update]}