The R10000, code named T5, is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.

Described in press reports during 1992 as MIPS Computer Systems' "next generation RISC part", the R10000 was originally scheduled for delivery in 1994 and intended to form the basis of a family of products, each of which requiring substantially less development effort to bring to market than the core technology itself while incrementally improving performance. During 1993, MIPS Technologies sought to bring its licencees' resources to bear on the design of the R10000 and related products, with MIPS, Integrated Device Technology, LSI Logic, NEC, Performance Semiconductor, Siemens and Toshiba collectively planning to invest a reported $150 million in this next generation. The R10000 was eventually unveiled in October 1994 by MIPS and its silicon partners NEC and Toshiba, emphasising the product's potential applications in multiprocessing and massively parallel configurations, and claiming a projected performance of 300 SPECint92, 600 SPECfp92 at 200 MHz.

The R10000 was introduced in July 1995 at clock frequencies of 175 MHz and 195 MHz. A 150 MHz version was introduced in the O2 product line in 1997, but discontinued shortly after due to customer preference for the 175 MHz version. The R10000 was not available in large volumes until later in the year due to fabrication problems at MIPS's foundries. The 195 MHz version was in short supply throughout 1996, and was priced at US$3,000 as a result.

On 25 September 1996, SGI announced that R10000s fabricated by NEC between March and the end of July that year were faulty, drawing too much current and causing systems to shut down during operation. SGI recalled 10,000 R10000s that had shipped in systems as a result, which impacted the company's earnings.

In 1997, a version of R10000 fabricated in a 0.25 μm process enabled the microprocessor to reach 250 MHz.

Users of the R10000 include:

The R10000 is a four-way superscalar design that implements register renaming and executes instructions out-of-order. Its design is a departure from previous MTI microprocessors such as the R4000, which is a much simpler scalar in-order design that relies largely on high clock rates for performance.

The R10000 fetches four instructions every cycle from its instruction cache. These instructions are decoded and then placed into the integer, floating-point or load/store instruction queues depending on the type of the instruction. The decode unit is assisted by the pre-decoded instructions from the instruction cache, which append five bits to every instruction to enable the unit to quickly identify which execution unit the instruction is executed in, and rearrange the format of the instruction to optimize the decode process.