2.5D integrated circuit

A 2.5D integrated circuit (2.5D IC) is an advanced packaging technique that combines multiple integrated circuit dies in a single package without stacking them into a three-dimensional integrated circuit (3D-IC) with through-silicon vias (TSVs). The term "2.5D" originated when 3D-ICs with TSVs were quite new and still very difficult. Chip designers realized that many of the advantages of 3D integration could be approximated by placing bare dies side by side on an interposer instead of stacking them vertically. If the pitch is very fine and the interconnect very short, the assembly can be packaged as a single component with better size, weight, and power characteristics than a comparable 2D circuit board assembly. This half-way 3D integration was facetiously named "2.5D" and the name stuck.

Since then, 2.5D has proven to be far more than just "half-way to 3D."

An interposer can support heterogeneous integration – that is, dies of different pitch, size, material, and process node. Placing dies side by side instead of stacking them reduces heat buildup. Upgrading or modifying a 2.5D assembly is as easy as swapping in a new component and revamping the interposer to suit; much faster and simpler than reworking an entire 3D-IC or System-on-Chip (SoC). Some sophisticated 2.5D assemblies even incorporate TSVs and 3D components. Several foundries now support 2.5D packaging.

The success of 2.5D assembly has given rise to "chiplets" – small, functional circuit blocks designed to be combined in mix-and-match fashion on interposers. Several high-end products already take advantage of these LEGO-style chiplets; some experts predict the emergence of an industry-wide chiplet ecosystem. Interposers can be larger than the reticle size which is the maximum area that can be projected by a photolithography scanner or stepper.

A 2.5D IC architecture is an intermediate solution between traditional 2D and advanced 3D architectures. While a 2D architecture integrates all components on a single silicon die (SoC) and a 3D architecture stacks multiple dies vertically, the 2.5D approach involves placing multiple chiplets side-by-side on a silicon interposer within a single package. The chiplets, which perform various functions, are bonded to the interposer, and the interconnection between them are routed on this interposer. The interposer is then connected to the package substrate using silicon vias, which provide connections to peripheral hardware such as SRAM or DRAM.

The interposer, also known as a redistributed layer (RDL), is a key component in the physical design of chiplets. It acts as an intermediate layer that facilitates communication between chiplets and provides interfaces for peripheral devices. The design of the interposer and its wiring is crucial, as the routing of these wires can introduce additional latency and parasitic parameters that can affect overall performance and reliability. In advanced packaging technologies like CoWoS, the interposer design method uses wiring within the interposer and through-silicon-via (TSV) technology to connect chiplets and establish connections to the packaging substrate.

Interposers can be made from different materials, including silicon, glass, and organics. Silicon interposers are widely used due to their ability to achieve fine feature sizes with existing process technology, making them a cost-effective option. Interposers use TSVs for communication between the chip and for connecting to the substrate. A 10x100um TSV is sometimes used in an interposer with three or four metal layers on the probe side and a single copper RDL on the grind side.

There are several interposer technologies used in 2.5D ICs, each with its own set of trade-offs in terms of cost, performance, and complexity.