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Bull Gamma 60
The Bull Gamma 60 was a large transistorized mainframe computer designed by Compagnie des Machines Bull. Initially announced in 1957, the first unit shipped in 1960. It was the world's first multi-threaded computer, and the first to feature an architecture specially designed for parallelism.
The Gamma 60 spearheaded numerous groundbreaking technologies during the early 1960s, notably in multi-programming, utilizing tools that were still in their nascent stages. Upon its release, its architecture garnered significant attention among machine designers, becoming a subject of study alongside contemporary supercomputers and being cited as an example for progress in computer design.
Despite its innovations, the Gamma 60's large footprint (close to 4,000 square feet (370 m2)), high cost, energy consumption, and complexity ultimately resulted in limited commercial success, with only about twenty units sold worldwide. Its main competitors included the IBM 7070, 7090, and 7030 "Stretch". The last Gamma 60 remained in service until 1974.
The Gamma 60 marked Bull's entry into core memory, solid-state logic and magnetic tape capabilities. Its architectural core was based on a large, high-speed central memory, with an arbitrator (known as the Program Distributor) responsible for distributing data and instructions to the various units within the computer. The processor was segmented into a central unit and a series of discrete, specialized processing units. This design allowed for the concurrent operation of up to five clusters, each containing five processing units.
Each unit in the computer, whether a processing unit or a peripheral device, operated autonomously and would request data and instructions from the central unit when they became available. Data was transmitted to and from the processing units over two independent buses, one for transmission and another for retrieval.
The processor operated in a 24-bit parallel configuration, with its primary data types employing one, two, or four words, also referred to as 'catenae', ranging from 24 to 96 bits in width. Simpler and slower external devices often employed an 8-bit parallel logic internally. These devices communicated with the central unit via bit-serial messages for instruction and data transfer requests. All messages were asynchronous, and the machine, through priority classes, was designed to accommodate very high device latencies if necessary, even from an ALU (Arithmetic Logic Unit).
The processor was divided into four kinds of processing elements:
Even though up to twenty-five of those specialized processing units could run simultaneously, the machine had only one central unit (functioning as a dispatcher), which does not classify the architecture as an SMP (Symmetric Multiprocessing).
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Bull Gamma 60 AI simulator
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Bull Gamma 60
The Bull Gamma 60 was a large transistorized mainframe computer designed by Compagnie des Machines Bull. Initially announced in 1957, the first unit shipped in 1960. It was the world's first multi-threaded computer, and the first to feature an architecture specially designed for parallelism.
The Gamma 60 spearheaded numerous groundbreaking technologies during the early 1960s, notably in multi-programming, utilizing tools that were still in their nascent stages. Upon its release, its architecture garnered significant attention among machine designers, becoming a subject of study alongside contemporary supercomputers and being cited as an example for progress in computer design.
Despite its innovations, the Gamma 60's large footprint (close to 4,000 square feet (370 m2)), high cost, energy consumption, and complexity ultimately resulted in limited commercial success, with only about twenty units sold worldwide. Its main competitors included the IBM 7070, 7090, and 7030 "Stretch". The last Gamma 60 remained in service until 1974.
The Gamma 60 marked Bull's entry into core memory, solid-state logic and magnetic tape capabilities. Its architectural core was based on a large, high-speed central memory, with an arbitrator (known as the Program Distributor) responsible for distributing data and instructions to the various units within the computer. The processor was segmented into a central unit and a series of discrete, specialized processing units. This design allowed for the concurrent operation of up to five clusters, each containing five processing units.
Each unit in the computer, whether a processing unit or a peripheral device, operated autonomously and would request data and instructions from the central unit when they became available. Data was transmitted to and from the processing units over two independent buses, one for transmission and another for retrieval.
The processor operated in a 24-bit parallel configuration, with its primary data types employing one, two, or four words, also referred to as 'catenae', ranging from 24 to 96 bits in width. Simpler and slower external devices often employed an 8-bit parallel logic internally. These devices communicated with the central unit via bit-serial messages for instruction and data transfer requests. All messages were asynchronous, and the machine, through priority classes, was designed to accommodate very high device latencies if necessary, even from an ALU (Arithmetic Logic Unit).
The processor was divided into four kinds of processing elements:
Even though up to twenty-five of those specialized processing units could run simultaneously, the machine had only one central unit (functioning as a dispatcher), which does not classify the architecture as an SMP (Symmetric Multiprocessing).