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Multiple patterning
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node or TSMC at its 28nm node. Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.
Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow. Since then several double patterning techniques have been developed such as self alignment double patterning (SADP) and a litho-only approach to double patterning.
Pitch double-patterning was pioneered by Gurtej Singh Sandhu of Micron Technology during the 2000s, leading to the development of 30-nm class NAND flash memory. Multi-patterning has since been widely adopted by NAND flash and random-access memory manufacturers worldwide.
There are a number of situations which lead to multiple patterning being required.
The most obvious case requiring multiple patterning is when the feature pitch is below the resolution limit of the optical projection system. For a system with numerical aperture NA and wavelength λ, any pitch below 0.5 λ/NA would not be resolvable in a single wafer exposure. The resolution limit may also originate from stochastic effects, as in the case of EUV. Consequently, 20 nm linewidth still requires EUV double patterning, due to larger defectivity at larger pitches.
It is well-established that dense two-dimensional patterns, which are formed from the interference of two or three beams along one direction, as in quadrupole or QUASAR illumination, are subject to significant rounding, particularly at bends and corners. The corner rounding radius is larger than the minimum pitch (~0.7 λ/NA). This also contributes to hot spots for feature sizes of ~0.4 λ/NA or smaller. For this reason, it is advantageous to first define line patterns, then cut segments from such lines accordingly. This requires additional exposures. The cut shapes themselves may also be round, which requires tight placement accuracy.
The rounding of line tips naturally leads to a tradeoff between shrinking the line width (i.e., the width of the line tip) and shrinking the gap between opposite facing tips. As the line width shrinks, the tip radius shrinks. When the line tip is already less than the point spread function (k1~0.6–0.7), the line tip naturally pulls back, increasing the gap between opposite facing tips. The point spread function likewise limits the resolvable distance between the centers of the line tips (modeled as circles). This leads in turn to a tradeoff between reducing cell width and reducing cell height. The tradeoff is avoided by adding a cut/trim mask (see discussion below). Hence, for the EUV-targeted 7nm node, with an 18 nm metal linewidth (k1=0.44 for λ=13.5 nm, NA=0.33), the line tip gap of less than 25 nm (k1=0.61) entails EUV single patterning is not sufficient; a second cut exposure is necessary.
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Multiple patterning AI simulator
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Multiple patterning
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.
Even with single exposure having sufficient resolution, extra masks have been implemented for better patterning quality such as by Intel for line-cutting at its 45nm node or TSMC at its 28nm node. Even for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.
Double patterning lithography was first demonstrated in 1983 by D. C. Flanders and N. N. Efremow. Since then several double patterning techniques have been developed such as self alignment double patterning (SADP) and a litho-only approach to double patterning.
Pitch double-patterning was pioneered by Gurtej Singh Sandhu of Micron Technology during the 2000s, leading to the development of 30-nm class NAND flash memory. Multi-patterning has since been widely adopted by NAND flash and random-access memory manufacturers worldwide.
There are a number of situations which lead to multiple patterning being required.
The most obvious case requiring multiple patterning is when the feature pitch is below the resolution limit of the optical projection system. For a system with numerical aperture NA and wavelength λ, any pitch below 0.5 λ/NA would not be resolvable in a single wafer exposure. The resolution limit may also originate from stochastic effects, as in the case of EUV. Consequently, 20 nm linewidth still requires EUV double patterning, due to larger defectivity at larger pitches.
It is well-established that dense two-dimensional patterns, which are formed from the interference of two or three beams along one direction, as in quadrupole or QUASAR illumination, are subject to significant rounding, particularly at bends and corners. The corner rounding radius is larger than the minimum pitch (~0.7 λ/NA). This also contributes to hot spots for feature sizes of ~0.4 λ/NA or smaller. For this reason, it is advantageous to first define line patterns, then cut segments from such lines accordingly. This requires additional exposures. The cut shapes themselves may also be round, which requires tight placement accuracy.
The rounding of line tips naturally leads to a tradeoff between shrinking the line width (i.e., the width of the line tip) and shrinking the gap between opposite facing tips. As the line width shrinks, the tip radius shrinks. When the line tip is already less than the point spread function (k1~0.6–0.7), the line tip naturally pulls back, increasing the gap between opposite facing tips. The point spread function likewise limits the resolvable distance between the centers of the line tips (modeled as circles). This leads in turn to a tradeoff between reducing cell width and reducing cell height. The tradeoff is avoided by adding a cut/trim mask (see discussion below). Hence, for the EUV-targeted 7nm node, with an 18 nm metal linewidth (k1=0.44 for λ=13.5 nm, NA=0.33), the line tip gap of less than 25 nm (k1=0.61) entails EUV single patterning is not sufficient; a second cut exposure is necessary.