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IBM A2
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IBM A2
The IBM A2 is an open source massively multicore capable and multithreaded 64-bit Power ISA processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz.
The A2 core is a processor core designed for customization and embedded use in system on chip-devices, and was developed following IBM's game console processor designs, the Xbox 360-processor and Cell processor for the PlayStation 3.
A2I is a 4-way simultaneous multithreaded core which implements the 64-bit Power ISA v.2.06 Book III-E embedded platform specification with support for the embedded hypervisor features. It was designed for implementations with many cores and focusing on high throughput and many simultaneous threads. A2I was written in VHDL.
The core has 4×32 64-bit general purpose registers (GPR) with full support for both little and big endian byte ordering, 16 KB+16 KB instruction and data cache and is capable of four-way multithreading.
It has a fine grain branch prediction unit (BPU) with eight 1024-entry branch history tables. The L1 caches is a 16 KB 8-way set-associative data cache and a 4-way set-associative 16 KB instruction cache. It executes a simple in-order pipeline capable of issuing two instructions per cycle; one to the 6-stage arithmetic logic unit (ALU) and one to the optional auxiliary execution unit (AXU).
It includes a memory management unit but no floating point unit (FPU). Such facilities are handled by the AXU, which has support for any number of standardized or customized macros, such as floating point units, vector units, DSPs, media accelerators and other units with instruction sets and registers not part of the Power ISA. The core has a system interface unit used to connect to other on die cores, with a 256-bit interface for data writes and a 128-bit interface for instruction and data reads at full core speed.
The A2O is a slightly more modern version, written in Verilog, using the Power ISA v.2.07 Book III-E. It is optimized for single core performance and designed to reach 3 GHz at 45 nm process technology. The A2O differs from its sibling in that it is only two-way multithreaded, 32+32 kB data and instruction L1 caches, and is capable of out-of-order execution.
When A2O was released, no actual products have used it.
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IBM A2 AI simulator
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IBM A2
The IBM A2 is an open source massively multicore capable and multithreaded 64-bit Power ISA processor core designed by IBM using the Power ISA v.2.06 specification. Versions of processors based on the A2 core range from a 2.3 GHz version with 16 cores consuming 65 W to a less powerful, four core version, consuming 20 W at 1.4 GHz.
The A2 core is a processor core designed for customization and embedded use in system on chip-devices, and was developed following IBM's game console processor designs, the Xbox 360-processor and Cell processor for the PlayStation 3.
A2I is a 4-way simultaneous multithreaded core which implements the 64-bit Power ISA v.2.06 Book III-E embedded platform specification with support for the embedded hypervisor features. It was designed for implementations with many cores and focusing on high throughput and many simultaneous threads. A2I was written in VHDL.
The core has 4×32 64-bit general purpose registers (GPR) with full support for both little and big endian byte ordering, 16 KB+16 KB instruction and data cache and is capable of four-way multithreading.
It has a fine grain branch prediction unit (BPU) with eight 1024-entry branch history tables. The L1 caches is a 16 KB 8-way set-associative data cache and a 4-way set-associative 16 KB instruction cache. It executes a simple in-order pipeline capable of issuing two instructions per cycle; one to the 6-stage arithmetic logic unit (ALU) and one to the optional auxiliary execution unit (AXU).
It includes a memory management unit but no floating point unit (FPU). Such facilities are handled by the AXU, which has support for any number of standardized or customized macros, such as floating point units, vector units, DSPs, media accelerators and other units with instruction sets and registers not part of the Power ISA. The core has a system interface unit used to connect to other on die cores, with a 256-bit interface for data writes and a 128-bit interface for instruction and data reads at full core speed.
The A2O is a slightly more modern version, written in Verilog, using the Power ISA v.2.07 Book III-E. It is optimized for single core performance and designed to reach 3 GHz at 45 nm process technology. The A2O differs from its sibling in that it is only two-way multithreaded, 32+32 kB data and instruction L1 caches, and is capable of out-of-order execution.
When A2O was released, no actual products have used it.