MyHDL is a Python-based hardware description language (HDL).

Features of MyHDL include:

MyHDL is developed by Jan Decaluwe.

Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.

A small combinatorial design

The example is a small combinatorial design, more specifically the binary to Gray code converter:

You can create an instance and convert to Verilog and VHDL as follows:

The generated Verilog code looks as follows: