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National Semiconductor PACE
National Semiconductor's IPC-16A PACE, short for "Processing and Control Element", was the first commercial single-chip 16-bit microprocessor, announced in late 1974. It was a single-chip implementation of their early 1973 five-chip IMP-16 architecture, which in turn had been inspired by the Data General Nova minicomputer. To the basic IMP-16, PACE added a new operational mode, "byte mode", which was useful for working with 8-bit data like ASCII text.
Implemented in pMOS, as was common for the era, PACE required three supply voltages and an external clock with enough signal to drive the internal logic. This was normally supplied by the STE chip. Most PACE systems also required the BTE chip to convert the higher internal voltage signals to TTL levels used by the rest of the system. Its multiplexed address and data pins also required additional logic.
Although National Semiconductor had second source agreements with Signetics and Rockwell Semiconductor, neither company produced the PACE design. The PACE was followed by the INS8900, which had the same architecture but was implemented in nMOS. This version made electrical interfacing easier and also fixed several bugs in the PACE logic and increased the speed by about 50%. By the time it was available, higher-performance 16-bit CPUs were appearing, and the company began to deemphasize sales of the line.
The PACE was packaged in a 40-pin dual in-line package (DIP), originally in ceramic. As it was based on pMOS logic, the PACE series required three supply voltages, +5V (VSS, pin 20), +3V (VBB, pin 23) and -12V as the ground level (VGG, pin 29). The +3V level was normally supplied using simple electronics fed by the +5V line, thus reducing the complexity of the power supply.
The chip was normally driven using an external 750 nanosecond clock (1.33 MHz) using the System Timing Element, STE, chip to produce signals of the required signal strength. As these signals were also used by external devices, the clock signals were at TTL levels, +5V, in contrast to most pins which were at +8V.
As the external signals were presented at the +8V level, interfacing the system with common devices working at TTL levels was not trivial. For this reason, systems using the PACE normally included a Bidirectional Transceiver Element, BTE. This worked in conjunction with the PACE to produce a complete set of bus signals at TTL voltages that could then be used to easily interface with most contemporary devices like SRAM.
In order to fit 16-bit addresses and data onto a 40-pin DIP, the same set of 16 pins was multiplexed between presenting an address and reading and writing data on separate cycles. This required the external devices, like the main memory, to latch the address between cycles.
National Semiconductor's IMP-16 had been inspired by the Data General Nova but had a number of minor differences in its ISA. Among these was the handling of the four user-accessible 16-bit processor registers. In the Nova, the first two registers were general-purpose accumulators and used for most basic arithmetic and logic operations, while the second two could be used as operands or used as index registers. The IMP-16 followed this model, but the PACE changed a number of instructions so that they operated only on the first accumulator, AC0.
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National Semiconductor PACE
National Semiconductor's IPC-16A PACE, short for "Processing and Control Element", was the first commercial single-chip 16-bit microprocessor, announced in late 1974. It was a single-chip implementation of their early 1973 five-chip IMP-16 architecture, which in turn had been inspired by the Data General Nova minicomputer. To the basic IMP-16, PACE added a new operational mode, "byte mode", which was useful for working with 8-bit data like ASCII text.
Implemented in pMOS, as was common for the era, PACE required three supply voltages and an external clock with enough signal to drive the internal logic. This was normally supplied by the STE chip. Most PACE systems also required the BTE chip to convert the higher internal voltage signals to TTL levels used by the rest of the system. Its multiplexed address and data pins also required additional logic.
Although National Semiconductor had second source agreements with Signetics and Rockwell Semiconductor, neither company produced the PACE design. The PACE was followed by the INS8900, which had the same architecture but was implemented in nMOS. This version made electrical interfacing easier and also fixed several bugs in the PACE logic and increased the speed by about 50%. By the time it was available, higher-performance 16-bit CPUs were appearing, and the company began to deemphasize sales of the line.
The PACE was packaged in a 40-pin dual in-line package (DIP), originally in ceramic. As it was based on pMOS logic, the PACE series required three supply voltages, +5V (VSS, pin 20), +3V (VBB, pin 23) and -12V as the ground level (VGG, pin 29). The +3V level was normally supplied using simple electronics fed by the +5V line, thus reducing the complexity of the power supply.
The chip was normally driven using an external 750 nanosecond clock (1.33 MHz) using the System Timing Element, STE, chip to produce signals of the required signal strength. As these signals were also used by external devices, the clock signals were at TTL levels, +5V, in contrast to most pins which were at +8V.
As the external signals were presented at the +8V level, interfacing the system with common devices working at TTL levels was not trivial. For this reason, systems using the PACE normally included a Bidirectional Transceiver Element, BTE. This worked in conjunction with the PACE to produce a complete set of bus signals at TTL voltages that could then be used to easily interface with most contemporary devices like SRAM.
In order to fit 16-bit addresses and data onto a 40-pin DIP, the same set of 16 pins was multiplexed between presenting an address and reading and writing data on separate cycles. This required the external devices, like the main memory, to latch the address between cycles.
National Semiconductor's IMP-16 had been inspired by the Data General Nova but had a number of minor differences in its ISA. Among these was the handling of the four user-accessible 16-bit processor registers. In the Nova, the first two registers were general-purpose accumulators and used for most basic arithmetic and logic operations, while the second two could be used as operands or used as index registers. The IMP-16 followed this model, but the PACE changed a number of instructions so that they operated only on the first accumulator, AC0.