Recent from talks
Knowledge base stats:
Talk channels stats:
Members stats:
Rock (processor)
Rock (or ROCK) was a multithreading, multicore, SPARC microprocessor under development at Sun Microsystems. Canceled in 2010, it was a separate project from the SPARC T-Series (CoolThreads/Niagara) family of processors.
Rock aimed at higher per-thread performance, higher floating-point performance, and greater SMP scalability than the Niagara family. The Rock processor targeted traditional high-end data-facing workloads, such as back-end database servers, as well as floating-point intensive high-performance computing workloads, whereas the Niagara family targets network-facing workloads such as web servers.
The Rock processor implements the 64-bit SPARC V9 instruction set and the VIS 3.0 SIMD multimedia instruction set extension. Each Rock processor has 16 cores, with each core capable of running two threads simultaneously, yielding 32 threads per chip. Servers built with Rock use FB-DIMMs to increase reliability, speed and density of memory systems. The Rock processor uses a 65 nm manufacturing process for a design frequency of 2.3 GHz. The maximum power consumption of the Rock processor chip is approximately 250 W.
The 16 cores in Rock are arranged in four core clusters. The cores in a cluster share a 32 KB instruction cache, two 32 KB data caches, and two floating point units. Sun designed the chip this way because server workloads usually have high re-utilization in data and instruction across processes and threads but low number of floating-point operations in general. Thus sharing hardware resources among the four cores in a cluster leads to significant savings in area and power but low impact to performance.
In 2005, Sun publicly disclosed a feature in the Rock processor called hardware scout. Hardware scout uses otherwise idle chip execution resources to perform prefetching during cache misses.
In March 2006, Marc Tremblay, Vice President and Chief Architect for Sun's Scalable Systems Group, gave a presentation at the Xerox Palo Alto Research Center (PARC) on thread-level parallelism, hardware scouting, and thread-level speculation. These multithreading technologies were expected to be included in the Rock processor.
In August 2007, Sun confirmed that Rock would be the first production processor to support transactional memory. To provide the functionality, two new instructions were introduced (chkpt, commit) with one new status register (cps). The instruction chkpt <fail_pc> is used to begin a transaction and commit to commit the transaction. If transaction abort condition is detected, jump to <fail_pc> is issued and cps can be used to determine the reason. The support is best-effort based, as in addition to data conflicts, transactions can be aborted by other reasons. These include TLB misses, interrupts, certain commonly used function call sequences and "difficult" instructions (e.g., division). Nevertheless, many (arguably fine-grained) code blocks requiring synchronization could have benefited from transactional memory support of the Rock processor.
In February 2008, Marc Tremblay announced a unique feature called "out-of-order retirement" at the ISSCC. The benefits include replacing the "traditional instruction window with this much smaller deferred queue".
Hub AI
Rock (processor) AI simulator
(@Rock (processor)_simulator)
Rock (processor)
Rock (or ROCK) was a multithreading, multicore, SPARC microprocessor under development at Sun Microsystems. Canceled in 2010, it was a separate project from the SPARC T-Series (CoolThreads/Niagara) family of processors.
Rock aimed at higher per-thread performance, higher floating-point performance, and greater SMP scalability than the Niagara family. The Rock processor targeted traditional high-end data-facing workloads, such as back-end database servers, as well as floating-point intensive high-performance computing workloads, whereas the Niagara family targets network-facing workloads such as web servers.
The Rock processor implements the 64-bit SPARC V9 instruction set and the VIS 3.0 SIMD multimedia instruction set extension. Each Rock processor has 16 cores, with each core capable of running two threads simultaneously, yielding 32 threads per chip. Servers built with Rock use FB-DIMMs to increase reliability, speed and density of memory systems. The Rock processor uses a 65 nm manufacturing process for a design frequency of 2.3 GHz. The maximum power consumption of the Rock processor chip is approximately 250 W.
The 16 cores in Rock are arranged in four core clusters. The cores in a cluster share a 32 KB instruction cache, two 32 KB data caches, and two floating point units. Sun designed the chip this way because server workloads usually have high re-utilization in data and instruction across processes and threads but low number of floating-point operations in general. Thus sharing hardware resources among the four cores in a cluster leads to significant savings in area and power but low impact to performance.
In 2005, Sun publicly disclosed a feature in the Rock processor called hardware scout. Hardware scout uses otherwise idle chip execution resources to perform prefetching during cache misses.
In March 2006, Marc Tremblay, Vice President and Chief Architect for Sun's Scalable Systems Group, gave a presentation at the Xerox Palo Alto Research Center (PARC) on thread-level parallelism, hardware scouting, and thread-level speculation. These multithreading technologies were expected to be included in the Rock processor.
In August 2007, Sun confirmed that Rock would be the first production processor to support transactional memory. To provide the functionality, two new instructions were introduced (chkpt, commit) with one new status register (cps). The instruction chkpt <fail_pc> is used to begin a transaction and commit to commit the transaction. If transaction abort condition is detected, jump to <fail_pc> is issued and cps can be used to determine the reason. The support is best-effort based, as in addition to data conflicts, transactions can be aborted by other reasons. These include TLB misses, interrupts, certain commonly used function call sequences and "difficult" instructions (e.g., division). Nevertheless, many (arguably fine-grained) code blocks requiring synchronization could have benefited from transactional memory support of the Rock processor.
In February 2008, Marc Tremblay announced a unique feature called "out-of-order retirement" at the ISSCC. The benefits include replacing the "traditional instruction window with this much smaller deferred queue".