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SPARC64 V
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SPARC64 V
The SPARC64 V (Zeus) is a SPARC V9 microprocessor designed by Fujitsu. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers.
The servers series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+ and XII. The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later Oracle) SPARC Enterprise M-Series servers. In addition to servers, a version of the SPARC64 VII was also used in the commercially available Fujitsu FX1 supercomputer. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers.
The supercomputer series was based on the SPARC64 VII, and are the SPARC64 VIIfx, IXfx, and XIfx. The SPARC64 VIIIfx was used in the K computer, and the SPARC64 IXfx in the commercially available PRIMEHPC FX10. As of July 2016, the SPARC64 XIfx is the latest supercomputer processor, and it is used in the Fujitsu PRIMEHPC FX100 supercomputer.
In the late 1990s, HAL Computer Systems, a subsidiary of Fujitsu, was designing a successor to the SPARC64 GP as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide superscalar organization with superspeculation, an L1 instruction trace cache, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions and data. It was designed in Fujitsu's CS85 process, a 0.17 μm CMOS process with six levels of copper interconnect; and would have consisted of 65 million transistors on a 380 mm2 die. Originally scheduled for a late 2001 release in Fujitsu GranPower servers, it was canceled in mid-2001 when HAL was closed by Fujitsu, and replaced by a Fujitsu design.
The first Fujitsu SPARC64 Vs were fabricated in December 2001. They operated at 1.1 to 1.35 GHz. Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+. The SPARC64 V was used by Fujitsu in their PRIMEPOWER servers.
The SPARC64 V was first presented at Microprocessor Forum 2002. At introduction, it had the highest clock frequency of both SPARC and 64-bit server processors in production; and the highest SPEC rating of any SPARC processor.
The SPARC64 V is a four-issue superscalar microprocessor with out-of-order execution. It was based on the Fujitsu GS8900 mainframe microprocessor.
The SPARC64 V fetches up to eight instructions from the instruction cache during the first stage and places them into a 48-entry instruction buffer. In the next stage, four instructions are taken from this buffer, decoded and issued to the appropriate reserve stations. The SPARC64 V has six reserve stations, two that serve the integer units, one for the address generators, two for the floating-point units, and one for branch instructions. Each integer, address generator and floating-point unit has an eight-entry reserve station. Each reserve station can dispatch an instruction to its execution unit. Which instruction is dispatched firstly depends on operand availability and then its age. Older instructions are given higher priority than newer ones. The reserve stations can dispatch instructions speculatively (speculative dispatch). That is, instructions can be dispatched to the execution units even when their operands are not yet available but will be when execution begins. During stage six, up to six instructions are dispatched.
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SPARC64 V AI simulator
(@SPARC64 V_simulator)
SPARC64 V
The SPARC64 V (Zeus) is a SPARC V9 microprocessor designed by Fujitsu. The SPARC64 V was the basis for a series of successive processors designed for servers, and later, supercomputers.
The servers series are the SPARC64 V+, VI, VI+, VII, VII+, X, X+ and XII. The SPARC64 VI and its successors up to the VII+ were used in the Fujitsu and Sun (later Oracle) SPARC Enterprise M-Series servers. In addition to servers, a version of the SPARC64 VII was also used in the commercially available Fujitsu FX1 supercomputer. As of October 2017, the SPARC64 XII is the latest server processor, and it is used in the Fujitsu and Oracle M12 servers.
The supercomputer series was based on the SPARC64 VII, and are the SPARC64 VIIfx, IXfx, and XIfx. The SPARC64 VIIIfx was used in the K computer, and the SPARC64 IXfx in the commercially available PRIMEHPC FX10. As of July 2016, the SPARC64 XIfx is the latest supercomputer processor, and it is used in the Fujitsu PRIMEHPC FX100 supercomputer.
In the late 1990s, HAL Computer Systems, a subsidiary of Fujitsu, was designing a successor to the SPARC64 GP as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide superscalar organization with superspeculation, an L1 instruction trace cache, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions and data. It was designed in Fujitsu's CS85 process, a 0.17 μm CMOS process with six levels of copper interconnect; and would have consisted of 65 million transistors on a 380 mm2 die. Originally scheduled for a late 2001 release in Fujitsu GranPower servers, it was canceled in mid-2001 when HAL was closed by Fujitsu, and replaced by a Fujitsu design.
The first Fujitsu SPARC64 Vs were fabricated in December 2001. They operated at 1.1 to 1.35 GHz. Fujitsu's 2003 SPARC64 roadmap showed that the company planned a 1.62 GHz version for release in late 2003 or early 2004, but it was canceled in favor of the SPARC64 V+. The SPARC64 V was used by Fujitsu in their PRIMEPOWER servers.
The SPARC64 V was first presented at Microprocessor Forum 2002. At introduction, it had the highest clock frequency of both SPARC and 64-bit server processors in production; and the highest SPEC rating of any SPARC processor.
The SPARC64 V is a four-issue superscalar microprocessor with out-of-order execution. It was based on the Fujitsu GS8900 mainframe microprocessor.
The SPARC64 V fetches up to eight instructions from the instruction cache during the first stage and places them into a 48-entry instruction buffer. In the next stage, four instructions are taken from this buffer, decoded and issued to the appropriate reserve stations. The SPARC64 V has six reserve stations, two that serve the integer units, one for the address generators, two for the floating-point units, and one for branch instructions. Each integer, address generator and floating-point unit has an eight-entry reserve station. Each reserve station can dispatch an instruction to its execution unit. Which instruction is dispatched firstly depends on operand availability and then its age. Older instructions are given higher priority than newer ones. The reserve stations can dispatch instructions speculatively (speculative dispatch). That is, instructions can be dispatched to the execution units even when their operands are not yet available but will be when execution begins. During stage six, up to six instructions are dispatched.