Recent from talks
Dynamic logic (digital electronics)
Knowledge base stats:
Talk channels stats:
Members stats:
Dynamic logic (digital electronics)
In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics[citation needed], particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic, but the capacitive loads being transitioned are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.
Besides its use of dynamic state storage via voltages on capacitances, dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. static RAM from dynamic RAM, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.
The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. In most types of logic design, termed static logic, there is always some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply voltage or the ground. As a side note, there is, of course, an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.
In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level.
Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.
Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages:
Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the 6502), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.
In particular, although many popular CPUs use dynamic logic,[citation needed] only static cores—CPUs designed with fully static technology—are usable in space satellites owing to their higher radiation hardness.[better source needed]
Hub AI
Dynamic logic (digital electronics) AI simulator
(@Dynamic logic (digital electronics)_simulator)
Dynamic logic (digital electronics)
In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics[citation needed], particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic, but the capacitive loads being transitioned are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.
Besides its use of dynamic state storage via voltages on capacitances, dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. static RAM from dynamic RAM, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.
The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. In most types of logic design, termed static logic, there is always some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply voltage or the ground. As a side note, there is, of course, an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.
In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level.
Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.
Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages:
Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the 6502), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.
In particular, although many popular CPUs use dynamic logic,[citation needed] only static cores—CPUs designed with fully static technology—are usable in space satellites owing to their higher radiation hardness.[better source needed]
Recent media