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System Management Bus
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System Management Bus
The System Management Bus (SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in chipsets of computer motherboards for communication with the power source for ON/OFF instructions. The exact functionality and hardware interfaces vary with vendors.
It is derived from I²C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery System and ACPI). Other devices might include external master hosts, temperature sensor, fan or voltage sensors, lid switches, clock generator, and RGB lighting. Peripheral Component Interconnect (PCI) add-in cards may connect to an SMBus segment.
A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of errors, accept control parameters, return status over SMBus, and poll chipset registers. The SMBus is generally not user configurable or accessible. Although SMBus devices usually can't identify their functionality, a new PMBus coalition has extended SMBus to include conventions allowing that.
The SMBus was defined by Intel and Duracell in 1994. It carries clock, data, and instructions and is based on Philips' I²C serial bus protocol. Its clock frequency range is 10 kHz to 100 kHz. (PMBus extends this to 400 kHz.) Its voltage levels and timings are more strictly defined than those of I²C, but devices belonging to the two systems are often successfully mixed on the same bus. [citation needed]
SMBus is used as an interconnect in several platform management standards including: Alert Standard Format (ASF), Desktop and mobile Architecture for System Hardware (DASH), Intelligent Platform Management Interface (IPMI).
SMBus is used to access DRAM configuration information as part of serial presence detect (SPD). SMBus has grown into a wide variety of system enumeration use cases other than power management.
While SMBus is derived from I²C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.
When mixing devices, the I²C specification defines the input levels to be 30% and 70% of the supply voltage VDD, which may be 5 V, 3.3 V, or any other value. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed. SMBus 2.0 defines VIL,max at 0.8 V and VIH,min at 2.1 V, and supports a VDD ranging from 3 to 5 V, while in SMBus 3.0, the levels are defined at 0.8 and 1.35 V, with a VDD ranging from 1.8 to 5 V.
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System Management Bus
The System Management Bus (SMBus or SMB) is a single-ended simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in chipsets of computer motherboards for communication with the power source for ON/OFF instructions. The exact functionality and hardware interfaces vary with vendors.
It is derived from I²C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery System and ACPI). Other devices might include external master hosts, temperature sensor, fan or voltage sensors, lid switches, clock generator, and RGB lighting. Peripheral Component Interconnect (PCI) add-in cards may connect to an SMBus segment.
A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of errors, accept control parameters, return status over SMBus, and poll chipset registers. The SMBus is generally not user configurable or accessible. Although SMBus devices usually can't identify their functionality, a new PMBus coalition has extended SMBus to include conventions allowing that.
The SMBus was defined by Intel and Duracell in 1994. It carries clock, data, and instructions and is based on Philips' I²C serial bus protocol. Its clock frequency range is 10 kHz to 100 kHz. (PMBus extends this to 400 kHz.) Its voltage levels and timings are more strictly defined than those of I²C, but devices belonging to the two systems are often successfully mixed on the same bus. [citation needed]
SMBus is used as an interconnect in several platform management standards including: Alert Standard Format (ASF), Desktop and mobile Architecture for System Hardware (DASH), Intelligent Platform Management Interface (IPMI).
SMBus is used to access DRAM configuration information as part of serial presence detect (SPD). SMBus has grown into a wide variety of system enumeration use cases other than power management.
While SMBus is derived from I²C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.
When mixing devices, the I²C specification defines the input levels to be 30% and 70% of the supply voltage VDD, which may be 5 V, 3.3 V, or any other value. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed. SMBus 2.0 defines VIL,max at 0.8 V and VIH,min at 2.1 V, and supports a VDD ranging from 3 to 5 V, while in SMBus 3.0, the levels are defined at 0.8 and 1.35 V, with a VDD ranging from 1.8 to 5 V.