Recent from talks
XAUI
Knowledge base stats:
Talk channels stats:
Members stats:
XAUI
10 Gigabit Attachment Unit Interface (XAUI /ˈzaʊi/ ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface".
The purpose of the XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board.
XGMII Extender has the following characteristics:
The following is a list of the major concepts of XGXS and XAUI:
Reduced Pin eXtended Attachment Unit Interface (RXAUI) is a proprietary modification created by Marvell and Dune Networks (later acquired by Broadcom) aimed to increase the port density by decreasing the interface pin count. The four lanes of the standard XAUI running at 3.125 Gbit/s are replaced by two lanes at 6.25 Gbit/s. Thus 16 pins of an integrated circuit (4 transmit + 4 receive differential pairs) can provide either one XAUI port or two RXAUI ports.
The specification also defines a XAUI to RXAUI adapter and provides an implementation as Verilog RTL code. FPGA vendors are offering their own implementations as IP blocks.
The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a printed circuit board. Where the XGMII is electrically limited to distances of approximately 7 cm, the XGMII Extender allows distances up to approximately 50 cm.
The XGMII Extender supports the 10 Gbit/s data rate of the XGMII. The 10 Gbit/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 gigabaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.
Hub AI
XAUI AI simulator
(@XAUI_simulator)
XAUI
10 Gigabit Attachment Unit Interface (XAUI /ˈzaʊi/ ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface".
The purpose of the XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board.
XGMII Extender has the following characteristics:
The following is a list of the major concepts of XGXS and XAUI:
Reduced Pin eXtended Attachment Unit Interface (RXAUI) is a proprietary modification created by Marvell and Dune Networks (later acquired by Broadcom) aimed to increase the port density by decreasing the interface pin count. The four lanes of the standard XAUI running at 3.125 Gbit/s are replaced by two lanes at 6.25 Gbit/s. Thus 16 pins of an integrated circuit (4 transmit + 4 receive differential pairs) can provide either one XAUI port or two RXAUI ports.
The specification also defines a XAUI to RXAUI adapter and provides an implementation as Verilog RTL code. FPGA vendors are offering their own implementations as IP blocks.
The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a printed circuit board. Where the XGMII is electrically limited to distances of approximately 7 cm, the XGMII Extender allows distances up to approximately 50 cm.
The XGMII Extender supports the 10 Gbit/s data rate of the XGMII. The 10 Gbit/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 gigabaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.