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2 nm process AI simulator
(@2 nm process_simulator)
Hub AI
2 nm process AI simulator
(@2 nm process_simulator)
2 nm process
In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.
The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.
As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.
TSMC began risk production of its 2 nm process in July 2024, with mass production planned for the second half of 2025, and Samsung plans to start production in 2025. Intel initially forecasted production in 2024 but scrapped its 2 nm node in favor of the smaller 18 angstrom (18A) node.
By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of gate-all-around FET (GAAFET): horizontal and vertical nanowires, horizontal nanosheet transistors (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors, complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors and negative-capacitance FET (NC-FET) which uses drastically different materials.
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.[needs update] TSMC began research on 2 nm in 2019—expecting to transition from FinFET to GAAFET.[needs update] In July 2021, TSMC received governmental approval to build its 2 nm plant. In August 2020, it began building a research and development lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.[needs update] In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand.[needs update] According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023.[needs update] According to Nikkei, the company at that time expected to have been installing production equipment for 2 nm by 2023.[needs update]
Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027, respectively, and in December 2019 announced plans for 1.4 nm production in 2029.[needs update]
At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.[needs update]
2 nm process
In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.
The term "2 nanometer", or alternatively "20 angstrom" (a term used by Intel), has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.
As such, 2 nm is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous 3 nm node generation.
TSMC began risk production of its 2 nm process in July 2024, with mass production planned for the second half of 2025, and Samsung plans to start production in 2025. Intel initially forecasted production in 2024 but scrapped its 2 nm node in favor of the smaller 18 angstrom (18A) node.
By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of gate-all-around FET (GAAFET): horizontal and vertical nanowires, horizontal nanosheet transistors (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors, complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors and negative-capacitance FET (NC-FET) which uses drastically different materials.
In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.[needs update] TSMC began research on 2 nm in 2019—expecting to transition from FinFET to GAAFET.[needs update] In July 2021, TSMC received governmental approval to build its 2 nm plant. In August 2020, it began building a research and development lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021.[needs update] In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand.[needs update] According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023.[needs update] According to Nikkei, the company at that time expected to have been installing production equipment for 2 nm by 2023.[needs update]
Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027, respectively, and in December 2019 announced plans for 1.4 nm production in 2029.[needs update]
At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as 2 nm, as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.[needs update]