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Burst mode (computing)
Burst mode (computing)
Burst mode (computing)
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from Wikipedia

Burst mode is a generic electronics term referring to any situation in which a device is transmitting data repeatedly without going through all the steps required to transmit each piece of data in a separate transaction.

Advantages

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The main advantage of burst mode over single mode is that the burst mode typically increases the throughput of data transfer. Any bus transaction is typically handled by an arbiter, which decides when it should change the granted master and slaves. In case of burst mode, it is usually more efficient if you allow a master to complete a known length transfer sequence.

The total delay in a data transaction can be typically written as a sum of initial access latency plus sequential access latency.

Here the sequential latency is same in both single mode and burst mode, but the total initial latency is decreased in burst mode, since the initial delay (usually depends on FSM for the protocol) is caused only once in burst mode. Hence the total latency of the burst transfer is reduced, and hence the data transfer throughput is increased.

It can also be used by slaves that can optimise their responses if they know in advance how many data transfers there will be. The typical example here is a DRAM which has a high initial access latency, but sequential accesses after that can be performed with fewer wait states.[1]

Beats in burst transfer

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A beat in a burst transfer is the number of write (or read) transfers from master to slave, that takes place continuously in a transaction. In a burst transfer, the address for write or read transfer is just an incremental value of previous address. Hence in a 4-beat incremental burst transfer (write or read), if the starting address is 'A', then the consecutive addresses will be 'A+m', 'A+2*m', 'A+3*m'. Similarly, in a 8-beat incremental burst transfer (write or read), the addresses will be 'A', 'A+n', 'A+2*n', 'A+3*n', 'A+4*n', 'A+5*n', 'A+6*n', 'A+7*n'.

Example

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Q:- A certain SoC master uses a burst mode to communicate (write or read) with its peripheral slave. The transaction contains 32 write transfers. The initial latency for the write transfer is 8ns and burst sequential latency is 0.5ns. Calculate the total latency for single mode (no-burst mode), 4-beat burst mode, 8-beat burst mode and 16-beat burst mode. Calculate the throughput factor increase for each burst mode.

Sol:-

Total latency of single mode = num_transfers x (tinitial + tsequential) = 32 x (8 + 1x(0.5)) = 32 x 8.5 = 272 ns


Total latency of one 4-beat burst mode = (tinitial + tsequential) = 8 + 4x(0.5) = 10 ns
For 32 write transactions, required 4-beat transfers = 32/4 = 8
Hence, total latency of 32 write transfers = 10 x 8 = 80 ns
Total throughput increase factor using 4-beat burst mode = single mode latency/(total burst mode latency) = 272/80 = 3.4


Total latency of one 8-beat burst mode = (tinitial + tsequential) = 8 + 8x(0.5) = 12 ns
For 32 write transactions, required 8-beat transfers = 32/8 = 4
Hence, total latency of 32 write transfers = 12 x 4 = 48 ns
Total throughput increase factor using 8-beat burst mode = single mode latency/(total burst mode latency) = 272/48 = 5.7


Total latency of one 16-beat burst mode = (tinitial + tsequential) = 8 + 16x(0.5) = 16 ns
For 32 write transactions, required 16-beat transfers = 32/16 = 2
Hence, total latency of 32 write transfers = 16 x 2 = 32 ns
Total throughput increase factor using 16-beat burst mode = single mode latency/(total burst mode latency) = 272/32 = 8.5


From the above calculations, we can conclude that the throughput increases with the number of beats.


Details

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The usual reason for having a burst mode capability, or using burst mode, is to increase data throughput.[2] The steps left out while performing a burst mode transaction may include:

  • Waiting for input from another device
  • Waiting for an internal process to terminate before continuing the transfer of data
  • Transmitting information which would be required for a complete transaction, but which is inherent in the use of burst mode[3]

In the case of DMA, the DMA controller and the device are given exclusive access to the bus without interruption; the CPU is also freed from handling device interrupts.

The actual manner in which burst modes work varies from one type of device to another; however, devices that have some sort of a standard burst mode include the following:

See also

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References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Burst mode (computing)

View on Grokipedia
from Grokipedia
Burst mode in computing refers to a transfer technique in which a device transmits multiple units of in rapid succession, often at a higher speed than normal operational rates, to minimize the overhead of repeated setup and teardown processes associated with individual transfers. This approach is widely used across various hardware and contexts to enhance by amortizing fixed costs, such as decoding or , over larger blocks. Common in both synchronous and asynchronous designs, burst mode contrasts with single-cycle or continuous streaming transfers by allowing temporary high-throughput bursts separated by idle periods. In memory systems, particularly (DRAM) like DDR variants, burst mode enables the sequential access of multiple consecutive words from the same row using a single initial address setup, reducing latency for subsequent accesses after the first one incurs the full row delay. Modern DRAM architectures, such as DDR3 and GDDR4, operate exclusively in burst mode, transferring fixed-length bursts (e.g., 8 words), while GDDR3 uses 4 words; into an internal buffer before serializing them at interface speed, which can achieve effective bandwidths exceeding 100 GB/s in multi-channel GPU configurations like NVIDIA's GTX280 with GDDR3. This pipelined mechanism discards unused data for non-sequential requests but optimizes for common sequential workloads in caching and . Burst mode memories also improve cache refill times, allowing a four-word cache line to be loaded in as few as five clock cycles. In (DMA) operations, burst mode—also known as block mode—allows the DMA controller to seize full control of the and transfer an entire block of between peripherals and without releasing it after each unit, thereby minimizing CPU interruptions and bus contention. This is particularly beneficial for high-volume transfers, such as in storage I/O or rendering, where the DMA halts the processor temporarily to complete the burst, achieving higher throughput than cycle-by-cycle or cycle-steal modes. For instance, in systems using controllers like the 8257, burst mode supports efficient bulk movement by prioritizing contiguous blocks over interleaved CPU access. Beyond memory and DMA, burst mode appears in communication protocols and asynchronous circuits, where it facilitates bursty traffic patterns in networks like Ethernet or passive optical networks (PONs), sending discrete data packets with minimal inter-burst gaps to simulate real-world variable loads. In FPGA serial interfaces, such as Intel's Serial Lite III, it supports applications like by streams with configurable gaps of one or two clock cycles between bursts. In asynchronous finite-state machines (FSMs), burst-mode specification defines hazard-free controllers that process input bursts under speed-independent assumptions, enabling robust synthesis for low-power embedded systems. Overall, these implementations underscore burst mode's role in balancing performance, power, and latency across computing domains.

Fundamentals

Definition

Burst mode in computing refers to a transfer technique in which multiple sequential units, such as words or blocks of , are moved from a source to a destination in a single, uninterrupted operation. This approach allows for the efficient handling of contiguous sequences by minimizing repetitive setup processes during the transfer. A key distinction from single-cycle transfers lies in the handling of initiation overhead: in burst mode, the address and control signals are established once at the start of the burst, after which subsequent data units are transferred without reissuing these signals, thereby achieving higher effective throughput for sequential accesses. The concept of burst mode originated in the context of early computer architectures during the 1960s and 1970s, particularly with the introduction of the in 1964, where it described a channel operation in which a single input/output device exclusively captures the multiplexor channel from selection until the last byte is serviced, enabling fast data rates for high-speed peripherals like tape units and . This innovation optimized memory access patterns in mainframe systems by supporting overlapped processing and burst operations on selector channels.

Basic Principles

In burst mode, the initial and control signals are set up once at the beginning of the transfer sequence, allowing the system to this starting point for efficient subsequent operations. This latching mechanism captures the base on the rising edge of the clock during the command phase, eliminating the need to respecify the for each unit. Subsequent transfers then proceed using internally generated sequential or incremented addresses, typically managed by an on-chip counter that advances automatically without additional external signaling. The burst length plays a central role in defining the scope of each transfer operation, specifying the fixed or programmable number of consecutive units to be moved in a single burst. Common lengths include 1, 2, 4, 8, or full-page accesses, configured via a mode register or hardware protocol at initialization to match the system's requirements. This parameter determines how many cycles the burst will span, optimizing for the expected access patterns while adhering to the device's capabilities, such as those in (SDRAM) implementations. Synchronization in burst mode relies on the to coordinate all phases of the transfer, ensuring reliable timing after the initial command. Data units are transferred on consecutive rising (or both rising and falling) edges of the clock, starting immediately following the latch and control assertion. This clock-driven approach maintains alignment between the and the target device, enabling high-speed pipelined operations without desynchronization.

Technical Aspects

Transfer Mechanics

In burst mode transfers, the process typically unfolds in distinct phases to optimize data movement across hardware interfaces such as memory buses. The command phase initiates the transfer by asserting the starting address and control signals, including direction (read or write), burst length, and transfer type, all within a single clock cycle to minimize overhead. This phase ensures that the target device, such as a , receives precise instructions before data exchange begins. Following the command phase, the data phase commences, spanning multiple clock cycles proportional to the configured burst length, during which the actual payload is transferred sequentially from consecutive addresses. For instance, in protocols like AMBA AHB, this phase overlaps with the address phase of the next potential transfer, allowing pipelined efficiency while the source or handles the . An optional termination phase may follow if the burst is interrupted early, signaled by a control command that halts the sequence and releases bus resources, preventing unnecessary cycles. Burst enable signals facilitate the coordination of these phases by indicating the initiation and extent of the transfer. These are often implemented as dedicated hardware pins or register flags that the burst parameters; in synchronous DRAM (SDRAM), for example, the burst length (typically 1, 2, 4, or 8 words) is programmed into a mode register via a load command, and the transfer is enabled by asserting control pins like /RAS (row address strobe), /CAS (column address strobe), and /WE (write enable) during the read or write operation. This configuration signals the memory device to automatically increment addresses and sustain data output or input over the specified cycles without repeated addressing. Error handling in burst transfers integrates mechanisms like parity bits or error-correcting code (ECC) to maintain across the multi-cycle data phase, as single-bit errors can propagate in sequential accesses. Basic parity checks compute an overall even or odd bit count for the burst , flagging discrepancies upon completion, while ECC schemes, such as Hamming codes, append check bits transferred alongside the data to detect and correct single- or double-bit errors in real-time during the transfer. In systems supporting ECC, these bits are stored and retrieved with each burst segment, ensuring the entire payload's reliability without halting the protocol.

Beats in Burst Transfer

In burst transfer protocols such as the AMBA AXI specification, a beat represents a single clock cycle or timing unit within a burst during which one unit of is transferred. The size of the data unit per beat is determined by the bus width and configuration signals like AxSIZE, which specifies the number of bytes transferred per beat (e.g., , 16, 32, 64, or 128 bytes). Each beat requires a between the master and slave using VALID and READY signals, synchronized to the rising edge of the clock, ensuring the transfer completes in one cycle under ideal conditions without stalls. The total number of beats defines the burst length, such as 4 beats for a quad-word burst, where the burst length is encoded as AxLEN + 1 (ranging from 1 to 256 beats in AXI4, though limited to 16 in earlier versions). The duration of a burst transfer is calculated as the sum of an initial latency (in clock cycles for address setup and first data access) plus the number of beats, multiplied by the clock period:
Burst time=(initial latency+number of beats)×clock period\text{Burst time} = (\text{initial latency} + \text{number of beats}) \times \text{clock period}
For instance, with an initial latency of 3 cycles and 4 beats at a 200 MHz clock (5 ns period), the burst time is (3 + 4) × 5 ns = 35 ns. In advanced bus protocols, variations exist between full-beat and half-beat modes, where data edges align differently relative to the clock. Full-beat modes, common in single data rate (SDR) buses, transfer data on the rising clock edge only, with each beat occupying a full clock cycle. Half-beat modes, as in (DDR) buses, transfer data on both rising and falling edges, effectively halving the time per beat and doubling bandwidth without increasing clock frequency; for example, a 4-beat burst in DDR completes in 2 clock cycles versus 4 in SDR.

Benefits and Limitations

Advantages

Burst mode in computing significantly reduces overhead associated with data transfers by amortizing setup costs, such as address latching and command issuance, across multiple sequential units rather than per individual transfer. In traditional single-transfer modes, each data unit requires separate address decoding and control signaling, leading to substantial latency from repeated handshakes; burst mode mitigates this by internally generating subsequent addresses after an initial setup, allowing continuous data flow. This efficiency can yield throughput improvements of 2-10x for patterns, as demonstrated in synchronous memory systems where an eight-word burst read achieves nearly 3x faster performance compared to asynchronous single-word accesses at 40 MHz. By maximizing bus utilization during the data phase, burst mode enhances bandwidth efficiency, minimizing idle cycles that occur in byte-by-byte transfers where control overhead dominates. In burst operations, the bus remains occupied with consecutive data payloads after the initial address phase, enabling higher effective data rates without proportional increases in clock cycles. For instance, in AXI interconnect protocols, burst transfers can provide 4-5x bandwidth gains over equivalent single transfers by sustaining full bus saturation for extended sequences. Burst mode also contributes to power savings, particularly in low-power designs, by reducing the number of control signal toggles and address bus transitions required for multi-unit transfers. Fewer activations of address lines and related control circuitry lower dynamic power dissipation, which has become increasingly relevant for mobile computing applications since the early 2000s with the adoption of power-optimized synchronous memories. In advanced SRAM implementations, such techniques can achieve power reductions through minimized bitline differentials and wordline toggling in burst operations.

Disadvantages

Burst mode's requirement for a full-length transfer commitment can lead to significant latency penalties in scenarios involving random or non-contiguous accesses, as the must complete the entire burst sequence regardless of immediate needs. This fixed commitment occupies the bus for the duration of the burst, delaying subsequent requests and preventing early release for other operations. In cache systems, for instance, fetching a full cache line via burst transfer can impose waits of up to 4-8 cycles, corresponding to typical burst lengths, even when only a single word is required initially. Furthermore, burst mode's rigid sequential delivery order conflicts with optimization techniques like critical-word-first, where the most urgent is prioritized, resulting in prolonged effective latencies in practical workloads. Implementing burst mode introduces hardware complexity in the , necessitating specialized logic for burst counters, buffering to handle sequential transfers, and address prediction to optimize access patterns without repeated addressing. This additional circuitry increases die area and overall , particularly in early pre-1990s designs where such features demanded custom silicon without the benefits of mature process technologies. For example, the introduction of burst capabilities in processors like the 80486 required enhanced bus protocols and control logic, elevating design and manufacturing expenses compared to simpler single-transfer modes. The extended duration of transfers in burst mode heightens the potential for errors, as bit flips or transient faults can affect multiple consecutive data units, amplifying the impact of a single failure across the burst. To mitigate this, stronger error-correcting codes (ECC) are essential, capable of detecting and correcting burst errors that arise from large-scale faults like row or bank failures in DRAM. Such advanced ECC schemes, including tiered or interleaved codes, impose overheads in storage (e.g., additional parity bits) and processing, adding latency for error handling in high-reliability configurations.

Applications and Examples

In Memory and Cache Systems

In memory and cache systems, burst mode facilitates efficient data transfer by allowing sequential accesses within a pre-activated row or cache line, minimizing overhead from repeated address setups and s. This approach leverages spatial locality, where nearby data is likely to be accessed next, to reduce latency in hierarchical storage. In (DRAM), burst mode enables multiple column reads or writes after a single row , optimizing bandwidth in page-mode operations. In Synchronous DRAM (SDRAM) and its evolutions like Double Data Rate (DDR) SDRAM, burst mode supports programmable burst lengths typically of 1, 2, 4, or 8 words, or full-page access, where the row is pre-activated once to allow a series of column bursts without re-specifying the row address. This page-mode burst operation sequences data transfers internally, aligning with the memory clock for synchronous pipelining and improving throughput for sequential workloads. For instance, standards specify burst lengths of 2, 4, or 8, enabling efficient prefetching during read or write commands. Cache systems in processors employ burst mode to fill entire cache lines from main , typically loading 64-byte lines in bursts of 8 beats to exploit spatial locality and amortize transfer costs. In x86 architectures, this mechanism has been integral since the , where a single memory command triggers the burst fill of a cache line, allowing the CPU to continue execution while subsequent beats arrive. These bursts align with the bus width, such as 64 bits, to deliver the full line in sequential transfers. The evolution of burst mode in DRAM progressed from asynchronous implementations in Burst Extended Data Out (BEDO) DRAM, a variant of EDO, during the 1990s, which supported burst accesses without clock synchronization for faster page-mode operations, to fully synchronous bursts in modern DDR5 SDRAM introduced in the 2020s. DDR5 supports features like auto-precharge, which can automatically close the row at the end of a burst to prepare for subsequent activations, reducing manual command overhead and enhancing efficiency in high-bandwidth scenarios. In DDR5 SDRAM, the burst length is typically 16, doubling previous generations to enhance prefetching. This shift to synchronous operation with auto-precharge has enabled higher clock rates and better power management in contemporary memory hierarchies.

In Bus and Network Interfaces

In bus and network interfaces, burst mode enables efficient data transfer by allowing multiple sequential to be sent or received without re-establishing addressing or control overhead for each unit, as defined in the PCI Local Bus Specification Revision 2.3. This approach is particularly prominent in (PCI) and its successor, (PCIe), where burst transfers occur through memory read and write commands that increment addresses automatically after the initial setup. In PCI, burst mode supports variable-length transfers initiated by the master device, with the target providing data in successive clock cycles without additional address phases, optimizing throughput for applications like and storage controllers. Transitioning to PCIe, introduced in 2003, burst transfers are implemented via Transaction Layer Packets (TLPs) for memory operations, where the maximum payload size negotiates between devices during link training. In PCIe 1.0, the maximum payload size defaults to 128 bytes but can be negotiated up to 256 bytes. Subsequent generations like PCIe commonly support up to 512 bytes, and later versions such as PCIe 6.0 (ratified ) up to 4096 bytes, enabling higher bandwidth for peripherals such as network adapters and GPUs. In network interfaces, burst mode manifests in Direct Memory Access (DMA) operations within Ethernet controllers, particularly since the advent of in the late 1990s, where NICs aggregate multiple incoming packets into larger bursts before DMA transfer to host memory, thereby reducing CPU interrupt frequency and overhead. This packet aggregation in DMA engines allows for batched processing, improving efficiency in high-throughput scenarios like server networking, as seen in implementations that combine frames to form single large DMA writes, minimizing per-packet latency. For wireless networks, burst transmission via frame aggregation was introduced in IEEE 802.11n (ratified in 2009) to enhance , where multiple MAC Protocol Data Units (MPDUs) are concatenated into an Aggregate MPDU (A-MPDU) for transmission within a single transmission opportunity, reducing protocol overhead in dense environments. This mechanism, extended in 802.11ac with larger aggregation limits and wider channels, supports burst sizes up to 64 MPDUs or more, significantly boosting throughput for streaming and data-intensive applications over . It was further extended in 802.11ax (2019) with support for up to 256 MPDUs and in 802.11be (2024) with multi-link aggregation, enabling bursts over multiple frequency bands for throughputs exceeding 40 Gbps as of 2025.

References

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