DDR SDRAM

Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) widely used in computers and other electronic devices. It improves on earlier SDRAM technology by transferring data on both the rising and falling edges of the clock signal, effectively doubling the data rate without increasing the clock frequency. This technique, known as double data rate (DDR), allows for higher memory bandwidth while maintaining lower power consumption and reduced signal interference.

DDR SDRAM was first introduced in the late 1990s and is sometimes referred to as DDR1 to distinguish it from later generations. It has been succeeded by DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, and DDR5 SDRAM, each offering further improvements in speed, capacity, and efficiency. These generations are not backward or forward compatible, meaning memory modules from different DDR versions cannot be used interchangeably on the same motherboard.

DDR SDRAM typically transfers 64 bits of data at a time. Its effective transfer rate is calculated by multiplying the memory bus clock speed by two (for double data rate), then by the width of the data bus (64 bits), and dividing by eight to convert bits to bytes. For example, a DDR module with a 100 MHz bus clock has a peak transfer rate of 1600 megabytes per second (MB/s).

In the late 1980s IBM had built DRAMs using a dual-edge clocking feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard DRAM, not SDRAM.

Samsung demonstrated the first DDR SDRAM memory prototype in 1997, and released the first commercial DDR SDRAM chip (64 Mbit) in June 1998, followed soon after by Hyundai Electronics (now SK Hynix) the same year. The development of DDR began in 1996, before its specification was finalized by JEDEC in June 2000 (JESD79). JEDEC has set standards for the data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM was released in August 2000.

To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with common address lines are called a memory rank. The term was introduced to avoid confusion with chip internal rows and banks. A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The chip select signal is used to issue commands to specific rank.

Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multi-channel architecture.

Note: All items listed above are specified by JEDEC as JESD79F. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC – often they are simply manufacturer optimizations using tighter tolerances or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.