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COP400
The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller. COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. Some COP400 devices were second-sourced by Western Digital as the WD4200 family. In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series (e.g. the COP402 with designation КР1820ВЕ1).
The COP400 is implemented in CMOS or N-channel silicon gate MOS technology. It was typically packaged in 24- or 28-pin DIP packages. Instruction cycle time of the faster family members is 4 microseconds. The COP400 family offered several memory and pinout configurations.
Notable products that used COP400-family chips include the Apple Lisa, Milton Bradley and Mattel electronic games, Coleco Head to Head Basketball, the Grundy Newbrain, and others.
The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum.
Program memory consists of a 512, 1024, or 2048 × 8-bit ROM. ROM bytes may be program instructions, program data, or jump address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into pages of 64 bytes each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must sometimes be thought of as organized into blocks of 256 bytes.
Data memory consists of a 32, 64, or 128 × 4-bit RAM, organized as several data registers of 16 4-bit digits. RAM addressing is implemented by the 6- or 7-bit B register used as a pointer. The B register's upper 2 or 3 bits (Br) select one of 4 or 8 data registers and lower 4 bits (Bd) select one of 16 4-bit digits in the selected data register. The 4-bit contents of the RAM digit pointed to by the B register are usually loaded into, exchanged with, or operate on the A register.
The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 × 8 bits) and RAM (128 × 4 bits). Family members with only 512 or 1024 bytes of ROM will have only a 9- or 10-bit PC. Those with 64 or 32 locations of RAM will have only a 2-bit Br register.
The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register.
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COP400 AI simulator
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COP400
The COP400 or COP II is a 4-bit microcontroller family introduced in 1977 by National Semiconductor as a follow-on product to their original PMOS COP microcontroller. COP400 family members are complete microcomputers containing internal timing, logic, ROM, RAM, and I/O necessary to implement dedicated controllers. Some COP400 devices were second-sourced by Western Digital as the WD4200 family. In the Soviet Union several COP400 microcontrollers were manufactured as the 1820 series (e.g. the COP402 with designation КР1820ВЕ1).
The COP400 is implemented in CMOS or N-channel silicon gate MOS technology. It was typically packaged in 24- or 28-pin DIP packages. Instruction cycle time of the faster family members is 4 microseconds. The COP400 family offered several memory and pinout configurations.
Notable products that used COP400-family chips include the Apple Lisa, Milton Bradley and Mattel electronic games, Coleco Head to Head Basketball, the Grundy Newbrain, and others.
The COP400 uses separate memory spaces for ROM and RAM. ROM addresses are 11-bit maximum, while data addresses are 7-bit maximum.
Program memory consists of a 512, 1024, or 2048 × 8-bit ROM. ROM bytes may be program instructions, program data, or jump address pointers. Due to the special characteristics associated with the JP and JSRP instructions, ROM must often be conceived of as organized into pages of 64 bytes each. Also, because of the unique operations performed by the LQID and JID instructions, ROM pages must sometimes be thought of as organized into blocks of 256 bytes.
Data memory consists of a 32, 64, or 128 × 4-bit RAM, organized as several data registers of 16 4-bit digits. RAM addressing is implemented by the 6- or 7-bit B register used as a pointer. The B register's upper 2 or 3 bits (Br) select one of 4 or 8 data registers and lower 4 bits (Bd) select one of 16 4-bit digits in the selected data register. The 4-bit contents of the RAM digit pointed to by the B register are usually loaded into, exchanged with, or operate on the A register.
The register configuration shown in the diagram is for the COP400 family members with maximum ROM (2048 × 8 bits) and RAM (128 × 4 bits). Family members with only 512 or 1024 bytes of ROM will have only a 9- or 10-bit PC. Those with 64 or 32 locations of RAM will have only a 2-bit Br register.
The 4-bit A register (accumulator) is the source and destination register for most arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B register, to load and input 4 bits of the 8-bit Q latch data, to input 4 bits of the 8-bit L port and to perform data exchanges with the SIO register.