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DDR5 SDRAM
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on July 14, 2020.
A new feature called Decision Feedback Equalization (DFE) enables input/output (I/O) speed scalability for higher bandwidth and performance improvement. DDR5 has about the same 14 ns latency as DDR4 and DDR3. DDR5 octuples the maximum DIMM capacity from 64 GB to 512 GB. DDR5 also has higher frequencies than DDR4, up to 9600 MT/s is currently possible, 8200 MT/s translates into around 120 GB/s of bandwidth. Speeds of more than 13,000 MT/s have been achieved using liquid nitrogen.
Rambus announced a working DDR5 dual in-line memory module (DIMM) in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; running at 5.2 GT/s at 1.1 V. In February 2019, SK Hynix announced a 6.4 GT/s chip, the highest speed specified by the preliminary DDR5 standard. The first production DDR5 DRAM chip was officially launched by SK Hynix on October 6, 2020.
The separate JEDEC standard Low Power Double Data Rate 5 (LPDDR5), intended for laptops and smartphones, was released in February 2019.
Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules incorporate on-board voltage regulators in order to reach higher speeds.[failed verification]
In 2024 the first CUDIMM (clocked unbuffered DIMM) and CSODIMM (clocked SODIMM) modules were introduced together with Intel Arrow Lake. These modules include a component to re-drive the clock signal to help reach higher speeds. AMD does not support CUDIMM, though Zen 5 will accept CUDIMMs in bypass mode.
Unlike DDR4, all DDR5 chips have on-die error-correction code, that detects and corrects errors before sending data to the CPU, to improve reliability and allow denser RAM chips with higher per-chip defect rate to be used.
However, on-die error-correction code is not the same as true ECC memory with extra chips for correction data on the memory module. Non-ECC and ECC DDR5 DIMM variants still exist; as with earlier RAM, ECC variants have extra data chips and data lines to the CPU for the additional error-detection data (8 more bits per 64 bits).
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DDR5 SDRAM
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on July 14, 2020.
A new feature called Decision Feedback Equalization (DFE) enables input/output (I/O) speed scalability for higher bandwidth and performance improvement. DDR5 has about the same 14 ns latency as DDR4 and DDR3. DDR5 octuples the maximum DIMM capacity from 64 GB to 512 GB. DDR5 also has higher frequencies than DDR4, up to 9600 MT/s is currently possible, 8200 MT/s translates into around 120 GB/s of bandwidth. Speeds of more than 13,000 MT/s have been achieved using liquid nitrogen.
Rambus announced a working DDR5 dual in-line memory module (DIMM) in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; running at 5.2 GT/s at 1.1 V. In February 2019, SK Hynix announced a 6.4 GT/s chip, the highest speed specified by the preliminary DDR5 standard. The first production DDR5 DRAM chip was officially launched by SK Hynix on October 6, 2020.
The separate JEDEC standard Low Power Double Data Rate 5 (LPDDR5), intended for laptops and smartphones, was released in February 2019.
Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules incorporate on-board voltage regulators in order to reach higher speeds.[failed verification]
In 2024 the first CUDIMM (clocked unbuffered DIMM) and CSODIMM (clocked SODIMM) modules were introduced together with Intel Arrow Lake. These modules include a component to re-drive the clock signal to help reach higher speeds. AMD does not support CUDIMM, though Zen 5 will accept CUDIMMs in bypass mode.
Unlike DDR4, all DDR5 chips have on-die error-correction code, that detects and corrects errors before sending data to the CPU, to improve reliability and allow denser RAM chips with higher per-chip defect rate to be used.
However, on-die error-correction code is not the same as true ECC memory with extra chips for correction data on the memory module. Non-ECC and ECC DDR5 DIMM variants still exist; as with earlier RAM, ECC variants have extra data chips and data lines to the CPU for the additional error-detection data (8 more bits per 64 bits).