I3C (bus)

I3C, also known as SenseWire, is a specification to enable communication between computer chips by defining the electrical connection between the chips and signaling patterns to be used. Short for Improved Inter-Integrated Circuit, the standard defines the electrical connection between the chips to be a two wire, shared (multidrop), serial data bus, one wire (SCL) being used as a clock to define the sampling times, the other wire (SDA) being used as a data line whose voltage can be sampled. The standard defines a signaling protocol in which multiple chips can control communication and thereby act as the bus controller.

The I3C specification takes its name from, uses the same electrical connections as, and allows some backward compatibility with, the I²C bus, a de facto standard for inter-chip communication, widely used for low-speed peripherals and sensors in electronic devices. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus but still have the bus able to switch to a higher data rate for communication at higher speeds between compliant I3C devices. The I3C standard thereby combines the advantage of the simple, two wire I²C architecture with the higher communication speeds common to higher pin count buses such as the Serial Peripheral Interface (SPI).

The I3C standard was developed as a collaborative effort between electronics and computer-related companies under the auspices of the MIPI Alliance. The I3C standard was first released to the public at the end of 2017, although access requires the disclosure of private information. Google and Intel have backed I3C as a sensor interface standard for Internet of things (IoT) devices.

Goals of the MIPI Sensor Working Group effort were first announced in November 2014 at the MEMS Executive Congress in Scottsdale, Arizona, United States.

Electronic design automation tool vendors including Cadence, Synopsys and Silvaco have released controller IP blocks and associated verification software for the implementation of the I3C bus in new integrated circuit designs.

In December 2016, Lattice Semiconductor integrated I3C support into its new FPGA known as an iCE40 UltraPlus.

In 2017, Qualcomm announced the Snapdragon 845 mobile SOC with integrated I3C controller support.^{[failed verification]}

In December 2017, the I3C 1.0 specification was released for public review. At about the same time, a Linux kernel patch introducing support for I3C was proposed by Boris Brezillon.