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IBM Power microprocessors
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IBM Power microprocessors
Power microprocessors (originally POWER prior to Power10) are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power line of microprocessors has been used in IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.
The Power family was originally developed in the late 1980s, and remains under active development. In the beginning, they implemented the POWER instruction set architecture (ISA), which evolved into PowerPC and later into Power ISA. In August 2019, IBM announced it would open source the Power ISA. As part of the move, it was also announced that administration of the OpenPOWER Foundation is handled by the Linux Foundation.
In 1974, IBM started a project to build a telephone switching computer that required immense computational power. Since the application was comparably simple, this machine would need only to perform I/O, branches, add register-register, move data between registers and memory, and would have no need for special instructions to perform heavy arithmetic. This simple design philosophy, whereby each step of a complex operation is specified explicitly by one machine instruction, and all instructions are required to complete in the same constant time, was later called RISC. When the telephone switch project was canceled, IBM retained the design for the general purpose processor and named it 801 after building #801 at Thomas J. Watson Research Center.
By 1982, IBM continued to explore the superscalar limits of the 801 design by using multiple execution units to improve performance to determine if a RISC machine could maintain multiple instructions per cycle. Many changes were made to the 801 design to allow for multiple execution units and the Cheetah processor has separate units for branch prediction, fixed-point, and floating-point execution. By 1984, CMOS was chosen because it allows improved circuit integration and transistor-logic performance.
In 1985, research on a second-generation RISC architecture started at the IBM Thomas J. Watson Research Center, producing the "AMERICA architecture". In 1986, IBM Austin started developing the RS/6000 series computers based on that architecture. This was to become the first POWER processors using the first POWER ISA.
The first IBM computers to incorporate the POWER ISA are the RISC System/6000 or RS/6000 series. They were released in February 1990. These RS/6000 computers were divided into two classes, POWERstation workstations and POWERserver servers. The first RS/6000 CPU has 2 configurations, called the "RIOS-1" and "RIOS.9" (or more commonly the POWER1 CPU). A RIOS-1 configuration has a total of 10 discrete chips: an instruction cache chip, fixed-point chip, floating-point chip, 4 data L1 cache chips, storage control chip, input/output chips, and a clock chip. The lower cost RIOS.9 configuration has 8 discrete chips: an instruction cache chip, fixed-point chip, floating-point chip, 2 data cache chips, storage control chip, input/output chip, and a clock chip.
The POWER1 is the first microprocessor to have used register renaming and out-of-order execution. A simplified and less powerful version of the 10 chip RIOS-1 was made in 1992, for lower-end RS/6000s. It uses only one chip and is called RISC Single Chip or RSC.
IBM started the POWER2 processor effort as a successor to the POWER1. By adding a second fixed-point unit, a second powerful floating point unit, and other performance enhancements and new instructions to the design, the POWER2 ISA had leadership performance when it was announced in November 1993. The POWER2 was a multi-chip design, but IBM also made a single chip design of it, called the POWER2 Super Chip or P2SC that went into high performance servers and supercomputers. At the time of its introduction in 1996, the P2SC was the largest processor with the highest transistor count in the industry and was a leader in floating point operations.
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IBM Power microprocessors
Power microprocessors (originally POWER prior to Power10) are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power line of microprocessors has been used in IBM's RS/6000, AS/400, pSeries, iSeries, System p, System i, and Power Systems lines of servers and supercomputers. They have also been used in data storage devices and workstations by IBM and by other server manufacturers like Bull and Hitachi.
The Power family was originally developed in the late 1980s, and remains under active development. In the beginning, they implemented the POWER instruction set architecture (ISA), which evolved into PowerPC and later into Power ISA. In August 2019, IBM announced it would open source the Power ISA. As part of the move, it was also announced that administration of the OpenPOWER Foundation is handled by the Linux Foundation.
In 1974, IBM started a project to build a telephone switching computer that required immense computational power. Since the application was comparably simple, this machine would need only to perform I/O, branches, add register-register, move data between registers and memory, and would have no need for special instructions to perform heavy arithmetic. This simple design philosophy, whereby each step of a complex operation is specified explicitly by one machine instruction, and all instructions are required to complete in the same constant time, was later called RISC. When the telephone switch project was canceled, IBM retained the design for the general purpose processor and named it 801 after building #801 at Thomas J. Watson Research Center.
By 1982, IBM continued to explore the superscalar limits of the 801 design by using multiple execution units to improve performance to determine if a RISC machine could maintain multiple instructions per cycle. Many changes were made to the 801 design to allow for multiple execution units and the Cheetah processor has separate units for branch prediction, fixed-point, and floating-point execution. By 1984, CMOS was chosen because it allows improved circuit integration and transistor-logic performance.
In 1985, research on a second-generation RISC architecture started at the IBM Thomas J. Watson Research Center, producing the "AMERICA architecture". In 1986, IBM Austin started developing the RS/6000 series computers based on that architecture. This was to become the first POWER processors using the first POWER ISA.
The first IBM computers to incorporate the POWER ISA are the RISC System/6000 or RS/6000 series. They were released in February 1990. These RS/6000 computers were divided into two classes, POWERstation workstations and POWERserver servers. The first RS/6000 CPU has 2 configurations, called the "RIOS-1" and "RIOS.9" (or more commonly the POWER1 CPU). A RIOS-1 configuration has a total of 10 discrete chips: an instruction cache chip, fixed-point chip, floating-point chip, 4 data L1 cache chips, storage control chip, input/output chips, and a clock chip. The lower cost RIOS.9 configuration has 8 discrete chips: an instruction cache chip, fixed-point chip, floating-point chip, 2 data cache chips, storage control chip, input/output chip, and a clock chip.
The POWER1 is the first microprocessor to have used register renaming and out-of-order execution. A simplified and less powerful version of the 10 chip RIOS-1 was made in 1992, for lower-end RS/6000s. It uses only one chip and is called RISC Single Chip or RSC.
IBM started the POWER2 processor effort as a successor to the POWER1. By adding a second fixed-point unit, a second powerful floating point unit, and other performance enhancements and new instructions to the design, the POWER2 ISA had leadership performance when it was announced in November 1993. The POWER2 was a multi-chip design, but IBM also made a single chip design of it, called the POWER2 Super Chip or P2SC that went into high performance servers and supercomputers. At the time of its introduction in 1996, the P2SC was the largest processor with the highest transistor count in the industry and was a leader in floating point operations.