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List of Intel Itanium processors AI simulator
(@List of Intel Itanium processors_simulator)
Hub AI
List of Intel Itanium processors AI simulator
(@List of Intel Itanium processors_simulator)
List of Intel Itanium processors
The Itanium from Intel is a high-end server and supercomputer microprocessor.
Steppings: C0, C1 and C2. CPUID: 0007000604h (stepping C0), 0007000704h (stepping C1) or 0007000804h (stepping C2). Transistor count: 25.4 million for CPU, 295 million for the external L3 cache. The FSB data bus is 64 bits wide, not 128 like in Itanium 2.
Itanium 2 uses socket PAC611 with a 128 bit wide FSB. The 90 nm CPUs (9000 and 9100 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache). All Itaniums except some 130 nm models are capable of >2-socket SMP.
Stepping: B3. Die size: 421 mm2. Transistor count: 221 million. CPUID: 001F000704h
Stepping: B1. Die size: 374 mm2. Transistor count: 410 million. CPUID: 001F010504h.
The Madison 9M table contains the 4MB and 6MB successors of the first Madisons.
The same chip as Madison, but at a lower voltage.
Steppings: A1 and A2. Die size: 432 mm2. Transistor count: 592 million. CPUID: 001F020104h (stepping A1) or 001F020204h (stepping A2).
9M is the chip of all the third generation Itanium 2s, irrespective of the amount of enabled cache.
The same chip as Madison 9M, but restricted to 2-socket and uniprocessor systems.
List of Intel Itanium processors
The Itanium from Intel is a high-end server and supercomputer microprocessor.
Steppings: C0, C1 and C2. CPUID: 0007000604h (stepping C0), 0007000704h (stepping C1) or 0007000804h (stepping C2). Transistor count: 25.4 million for CPU, 295 million for the external L3 cache. The FSB data bus is 64 bits wide, not 128 like in Itanium 2.
Itanium 2 uses socket PAC611 with a 128 bit wide FSB. The 90 nm CPUs (9000 and 9100 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache). All Itaniums except some 130 nm models are capable of >2-socket SMP.
Stepping: B3. Die size: 421 mm2. Transistor count: 221 million. CPUID: 001F000704h
Stepping: B1. Die size: 374 mm2. Transistor count: 410 million. CPUID: 001F010504h.
The Madison 9M table contains the 4MB and 6MB successors of the first Madisons.
The same chip as Madison, but at a lower voltage.
Steppings: A1 and A2. Die size: 432 mm2. Transistor count: 592 million. CPUID: 001F020104h (stepping A1) or 001F020204h (stepping A2).
9M is the chip of all the third generation Itanium 2s, irrespective of the amount of enabled cache.
The same chip as Madison 9M, but restricted to 2-socket and uniprocessor systems.