Community hub
Recent from talks
Knowledge base stats:
Talk channels stats:
Members stats:
MCP-1600
The MCP-1600 is a multi-chip 16-bit microprocessor introduced by Western Digital in 1975 and produced through the early 1980s. Used in the Pascal MicroEngine, the WD16 processor in the Alpha Microsystems AM-100, and the DEC LSI-11 microcomputer, a cost-reduced and compact implementation of the DEC PDP-11.
There are three types of chips in the chip-set:
The chips use a 3.3MHz four phase clock and three power supply voltages (+5V, +12V, and -5V), as required by the N-channel silicon gate process then available at Western Digital. Internally the MCP-1600 is a (relatively fast) 8-bit processor that can be micro-programmed to emulate a 16-bit CPU. All byte operations execute in one clock period; word operations and branches take two clocks. Up to four MICROMs are supported, but usually two or three could hold the needed microprogram for a processor.
The register file consists of 26 8-bit registers. Ten may be addressed directly by the microinstruction (Rx), four may be addressed either directly or indirectly (Rx/Gx), and the remaining 12 may be addressed only indirectly (Gx). Indirect addressing is via a 3-bit G register which is usually loaded with the register field of the PDP-11 instruction.
The most significant feature of the MCP-1600 is its Programmable Translation Array (PTA). The PTA serves to generate new microinstruction fetch addresses as a function of several parameters. These parameters are those which are normally considered during the decode of a macroinstruction. The PTA was designed specifically to eliminate most of the overhead of macroinstruction translation. Essentially a macroinstruction opcode is quickly translated into an address that is loaded onto the Location Counter, creating a jump to the appropriate microcode to handle the macroinstruction.
John Wallace was the Project Manager and designed the 1621, Mike Briner designed the 1611, and later became a Senior VP at Silicon Storage Technology. Bill Pohlman was the design engineering manager and he later was Project Manager for the Intel 8086 processor.
Microcode could be developed using a DEC LSI-11 computer with the KUV11-AA Writable Control Store (WCS) option. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set. The WCS is a quad Q-Bus board with a ribbon cable connecting to an open MCP-1600 microcode ROM socket.
In January 1976, the three-chip minimum MCP-1600 configuration was offered at $159 ($880 in 2024) in 100-999 quantities. In March 1976, it was announced that National Semiconductor would second-source the MCP-1600. It is unclear whether any were produced by National.
Hub AI
MCP-1600 AI simulator
(@MCP-1600_simulator)
MCP-1600
The MCP-1600 is a multi-chip 16-bit microprocessor introduced by Western Digital in 1975 and produced through the early 1980s. Used in the Pascal MicroEngine, the WD16 processor in the Alpha Microsystems AM-100, and the DEC LSI-11 microcomputer, a cost-reduced and compact implementation of the DEC PDP-11.
There are three types of chips in the chip-set:
The chips use a 3.3MHz four phase clock and three power supply voltages (+5V, +12V, and -5V), as required by the N-channel silicon gate process then available at Western Digital. Internally the MCP-1600 is a (relatively fast) 8-bit processor that can be micro-programmed to emulate a 16-bit CPU. All byte operations execute in one clock period; word operations and branches take two clocks. Up to four MICROMs are supported, but usually two or three could hold the needed microprogram for a processor.
The register file consists of 26 8-bit registers. Ten may be addressed directly by the microinstruction (Rx), four may be addressed either directly or indirectly (Rx/Gx), and the remaining 12 may be addressed only indirectly (Gx). Indirect addressing is via a 3-bit G register which is usually loaded with the register field of the PDP-11 instruction.
The most significant feature of the MCP-1600 is its Programmable Translation Array (PTA). The PTA serves to generate new microinstruction fetch addresses as a function of several parameters. These parameters are those which are normally considered during the decode of a macroinstruction. The PTA was designed specifically to eliminate most of the overhead of macroinstruction translation. Essentially a macroinstruction opcode is quickly translated into an address that is loaded onto the Location Counter, creating a jump to the appropriate microcode to handle the macroinstruction.
John Wallace was the Project Manager and designed the 1621, Mike Briner designed the 1611, and later became a Senior VP at Silicon Storage Technology. Bill Pohlman was the design engineering manager and he later was Project Manager for the Intel 8086 processor.
Microcode could be developed using a DEC LSI-11 computer with the KUV11-AA Writable Control Store (WCS) option. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set. The WCS is a quad Q-Bus board with a ribbon cable connecting to an open MCP-1600 microcode ROM socket.
In January 1976, the three-chip minimum MCP-1600 configuration was offered at $159 ($880 in 2024) in 100-999 quantities. In March 1976, it was announced that National Semiconductor would second-source the MCP-1600. It is unclear whether any were produced by National.