Motorola 68020

The Motorola 68020 is a 32-bit microprocessor from Motorola, released in 1984. A lower-cost version was also made available, known as the 68EC020. In keeping with naming practices common to Motorola designs, the 68020 is usually referred to as the "020", pronounced "oh-two-oh" or "oh-twenty".

The 020 was in the market for a relatively short time. The Motorola 68030 was announced in September 1986 and began deliveries in the summer of 1987. Priced about the same as the 020 of the time, the 030 was significantly faster and quickly replaced in 020 in almost every use.

At the time the Motorola 68000 was designed, Motorola's design and fabrication services were outdated. Although even small companies like MOS Technology and Zilog had moved on to silicon gate depletion mode NMOS logic on ever-larger wafers, Motorola was still using metal gates and enhancement mode and their largest fab worked on 4-inch wafers long after most lines had moved to 5-inch. Although the 68000 met the goal of being the fastest CPU available when it was introduced, it was not nearly as powerful as it could be if it had been designed with more modern techniques.

During the period of the 68000 design, the company was working with Hitachi on their process technology and as part of this they opened a new fab, MOS-8, using 5-inch wafers and the latest HMOS process licensed from Intel. This line was capable of building all of the new techniques, but the 68000 went ahead with the older design as they were sure it would work. Moving to new design techniques would wait until the design was in the market. The conversion to the new design techniques took place during the Motorola 68010 effort, a relatively minor upgrade to the original design that added basic virtual memory support for the emerging Unix workstation market.

As this effort was ongoing, Motorola was canvassing their customers for their desires for future developments in the line. These all pointed to a fully 32-bit implementation. Those using the 68k in Unix systems also stated they would purchase a floating-point unit for every one of the machines if one was available.

The original 68000 had been designed as a hybrid 16/32-bit system largely because the maximum number of pins available on dual inline packages (DIPs) was 64, and even at that size, packaging of this size was highly problematic. By reducing the number of address pins to 24, and the data pins to only 16, there were enough free pins to implement all the other needed lines, like interrupts and power supplies. The 24-pin address bus meant that the memory could only be 16 MB in total, which was at this point becoming a limitation. The 16-bit data bus meant reading a 32-bit word from that memory required two bus cycles.

A design that had 32 pins for both the address and data busses would access data twice as fast, making the machine that much faster even with no other changes. Moving to 32-bit addressing would also make the implementation of virtual memory easier, and allow for more than 16 MB of random access memory. But doing so would also demand a much higher total pin count. By the early 1980s, similar limitations on all modern CPU designs led to the introduction of the pin grid array that replaced the DIP. For the new project, Motorola selected a 169-pin layout, giving them plenty of room to work with. The design ultimately used only 114 of them.

A great debate broke out about how to refer to the underlying design of the new chip in marketing materials. Technically, the 020 was moving from the long-established NMOS logic design to a CMOS layout, which requires two transistors per gate. Common knowledge of the era suggested that CMOS cost four times as much as NMOS, and there was a significant amount of the market that believed "CMOS equals bad."