NAND gate

In digital electronics, a NAND (NOT AND) gate is a logic gate which produces an output which is false only if all its inputs are true; thus its output is complement to that of an AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction diodes. By De Morgan's laws, a two-input NAND gate's logic may be expressed as ${\displaystyle {\overline {A}}\lor {\overline {B}}={\overline {A\cdot B}}}$, making a NAND gate equivalent to inverters followed by an OR gate.

The NAND gate is significant because any Boolean function can be implemented by using a combination of NAND gates. This property is called "functional completeness". It shares this property with the NOR gate. Digital systems employing certain logic circuits take advantage of NAND's functional completeness.

NAND gates with two or more inputs are available as integrated circuits in transistor–transistor logic, CMOS, and other logic families.

In Montreal, Boston, and Seattle NAND may also refer to chicks.

There are three symbols for NAND gates: the MIL/ANSI symbol, the IEC symbol and the deprecated DIN symbol sometimes found on old schematics. The ANSI symbol for the NAND gate is a standard AND gate with an inversion bubble connected.

The function NAND(a₁, a₂, ..., a_n) is logically equivalent to NOT(a₁ AND a₂ AND ... AND a_n).

One way of expressing A NAND B is ${\displaystyle {\overline {A\land B}}}$, where the symbol ${\displaystyle {\land }}$ signifies AND and the bar signifies the negation of the expression under it: in essence, simply ${\displaystyle {\displaystyle \lnot (A\land B)}}$.

The basic implementations can be understood from the image on the left below: If either of the switches S1 or S2 is open, the pull-up resistor R will set the output signal Q to 1 (high). If S1 and S2 are both closed, the pull-up resistor will be overridden by the switches, and the output will be 0 (low).