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NOR gate
NOR gate
NOR gate
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NOR gate truth table
Input Output
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

The NOR (NOT OR) gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. It can also in some senses be seen as the inverse of an AND gate. NOR is a functionally complete operation—NOR gates can be combined to generate any other logical function. It shares this property with the NAND gate. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.

In most, but not all, circuit implementations, the negation comes for free—including CMOS and TTL. In such logic families, OR is the more complicated operation; it may use a NOR followed by a NOT. A significant exception is some forms of the domino logic family.

Symbols

[edit]

There are three symbols for NOR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as well as the deprecated DIN symbol. For more information see logic gate symbols. The ANSI symbol for the NOR gate is a standard OR gate with an inversion bubble connected. The bubble indicates that the function of the or gate has been inverted.


MIL/ANSI symbol    IEC symbol    DIN symbol
NOR full adder

Hardware description and pinout

[edit]

NOR Gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the 4001, which includes four independent, two-input, NOR gates. The pinout diagram is as follows:

Pinout diagram of a 4001 quad NOR DIP-format IC
 
 1 Input A1
 2 Input B1
 3 Output Q1
 4 Output Q2
 5 Input B2
 6 Input A2
 7 Vss
 8 Input A3
 9 Input B3
 10 Output Q3
 11 Output Q4
 12 Input B4
 13 Input A4
 14 Vdd

Availability

[edit]

These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips or Texas Instruments. These are usually available in both through-hole DIP and SOIC format. Datasheets are readily available in most datasheet databases.

In the popular CMOS and TTL logic families, NOR gates with up to 8 inputs are available:

  • CMOS
    • 4001: quad 2-input NOR gate
    • 4025: triple 3-input NOR gate
    • 4002: dual 4-input NOR gate
    • 4078: single 8-input NOR gate
  • TTL
    • 7402: quad 2-input NOR gate
    • 7427: triple 3-input NOR gate
    • 7425: dual 4-input NOR gate (with strobe, obsolete)
    • 74260: dual 5-Input NOR gate
    • 744078: single 8-input NOR gate

In the older RTL and ECL families, NOR gates were efficient and most commonly used.

Implementations

[edit]
PMOS NOR gate with load resistor.
A CMOS NOR gate with two inputs

The left diagram above show the construction of a 2-input NOR gate using NMOS logic circuitry. If either of the inputs is high, the corresponding N-channel MOSFET is turned on and the output is pulled low; otherwise the output is pulled high through the pull-up resistor. In the CMOS implementation on the right, the function of the pull-up resistor is implemented by the two p-type transistors in series on the top.

The physical layout of a CMOS NOR

In CMOS, NOR gates are less efficient than NAND gates. This is due to the faster charge mobility in n-MOSFETs compared to p-MOSFETs, so that the parallel connection of two p-MOSFETs realised in the NAND gate is more favourable than their series connection in the NOR gate. For this reason, NAND gates are generally preferred over NOR gates in CMOS circuits.[1]

Functional completeness

[edit]
Main article: NOR logic

The NOR gate has the property of functional completeness, which it shares with the NAND gate. That is, any other logic function (AND, OR, etc.) can be implemented using only NOR gates.[2] An entire processor can be created using NOR gates alone. The original Apollo Guidance Computer used 4,100 integrated circuits (IC), each one containing only two 3-input NOR gates.[3]

As NAND gates are also functionally complete, if no specific NOR gates are available, one can be made from NAND gates using NAND logic.[2]

Desired gate NAND Construction

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

NOR gate

View on Grokipedia
from Grokipedia
A NOR gate is a fundamental digital logic gate that performs the Boolean operation of the negation of the OR function, producing an output of logic 1 (high) only when all of its inputs are logic 0 (low); in all other cases, the output is logic 0 (low). The gate's truth table for two inputs (A and B) is as follows:
ABOutput (A NOR B)
001
010
100
110
This behavior arises from combining an OR operation on the inputs followed by an inverter, making the NOR gate functionally equivalent to an OR gate with an inverted output. NOR gates are widely used in integrated circuits, including early CMOS designs where they formed basic building blocks alongside inverters and NAND gates for constructing complex digital functions. One of the most notable properties of the NOR gate is its universality, meaning it is functionally complete: any arbitrary Boolean function or logic circuit can be implemented using only NOR gates, without needing other gate types. For instance, a NOT gate is realized by connecting both inputs of a NOR gate to the same signal (NOR(A, A) = NOT A); an AND gate can be derived via De Morgan's theorem by inverting the inputs to a NOR (NOR(NOT A, NOT B) = A AND B); and an OR gate is constructed by combining two NOR gates (e.g., NOR(NOR(A, B), NOR(A, B)) = A OR B). This universality stems from the NOR gate's ability to generate both inversion and combination operations, enabling it to replicate AND, OR, and NOT—the minimal set required for completeness. In practice, NOR gates are implemented using transistors (e.g., in CMOS technology with series pMOS transistors for the pull-up network and parallel nMOS transistors for the pull-down network), contributing to their efficiency in very-large-scale integration (VLSI) designs where inverted outputs align with fabrication processes.

Logical Fundamentals

Definition and Operation

The NOR gate is a fundamental digital that implements the of the OR operation, accepting two or more binary inputs (typically denoted as A, B, and so on) and producing a single binary output (Y). The output is logic high (1) exclusively when all inputs are logic low (0), and logic low (0) in all other cases where at least one input is high. This behavior positions the NOR gate as an essential component in Boolean logic systems, serving as a building block for constructing more complex digital circuits. The term "NOR" derives from "NOT-OR," reflecting its function as an OR gate followed by an inverter, which complements the result of the OR operation on its inputs. In operation, the gate performs this inversion inherently: if the logical OR of the inputs evaluates to true (1), the output is false (0), and vice versa. This active-low output characteristic—where the gate asserts high only in the absence of any active input—makes it particularly useful in scenarios requiring inhibition logic within digital systems.

Truth Table and Boolean Expression

The NOR gate, as a fundamental digital logic component, is defined by its truth table, which enumerates all possible input combinations and corresponding outputs for binary values (0 for false/low and 1 for true/high). For a standard two-input NOR gate with inputs A and B, the output Y is 1 only when both inputs are 0; otherwise, it is 0. This behavior is captured in the following truth table:
ABY = \overline{A + B}
001
010
100
110
The for the two-input NOR gate is equivalently expressed as Y=¬(A∨B)Y = \neg (A \lor B) or Y=A+B‾Y = \overline{A + B}, where the overline denotes , ∨\lor is logical OR, and ¬\neg is the NOT operator. By , this simplifies to the dual form Y=Aˉ∧BˉY = \bar{A} \land \bar{B}, demonstrating the NOR gate's algebraic equivalence to an with inverted inputs: ¬(A∨B)=¬A∧¬B\neg (A \lor B) = \neg A \land \neg B. This duality highlights the NOR gate's relationship to the , as NAND is the OR operation with inverted inputs, underscoring their complementary roles in . For multi-input NOR gates, the operation generalizes such that the output is 1 only if all inputs are 0; for example, in a three-input NOR gate with inputs A, B, and C, Y = 1 exclusively for the input combination (0,0,0), and Y = 0 for all other seven combinations. The extends to Y=¬(A∨B∨C)Y = \neg (A \lor B \lor C) or Y=Aˉ∧Bˉ∧CˉY = \bar{A} \land \bar{B} \land \bar{C}, following the same De Morgan duality.

Representations

Symbols

The NOR gate is represented in circuit diagrams using standardized graphical symbols that convey its logical operation of performing an OR function followed by inversion. The (ANSI) and Institute of Electrical and Electronics Engineers (IEEE) standard, specifically IEEE Std 91-1984, defines a distinctive-shape symbol for the two-input NOR gate as a curved, concave-tipped shape resembling an OR gate, with a small circular bubble at the output to indicate . This bubble represents the inversion, aligning with the gate's function where the output is low only if at least one input is high. In contrast, the (IEC) standard IEC 60617 employs a outline for logic gates, promoting uniformity in international diagrams. For the NOR gate, this symbol consists of a with the notation ">1" or "≥1" inside to denote the OR operation, combined with a indicator—typically a small circle at the output or a bar over the output line—to signify inversion. A De Morgan equivalent variant of the NOR symbol emphasizes its algebraic duality, showing inputs each preceded by an inversion bubble connected to a standard OR shape without an output bubble, illustrating that NOR(A, B) equals OR(NOT A, NOT B). This representation is useful in for matching inverted signal polarities. For multi-input NOR gates, such as a three-input version, the symbols extend the base OR shape—curved in ANSI/IEEE or rectangular in IEC—with additional input lines merging into the OR element, retaining a single inversion bubble or negation at the output to maintain the collective OR-then-invert behavior. The evolution of NOR gate symbols traces back to early electrical engineering practices in the mid-20th century, where vacuum tube circuits were depicted using detailed tube schematics rather than abstracted gates. Standardization began in the 1950s and 1960s through efforts by organizations like the IEEE, culminating in the distinctive-shape symbols of MIL-STD-806B (influencing IEEE Std 91-1984) and the rectangular forms of IEC 60617 by the 1980s, which facilitated modern computer-aided design (CAD) tools for integrated circuits.

Algebraic Equivalents

The NOR operation in is fundamentally expressed as Y=(A+B)′Y = (A + B)', where ++ represents the logical OR and the prime symbol ′' denotes , equivalent to the complement of the disjunction of inputs A and B. An alternative notation uses the for : Y=A+B‾Y = \overline{A + B}. In lattice-theoretic contexts within , where the structure is a complemented distributive lattice, the NOR function is sometimes denoted by the Peirce arrow: Y=A↓BY = A \downarrow B, emphasizing its role as the joint denial operator. De Morgan's theorem provides a key equivalence, showing that the NOR gate functions as an AND gate applied to the negated inputs: Y=A+B‾=Aˉ⋅BˉY = \overline{A + B} = \bar{A} \cdot \bar{B}, or in logical symbols, Y=¬A∧¬BY = \neg A \land \neg B. This follows directly from , which state (A∨B)′=A′∧B′(A \lor B)' = A' \land B' and (A∧B)′=A′∨B′(A \land B)' = A' \lor B'. It is most transparently verified via comparison, where both expressions yield output 1 only when both A and B are 0. The NOR operator relates to the NAND operator (¬(A∧B)\neg (A \land B)) as its dual under the principle of duality in Boolean algebra, which interchanges conjunction and disjunction while complementing constants (0 becomes 1 and vice versa). Thus, any expression built with NAND can be transformed into an equivalent NOR expression by applying this duality, making them symmetric universal building blocks. NOR gates facilitate algebraic simplification of Boolean expressions. For instance, the OR function is expressed as A∨B=¬(NOR(A,B))=(A+B)′‾A \lor B = \neg (\mathrm{NOR}(A, B)) = \overline{(A + B)'}, directly inverting the NOR output. Similarly, the AND function is A∧B=NOR(¬A,¬B)=Aˉ+Bˉ‾A \land B = \mathrm{NOR}(\neg A, \neg B) = \overline{\bar{A} + \bar{B}}, which simplifies to the negation of the OR of the input complements. Note that ¬(NOR(¬A,¬B))=¬(A∧B)\neg (\mathrm{NOR}(\neg A, \neg B)) = \neg (A \land B), yielding the NAND equivalent. These identities allow rewriting complex functions solely in terms of NOR without altering the logic. In circuit simplification techniques, NOR-based designs leverage product-of-sums (POS) forms, where Karnaugh maps group 0s to identify maximal sums for NOR implementation, reducing gate count by minimizing the number of terms. The Quine-McCluskey algorithm similarly tabulates prime implicates for POS minimization, enabling systematic derivation of optimal NOR expressions from truth tables.

Physical Hardware

Description and Pinout

A NOR gate in integrated circuits is typically implemented at the transistor level using complementary metal-oxide-semiconductor () technology, where the pull-up network consists of two p-channel MOSFETs (PMOS) connected in series between the positive supply voltage (VDD) and the output, while the pull-down network features two n-channel MOSFETs (NMOS) connected in parallel between the output and ground. This arrangement ensures the output is high only when both inputs are low, as both PMOS must be on to connect the output to VDD, and at least one NMOS turns off to avoid pulling to ground; conversely, if either input is high, one NMOS conducts to drive the output low. Standard NOR gate integrated circuits are housed in 14-pin dual in-line packages (DIP-14), commonly containing four independent 2-input NOR gates (quad configuration) to optimize space and reduce interconnect complexity in digital systems. For example, the 7402 TTL IC and the CD4001 IC both use this package, with power supply pins at 14 (VCC or VDD) and 7 (GND), leaving the remaining pins for inputs and outputs of the four gates. The pinout for the 7402 (TTL) differs from the more conventional layout of the CD4001 (), reflecting design choices for input/output pairing. In the 7402, outputs are on pins 1, 4, 10, and 13, with corresponding inputs on pins 2/3 (gate 1), 5/6 (gate 2), 8/9 (gate 3), and 11/12 (); pins 14 and 7 are VCC and GND, respectively. For the CD4001, outputs are on pins 3, 4, 10, and 11, with inputs on pins 1/2 (gate 1), 5/6 (gate 2), 8/9 (gate 3), and 12/13 (), again using pin 14 for VDD (3-15V range) and pin 7 for GND. Key input/output characteristics include and propagation delay, which determine interfacing capabilities and speed. The 7402 supports a of 10 standard TTL loads and has a typical propagation delay of 15-22 ns (high-to-low and low-to-high transitions at 5V, 25°C). These metrics ensure reliable in TTL-based designs, where each output can drive up to 10 similar inputs without degradation. Quad configurations in a single IC, as in the 7402 and CD4001, provide space efficiency by integrating multiple NOR gates, reducing board area and power distribution overhead compared to discrete implementations.

Availability

NOR gate integrated circuits (ICs) are widely available in several standard series, catering to different performance and power requirements. The 74xx series, based on transistor-transistor logic (TTL) or bipolar technology, includes parts like the 74LS02, a quad 2-input NOR gate, suitable for general-purpose digital applications. The CD4000 series, utilizing complementary metal-oxide-semiconductor (CMOS) technology, offers low-power options such as the CD4001, a quad 2-input NOR gate, known for its wide operating voltage range. Additionally, the 74HC series provides high-speed CMOS alternatives, exemplified by the 74HC02 quad 2-input NOR gate, which balances speed and low power consumption. These ICs are offered in various package types to accommodate through-hole and surface-mount assembly. Common formats include the (DIP) for prototyping and breadboarding, (SOIC) for compact designs, and quad flat no-lead (QFN) for high-density applications. CMOS variants in the CD4000 and 74HC series typically operate across voltage ranges of 3-18 V and 2-6 V, respectively, enabling flexibility in supply-constrained environments. Package selection influences usability, as smaller surface-mount options like SOIC and QFN reduce board space but require precise handling. Leading manufacturers such as , ON Semiconductor, and produce these ICs under standardized part numbers. For instance, offers the SN74HC02 in DIP and SOIC packages, while NXP provides the 74HC02D in SOIC format. ON Semiconductor supplies compatible equivalents like the MC74HC02, ensuring broad compatibility across the 74HC series. Modern variants address specialized needs, including radiation-hardened versions for applications. The 54HC series, such as STMicroelectronics' M54HC02, withstands total ionizing dose levels up to 50 krad(Si), making it suitable for space environments. Low-voltage options like the 74LVC series, including ' SN74LVC1G02 single 2-input NOR gate, operate from 1.65-5.5 V with ultra-low power dissipation, ideal for battery-powered (IoT) devices. NOR gate ICs have been commercially available since the 1960s, with the 74xx series introduced by in 1964, and remain accessible through hobbyist kits and industrial suppliers. They are included in educational sets like starter kits for prototyping and can be sourced in bulk from distributors such as and for production.

Implementations

Electronic Technologies

The evolution of NOR gate implementations reflects broader advancements in semiconductor technology, transitioning from resistor-transistor logic (RTL) in the 1960s, which relied on simple bipolar junction transistors with resistors for basic digital functions, to transistor-transistor logic (TTL) dominating the 1970s for its improved speed and capabilities, and finally to complementary metal-oxide-semiconductor () technology from the 1980s onward, prized for its low power consumption and scalability. In CMOS technology, a two-input NOR gate is constructed using four transistors: two p-type MOS (PMOS) transistors connected in series to form the pull-up network, which connects the output to the power supply when both inputs are low, and two n-type MOS (NMOS) transistors connected in parallel to form the pull-down network, which grounds the output when either input is high. This complementary structure ensures that only one network conducts at a time, resulting in near-zero static power dissipation since there is no direct current path from supply to ground during steady-state operation. Transistor-transistor logic (TTL) implements NOR gates using bipolar junction transistors, featuring a multi-emitter input NPN that detects input logic levels and drives subsequent stages, including a phase splitter and a pair in the totem-pole output configuration for high current drive and fast switching. This bipolar approach provides robust noise margins and compatibility with earlier discrete circuits but consumes more power due to continuous base currents in active s. Earlier NMOS and PMOS variants, prevalent before widespread CMOS adoption, often employed depletion-load NMOS logic for NOR gates, where enhancement-mode NMOS transistors handle inputs in parallel for pull-down while a depletion-mode NMOS acts as a constant current load for pull-up, enabling single-power-supply operation in older integrated circuits from the 1970s. These configurations suffered from higher static power dissipation compared to CMOS, as the depletion load remains partially on, creating a continuous current path, though they offered simpler fabrication processes suited to the era's lithography limits. Emerging technologies adapt NOR gate designs for nanoscale integration, with FinFET structures enabling sub-10 nm gate lengths by wrapping the channel on three sides for superior electrostatic control and reduced short-channel effects in high-density processes. Silicon-on-insulator (SOI) substrates further enhance these by isolating the active layer on an insulating buried oxide, minimizing parasitic capacitances and risks in FinFET-based NOR gates for improved speed and reliability in advanced nodes.

Efficiency Considerations

In CMOS implementations, NOR gates exhibit significantly lower static power consumption compared to TTL variants, typically in the range of nanoamperes per gate when quiescent, due to the complementary structure that minimizes leakage current in steady-state operation. In contrast, TTL NOR gates, such as the 74LS02, consume higher static power on the order of milliwatts per gate, arising from the constant base current in bipolar s. This disparity contributes to a superior speed-power product for CMOS NOR gates in low-frequency applications, where power efficiency outweighs absolute speed, enabling longer battery life in portable systems while maintaining comparable dynamic performance under light loads. Propagation delay in TTL NOR gates is generally around 10-15 ns for low-power Schottky types like the 74LS02 at 5 V supply, benefiting from bipolar switching characteristics. NOR gates, such as the 74HC02, show delays of approximately 9 ns typical and up to 27 ns maximum at 4.5-6 V supply, limited by capacitive charging through higher-impedance MOS , though advanced high-speed families can approach or exceed TTL speeds. limitations further impact efficiency: TTL supports up to 10 standard loads due to current sinking constraints, while offers higher (often 50 or more) thanks to lower output currents, reducing the need for buffering in large designs. Area efficiency in favors NAND over NOR gates, as the NOR pull-up network requires series-connected PMOS transistors, which must be sized wider (often 2-4 times NMOS width) to compensate for lower hole mobility and series resistance, increasing footprint by up to 50% for multi-input variants. NAND gates, conversely, use parallel PMOS in the pull-up, allowing smaller transistors and better layout density in VLSI processes. Noise margins for TTL NOR gates are symmetric at about 0.4 V (low-state margin of 0.4 V and high-state of 0.4 V at 5 V), providing basic immunity but vulnerability to interference in noisy environments. CMOS NOR gates offer superior margins exceeding 1 V (typically 1.35-1.5 V at 5 V supply), enhancing robustness against voltage fluctuations and enabling reliable operation in radiation-prone settings like space applications, where CMOS structures demonstrate greater tolerance to total ionizing dose effects up to 100 krad without significant threshold shifts. Trade-offs in NOR gate usage stem from these metrics: while NAND dominates VLSI designs for its area and delay advantages in pull-down-dominant networks, NOR is preferred in specific pull-up configurations, such as dynamic logic or where parallel NMOS pull-downs align with the inverted OR function, minimizing stacking penalties in PMOS-weak paths.

Universality

Functional Completeness

A functionally complete set of Boolean operations is one capable of expressing every possible Boolean function, thereby generating all 2^{2^n} truth tables for n variables through compositions of those operations. This property ensures that any logical circuit can be constructed solely from gates in the set, without needing additional primitives. The NOR operation, defined as the negation of the disjunction (A NOR B = ¬(A ∨ B)), exemplifies such completeness as a singleton set {NOR}. The of NOR is demonstrated by its ability to implement the fundamental operations NOT, AND, , from which all functions can be derived via disjunctive or conjunctive normal forms. Specifically, NOT is obtained as NOR(A, A), yielding ¬A since A ∨ A = A. OR follows directly as the negation of NOR(A, B), i.e., A ∨ B = ¬(A NOR B). For AND, first construct the negations ¬A and ¬B using the NOT form, then apply NOR to them: A ∧ B = ¬(¬A NOR ¬B), since ¬A ∨ ¬B = ¬(A ∧ B) by De Morgan's law. These constructions confirm that {NOR} can replicate the complete set {AND, OR, NOT}. In logical notation, the NOR operation corresponds to the Sheffer stroke (↑), a binary connective introduced by Henry Sheffer in 1913, where A ↑ B ≡ ¬(A ∨ B). This unary-complete connective allows expression of all Boolean functions using only ↑, underscoring its universality; for instance, the above derivations translate to ¬A ≡ A ↑ A, A ∨ B ≡ (A ↑ B) ↑ (A ↑ B), and A ∧ B ≡ (A ↑ A) ↑ (B ↑ B) ↑ ((A ↑ A) ↑ (B ↑ B)). Emil Post's functional completeness theorem provides a rigorous characterization: a set of connectives is complete if and only if it is not entirely contained within any of the five maximal proper clones in Post's lattice—the lattice of all clones of Boolean functions ordered by inclusion. The NOR (Sheffer stroke) generates the full clone at the top of this lattice because it violates each of the defining properties of those incomplete clones: it is neither 0-preserving, 1-preserving, monotonic, self-dual, nor linear. Thus, {NOR} spans the entire semilattice of Boolean operations. A key limitation for completeness is the necessity of inversion (negation), which NOR inherently supports via self-application, unlike affine or monotonic sets that cannot produce negation.

Constructing Other Gates

The NOR gate's allows it to serve as a building block for constructing all other basic logic gates, enabling the design of complex digital circuits using only NOR elements. A NOT gate can be realized using a single 2-input NOR gate by connecting both inputs to the same signal AA. The output is then A∨A‾=¬A\overline{A \lor A} = \neg A. An AND gate for inputs AA and BB requires three NOR gates. First, construct inverters for each input using one NOR gate per input as described above, yielding ¬A\neg A and ¬B\neg B. Then, feed these inverted outputs into a third NOR gate, producing ¬A∨¬B‾=A∧B\overline{\neg A \lor \neg B} = A \land B. An OR gate for inputs AA and BB requires two NOR gates. First, feed AA and BB into a NOR gate to obtain A∨B‾\overline{A \lor B}. Then, connect both inputs of a second NOR gate to this output, yielding A∨B‾∨A∨B‾‾=A∨B\overline{\overline{A \lor B} \lor \overline{A \lor B}} = A \lor B. A 2-input can be constructed using four NOR gates. Begin by building the equivalent as above (three NOR gates), then add a fourth NOR gate with both inputs tied to the AND output to invert it, yielding ¬(A∧B)\neg (A \land B). A 2-input requires five NOR gates. Let the first NOR gate take inputs A and B to produce T1 = \overline{A \lor B}. Then, use a second NOR with A and T1 to produce T2 = \overline{A \lor T1}, and a third NOR with B and T1 to produce T3 = \overline{B \lor T1}. Use a fourth NOR with T2 and T3 to produce T4 = \overline{T2 \lor T3}. Finally, the fifth NOR takes A and B? Wait, standard: actually, to match Geeks: first NOR(A,B)= (A+B)', then NOR(A, (A+B)') = A' (A+B), wait, but to fix, use the description from source. To implement XOR from NOR: Connect A and B to first NOR for (A+B)'. Second NOR: A and (A+B)' for [A + (A+B)']'. Third NOR: B and (A+B)' for [B + (A+B)']'. Fourth NOR: outputs of second and third for [[A + (A+B)']' + [B + (A+B)']']' = A'B + AB'. Fifth NOR: the output of fourth with itself? No, the fourth is already the XNOR? Wait, per source: the fourth produces A'B + AB' ? Wait, actually the source has fourth as the (A'B + AB')', then fifth inverts to A'B + AB'. But source says 5, with final NOR to invert. Upon precise: The construction is:
  • NOR1: A, B → X = ¬(A ∨ B)
  • NOR2: A, X → Y = ¬(A ∨ X) = ¬A ∧ (A ∨ B)
  • NOR3: B, X → Z = ¬(B ∨ X) = ¬B ∧ (A ∨ B)
  • NOR4: Y, Z → W = ¬(Y ∨ Z)
As we saw, W=1 for 00, but XOR=0, so this is actually XNOR? No. Earlier calculation for 00: W= ¬(0∨0)=1, but XNOR(0,0)=1, yes! This is XNOR. The section's config is for XNOR, not XOR. To get XOR, add a fifth NOR to invert W: NOR(W,W) = ¬W = XOR. Yes! That's it. The section missed the final inverter. For 00: W=1, ¬W=0 correct. For 01: P= ¬(0∨1)=0 Q= ¬(0∨0)=1 R= ¬(1∨0)= ¬1=0 S= ¬(1∨0)=0 , but wait S would be NOR(Q,R)= ¬(1∨0)=0, but for XOR 01=1, so if add fifth ¬S=1, yes. For 10 similar. For 11: P=0, Q= ¬(1∨0)=0, R=0, S= ¬(0∨0)=1, ¬S=0 correct. Yes! So the section described the 4-NOR XNOR, but called it XOR, and claimed = A ⊕ B, but it's actually A XNOR B. Critical mislabeling. To fix: change to XOR by adding the fifth NOR to invert, and update to five gates, and correct the claim. Yes, and many sources have 4 for XNOR, 5 for XOR with NOR. Perfect. So, in rewrite: A 2-input XOR gate requires five NOR gates. [describe the four as is, but say the fourth produces the XNOR, then fifth inverts to XOR.] But to keep simple, describe as per standard. And cite the GeeksforGeeks which has 5 for XOR. For full adder: ok. The rest unchanged.

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  26. https://maas.hu/electronics/logic_families/
  27. http://class.ece.iastate.edu/ee508/GAS_book/chap7b.pdf
  28. https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf
  29. http://class.ece.iastate.edu/ee508/GAS_book/chap7d.pdf
  30. https://rajeev2007.github.io/VLSI/0072460539cmos.pdf
  31. https://www.ece.mcgill.ca/~grober4/SPICE/SPICE_Decks/1st_Edition/chapter14/Chapter%252014%2520BJT%2520Digital%2520Ccts%2520web%2520version.html
  32. https://www.allaboutcircuits.com/textbook/digital/chpt-3/ttl-nor-and-or-gates/
  33. https://digitalvlsidesign.files.wordpress.com/2019/01/chapter-3-combinational-circuits.pdf
  34. https://fr.scribd.com/document/474078991/NMOS-inverter-pdf-version-1
  35. https://ece424.cankaya.edu.tr/uploads/files/Chap16-1-NMOS-Inverter.pdf
  36. https://www.mdpi.com/2072-666X/15/10/1187
  37. https://www.researchgate.net/publication/346646209_Assessment_of_High-k_Gate_Stack_on_Sub-10nm_SOI-FinFET_for_High-Performance_Analog_and_RF_Applications_Perspective
  38. https://www.sciencedirect.com/science/article/abs/pii/S0167931725000723
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  41. https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk09/l26/EE2301Exp3F10.pdf
  42. https://electronics.stackexchange.com/questions/110649/why-is-nand-gate-preferred-over-nor-gate-in-industry
  43. https://www.edaboard.com/threads/what-is-more-preferred-in-cmos-nand-or-nor.116448/
  44. https://ee173-spring17-01.courses.soe.ucsc.edu/system/files/attachments/an-77.pdf
  45. https://www.ti.com/lit/pdf/snoa254
  46. https://www.sfu.ca/~jeffpell/papers/PostPellMartin.pdf
  47. https://www.ece.lsu.edu/alex/EE2720/EE2720_HO9.pdf
  48. https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/logic_gates.html
  49. https://www.geeksforgeeks.org/digital-logic/realization-of-logic-gate-using-universal-gates/
  50. https://www.geeksforgeeks.org/implementation-of-xor-gate-from-nor-gate/
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