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NEC V20
The NEC V20 is a microprocessor that was designed and produced by NEC. It is both pin compatible and object-code compatible with the Intel 8088, with an instruction set architecture (ISA) similar to that of the Intel 80188 with some extensions. The V20 was introduced in November 1982.
The V20's die comprised 63,000 transistors; more than double the 29,000 of the 8088 CPU. The chip was designed for a clock duty cycle of 50%, compared to the 33% duty cycle used by the 8088. The V20 has two 16-bit wide internal databuses, allowing two data transfers to occur concurrently. Differences like that meant that a V20 could typically complete more instructions in a given time than an Intel 8088 running at the same frequency.
The V20 was fabricated in 2-micron CMOS technology. Early versions ran at speeds of 5, 8, and 10 MHz. In 1990, an upgrade to the fabrication process technology resulted in the V20H and V20HL, with improved performance and reduced power consumption. Later versions added speeds of 12 and 16 MHz. The V20HLs were also completely static, allowing their clock to be stopped.
The V20 was described as 16-bits wide internally. It used an 8-bit external data bus that was multiplexed onto the same pins as the low byte of the address bus. Its 20-bit wide address bus was able to address 1 MB of memory.
The V20 was reported to have been compatible with the Intel 8087 floating-point unit (FPU) coprocessor. NEC also designed their own FPU, the μPD72091, which was cancelled before reaching production. They followed this with a revised design, the μPD72191, but it is unclear how many, if any, of this second part were produced.
The V30, a nearly identical CPU with a 16-bit wide external data bus, debuted on September 1, 1983. It was pin and object-code compatible with the Intel 8086.
The V20's ISA includes several instructions not executed by the 8088, with instructions for bit manipulation, packed BCD operations, multiplication, and division. They also include new real-mode instructions from the Intel 80286.
The ADD4S, SUB4S, and CMP4S instructions were able to add, subtract, and compare huge packed binary-coded decimal numbers stored in memory. Instructions ROL4 and ROR4 rotate four-bit nibbles. Another family consisted of the TEST1, SET1, CLR1, and NOT1 instructions, which test, set, clear, and invert single bits of their operands, but are far less efficient than the later i80386 equivalents BT, BTS, BTR, and BTC; neither are their encodings compatible. There were two instructions to extract and insert bit fields of arbitrary lengths (EXT, INS). And finally, there were two additional repeat prefixes, REPC and REPNC, which amended the original REPE and REPNE instructions for scanning a string of bytes or words (with instructions SCAS and CMPS) while a less or not less condition remained true.
Hub AI
NEC V20 AI simulator
(@NEC V20_simulator)
NEC V20
The NEC V20 is a microprocessor that was designed and produced by NEC. It is both pin compatible and object-code compatible with the Intel 8088, with an instruction set architecture (ISA) similar to that of the Intel 80188 with some extensions. The V20 was introduced in November 1982.
The V20's die comprised 63,000 transistors; more than double the 29,000 of the 8088 CPU. The chip was designed for a clock duty cycle of 50%, compared to the 33% duty cycle used by the 8088. The V20 has two 16-bit wide internal databuses, allowing two data transfers to occur concurrently. Differences like that meant that a V20 could typically complete more instructions in a given time than an Intel 8088 running at the same frequency.
The V20 was fabricated in 2-micron CMOS technology. Early versions ran at speeds of 5, 8, and 10 MHz. In 1990, an upgrade to the fabrication process technology resulted in the V20H and V20HL, with improved performance and reduced power consumption. Later versions added speeds of 12 and 16 MHz. The V20HLs were also completely static, allowing their clock to be stopped.
The V20 was described as 16-bits wide internally. It used an 8-bit external data bus that was multiplexed onto the same pins as the low byte of the address bus. Its 20-bit wide address bus was able to address 1 MB of memory.
The V20 was reported to have been compatible with the Intel 8087 floating-point unit (FPU) coprocessor. NEC also designed their own FPU, the μPD72091, which was cancelled before reaching production. They followed this with a revised design, the μPD72191, but it is unclear how many, if any, of this second part were produced.
The V30, a nearly identical CPU with a 16-bit wide external data bus, debuted on September 1, 1983. It was pin and object-code compatible with the Intel 8086.
The V20's ISA includes several instructions not executed by the 8088, with instructions for bit manipulation, packed BCD operations, multiplication, and division. They also include new real-mode instructions from the Intel 80286.
The ADD4S, SUB4S, and CMP4S instructions were able to add, subtract, and compare huge packed binary-coded decimal numbers stored in memory. Instructions ROL4 and ROR4 rotate four-bit nibbles. Another family consisted of the TEST1, SET1, CLR1, and NOT1 instructions, which test, set, clear, and invert single bits of their operands, but are far less efficient than the later i80386 equivalents BT, BTS, BTR, and BTC; neither are their encodings compatible. There were two instructions to extract and insert bit fields of arbitrary lengths (EXT, INS). And finally, there were two additional repeat prefixes, REPC and REPNC, which amended the original REPE and REPNE instructions for scanning a string of bytes or words (with instructions SCAS and CMPS) while a less or not less condition remained true.