TeraScale (microarchitecture)

TeraScale is the codename for a family of graphics processing unit microarchitectures developed by ATI Technologies/AMD and their second microarchitecture implementing the unified shader model following Xenos. TeraScale replaced the old fixed-pipeline microarchitectures and competed directly with Nvidia's first unified shader microarchitecture named Tesla.

TeraScale was used in Radeon HD 2000 manufactured in 80 nm and 65 nm, Radeon HD 3000 manufactured in 65 nm and 55 nm, Radeon HD 4000 manufactured in 55 nm and 40 nm, Radeon HD 5000 and Radeon HD 6000 manufactured in 40 nm. TeraScale was also used in the AMD Accelerated Processing Units code-named "Brazos", "Llano", "Trinity" and "Richland". TeraScale is even found in some of the succeeding graphics cards brands.

TeraScale is a VLIW SIMD architecture, while Tesla is a RISC SIMD architecture, similar to TeraScale's successor Graphics Core Next. TeraScale implements HyperZ.

An LLVM code generator (i.e. a compiler back-end) is available for TeraScale, but it seems to be missing in LLVM's matrix. E.g. Mesa 3D makes use of it.

TeraScale was first announced and released with the Radeon HD 2000 series in 2007. At SIGGRAPH 08 in December 2008, AMD employee Mike Houston described some details of the TeraScale microarchitecture.

At FOSDEM09 Matthias Hopf from AMDs technology partner SUSE Linux presented a slide regarding the programming of open-source driver for the R600.

Previous GPU architectures implemented fixed-pipelines, i.e. there were distinct shader processors for each type of shader. TeraScale leverages many flexible shader processors which can be scheduled to process a variety of shader types, thereby significantly increasing GPU throughput (dependent on application instruction mix as noted below). The R600 core processes vertex, geometry, and pixel shaders as outlined by the Direct3D 10.0 specification for Shader Model 4.0, in addition to full OpenGL 3.3 support.

The new unified shader functionality is based upon a very long instruction word (VLIW) architecture in which the core executes operations in parallel.