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UNIVAC LARC
The UNIVAC LARC, short for the Livermore Advanced Research Computer, is a mainframe computer designed to a requirement published by Edward Teller in order to run hydrodynamic simulations for nuclear weapon design. It was one of the earliest supercomputers. It used solid-state electronics.
The LARC architecture supported multiprocessing with two CPUs (called Computers) and an input/output (I/O) Processor (called the Processor). Two LARC machines were built, the first delivered to Livermore in June 1960, and the second to the Navy's David Taylor Model Basin. Both examples had only one CPU, so no multiprocessor LARCs were ever built. Livermore decommissioned their LARC in December 1968 and the Navy's LARC was turned off in April 1969.
The LARC CPUs were able to perform addition in about 4 microseconds, corresponding to about 250 kIPS speed. This made it the fastest computer in the world until 1962 when the IBM 7030 Stretch took the title. The 7030 started as IBM's entry to the LARC contest, but Teller chose the simpler Univac over the riskier IBM design.
The LARC was a decimal mainframe computer with 60 bits per word. It used bi-quinary coded decimal arithmetic with five bits per digit (see below), allowing for 11-digit signed numbers. Instructions were 60 bits long, one per word. The basic configuration had 26 general-purpose registers, which could be expanded to 99. The general-purpose registers had an access time of one microsecond.
LARC weighed about 115,000 pounds (58 short tons; 52 t).
The basic configuration had one Computer and LARC could be expanded to a multiprocessor with a second Computer.
The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 magnetic drum storage units, four to forty UNISERVO II tape drives, two electronic page recorders (a 35mm film camera facing a cathode-ray tube), one or two high-speed printers, and a high-speed punched card reader.
The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20,000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97,500 words. The core memory had one parity bit on each digit for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4-microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).
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UNIVAC LARC AI simulator
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UNIVAC LARC
The UNIVAC LARC, short for the Livermore Advanced Research Computer, is a mainframe computer designed to a requirement published by Edward Teller in order to run hydrodynamic simulations for nuclear weapon design. It was one of the earliest supercomputers. It used solid-state electronics.
The LARC architecture supported multiprocessing with two CPUs (called Computers) and an input/output (I/O) Processor (called the Processor). Two LARC machines were built, the first delivered to Livermore in June 1960, and the second to the Navy's David Taylor Model Basin. Both examples had only one CPU, so no multiprocessor LARCs were ever built. Livermore decommissioned their LARC in December 1968 and the Navy's LARC was turned off in April 1969.
The LARC CPUs were able to perform addition in about 4 microseconds, corresponding to about 250 kIPS speed. This made it the fastest computer in the world until 1962 when the IBM 7030 Stretch took the title. The 7030 started as IBM's entry to the LARC contest, but Teller chose the simpler Univac over the riskier IBM design.
The LARC was a decimal mainframe computer with 60 bits per word. It used bi-quinary coded decimal arithmetic with five bits per digit (see below), allowing for 11-digit signed numbers. Instructions were 60 bits long, one per word. The basic configuration had 26 general-purpose registers, which could be expanded to 99. The general-purpose registers had an access time of one microsecond.
LARC weighed about 115,000 pounds (58 short tons; 52 t).
The basic configuration had one Computer and LARC could be expanded to a multiprocessor with a second Computer.
The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 magnetic drum storage units, four to forty UNISERVO II tape drives, two electronic page recorders (a 35mm film camera facing a cathode-ray tube), one or two high-speed printers, and a high-speed punched card reader.
The LARC used core memory banks of 2500 words each, housed four banks per memory cabinet. The basic configuration had eight banks of core (two cabinets), 20,000 words. The memory could be expanded to a maximum of 39 banks of core (ten cabinets with one empty bank), 97,500 words. The core memory had one parity bit on each digit for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4-microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).