WDC 65C265

The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor.

The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.