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X86 memory models
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X86 memory models
In computing, the x86 memory models are a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers are used and the default size of pointers.
Four registers are used to refer to four segments on the 16-bit x86 segmented memory architecture. DS (data segment), CS (code segment), SS (stack segment), and ES (extra segment). Another 16-bit register can act as an offset into a given segment, and so a logical address on this platform is written segment:offset, typically in hexadecimal notation. In real mode, in order to calculate the physical address of a byte of memory, the hardware shifts the contents of the appropriate segment register 4 bits left (effectively multiplying by 16), and then adds the offset.
For example, the logical address 7522:F139 yields the 20-bit physical address:
Note that this process leads to aliasing of memory, such that any given physical address has up to 4096 corresponding logical addresses. This complicates the comparison of pointers to different segments.
Pointer formats are known as near, far, or huge. These examples each load two adjacent integers into AX and DX from an address stored at [reg].
In reality, a compiler may optimize the above Huge pointer code using no branches. This version decrements the segment unconditionally and to compensate, a segment length (0x10) is added to BX. Unlike the previous Huge example, this version does not require the segment:offset to be normalized.
The memory models are:
In protected mode a segment cannot be both writable and executable. Therefore, when implementing the Tiny memory model the code segment register must point to the same physical address and have the same limit as the data segment register. This defeated one of the features of the 80286, which makes sure data segments are never executable and code segments are never writable (which means that self-modifying code is never allowed). However, on the 80386, with its paged memory management unit it is possible to protect individual memory pages against writing.
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X86 memory models
In computing, the x86 memory models are a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers are used and the default size of pointers.
Four registers are used to refer to four segments on the 16-bit x86 segmented memory architecture. DS (data segment), CS (code segment), SS (stack segment), and ES (extra segment). Another 16-bit register can act as an offset into a given segment, and so a logical address on this platform is written segment:offset, typically in hexadecimal notation. In real mode, in order to calculate the physical address of a byte of memory, the hardware shifts the contents of the appropriate segment register 4 bits left (effectively multiplying by 16), and then adds the offset.
For example, the logical address 7522:F139 yields the 20-bit physical address:
Note that this process leads to aliasing of memory, such that any given physical address has up to 4096 corresponding logical addresses. This complicates the comparison of pointers to different segments.
Pointer formats are known as near, far, or huge. These examples each load two adjacent integers into AX and DX from an address stored at [reg].
In reality, a compiler may optimize the above Huge pointer code using no branches. This version decrements the segment unconditionally and to compensate, a segment length (0x10) is added to BX. Unlike the previous Huge example, this version does not require the segment:offset to be normalized.
The memory models are:
In protected mode a segment cannot be both writable and executable. Therefore, when implementing the Tiny memory model the code segment register must point to the same physical address and have the same limit as the data segment register. This defeated one of the features of the 80286, which makes sure data segments are never executable and code segments are never writable (which means that self-modifying code is never allowed). However, on the 80386, with its paged memory management unit it is possible to protect individual memory pages against writing.