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Capacitance multiplier

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A capacitance multiplier is designed to make a capacitor function like a much larger capacitor. This can be achieved in at least two ways.

An active circuit, using a device such as a transistor or operational amplifier
A passive circuit, using autotransformers. These are typically used for calibration standards. The General Radio / IET labs 1417 is one such example.

Capacitor multipliers make low-frequency filters and long-duration timing circuits possible that would be impractical with actual capacitors. Another application is in DC power supplies where very low ripple voltage (under load) is of paramount importance, such as in class-A amplifiers.

Transistor-based

[edit]

A basic transistor capacitance multiplier.

Here the capacitance of capacitor C1 is multiplied by approximately the transistor's current gain (β).

Without Q, R2 would be the load on the capacitor. With Q in place, the loading imposed upon C1 is simply the load current reduced by a factor of (β + 1). Consequently, C1 appears multiplied by a factor of (β + 1) when viewed by the load.

Another way is to look at this circuit as an emitter follower with capacitor C1 holding voltage at base constant with load of input impedance of Q1: R2 multiplied by (1 + β), so the output current is stabilized much more against power line voltage noise. ^{[citation needed]}

Operational amplifier based

[edit]

Here, the capacitance of capacitor C1 is multiplied by the ratio of resistances: C = C1 * R1 / R2 at the Vi node.^[1]

The synthesized capacitance also brings a series resistance approximately equal to R2, and a leakage current appears across the capacitance because of the input offsets of OP. These problems can be avoided by a circuit with two op amps. In this circuit the input to OP1 can be a.c.-coupled if necessary, and the capacitance can be made variable by making the ratio of R1 to R2 variable. C = C1 * (1 + (R2 / R1)).^[1]

In the circuits described above the capacitance is grounded, but floating capacitance multipliers are possible.

A negative capacitance multiplier can be created with a negative impedance converter.^[1]

Autotransformer based

[edit]

These permit the synthesis of accurate values of large capacitance (e.g., 1 F) by multiplying the capacitance of a high-precision lower value capacitor by the use of two^{[clarification needed]} transformers. Its function acts as a reference standard, not as a general-purpose circuit element. The resulting device is a four-terminal element and cannot be used at dc.

References

[edit]

^ ^a ^b ^c Op Amp Circuit Collection, National Semiconductor Application Note AN-31, reproduced in National Semiconductor Applications Handbook, 1994, p. 86.

IET Labs 1417 FOUR-TERMINAL CAPACITANCE STANDARD

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A capacitance multiplier is an electronic circuit that simulates the function of a far larger capacitor by using a smaller physical capacitor in conjunction with an active device, such as a transistor or operational amplifier, to amplify the effective capacitance value, often by a factor related to the device's gain.^[1] In its simplest transistor-based form, the circuit operates as an emitter follower with a capacitor connected to the base and a resistor feeding the input signal, where the effective capacitance becomes approximately (1 + β)C, with β denoting the transistor's current gain and C the physical capacitance.^[2] This multiplication effect lowers the cutoff frequency of associated RC filters, enabling superior ripple rejection and noise suppression compared to passive capacitors alone.^[2] Capacitance multipliers find widespread use in power supply designs to filter residual AC ripple and noise, particularly in low-current applications like audio amplifiers, RF circuits, and data acquisition systems, where they reduce the need for bulky electrolytic capacitors and minimize space requirements.^[3] In integrated circuits, CMOS-based variants employ operational amplifiers or specialized building blocks like voltage differencing transconductance amplifiers to achieve multiplication factors up to 100 with high accuracy (error <0.5%), making them essential for on-chip filtering, timing, and compensation in mixed-signal and power management ICs.^[4] While not true voltage regulators, they can complement regulators by providing dynamic low-pass filtering, though they introduce a voltage drop (typically 0.65–3 V) across the active device and require sufficient headroom for operation.^[1] The concept of capacitance multiplication has roots in analog circuit techniques from the 1960s,^[5] with early on-chip implementations emerging in the 1990s using current conveyors and Miller-compensated amplifiers to address the challenges of fabricating large capacitors in silicon processes.^[6] Modern advancements include electronically tunable grounded multipliers based on devices like voltage differencing buffered amplifiers, enhancing versatility in low-frequency filters and sensor interfaces.^[7] Recent developments (as of 2025) include resistor-less CMOS realizations and voltage-mode multipliers tunable down to 12 mHz for ultra-low frequency filters.^[8]^[9] Despite their benefits, limitations such as nonlinearity in transistor versions and sensitivity to load currents necessitate careful design to maintain performance.^[3]

Overview

Definition and Purpose

A capacitance multiplier is an electronic circuit that simulates the behavior of a much larger capacitor by employing a smaller physical capacitor in conjunction with active components, such as transistors or operational amplifiers.^[10]^[1] This technique effectively amplifies the apparent capacitance value without requiring the physical size or expense associated with oversized passive components.^[11] The primary purpose of a capacitance multiplier is to provide high effective capacitance for tasks like filtering, decoupling, and timing in electronic circuits, while mitigating challenges such as the bulkiness, high cost, and potential leakage currents of large electrolytic capacitors.^[1] In particular, it addresses space constraints and economic considerations in power supply designs, where substantial capacitance is needed to smooth voltage ripple but physical limitations make large capacitors impractical.^[12] By leveraging active elements, the circuit enables the use of compact ceramic or film capacitors to achieve equivalent performance.^[11] Capacitance multiplication occurs through feedback or buffering mechanisms that scale the current or voltage across the small capacitor, making it behave as if it were significantly larger—often by factors related to the gain of the active components.^[10] This approach has been commonly employed in analog electronics since the mid-20th century to replicate the low-frequency response of electrolytic capacitors using smaller alternatives.^[12]

Historical Development

The capacitance multiplier circuit emerged during the 1950s and 1960s amid the rapid advancement of transistor technology, serving as an active filtering technique to simulate larger capacitance values for voltage ripple reduction in power supplies, when bulky electrolytic capacitors were costly and space-intensive.^[13] This technique evolved from broader innovations in semiconductor-based circuit simulation, without a single attributed inventor. A notable early application appeared in the 1969 JLH amplifier power supply, where a discrete transistor-based capacitance multiplier effectively lowered ripple on the DC rail, demonstrating its practicality in high-fidelity audio equipment.^[14] By the 1970s, the circuit saw wider adoption in professional audio gear, including microphone preamplifiers, as transistor designs matured for low-noise filtering.^[15] The technique's reliability was further underscored in influential analog design literature, such as the first edition of The Art of Electronics by Paul Horowitz and Winfield Hill (1980), which presented the capacitance multiplier as a standard method for enhancing power supply performance in discrete and integrated circuits.^[16] Operational amplifier-based configurations emerged in the late 20th century, offering improved precision and integration in mixed-signal systems. Transistor and op-amp forms have dominated due to their versatility. This evolution reflected ongoing refinements in active device technology, prioritizing compactness and noise rejection.

Operating Principles

Basic Mechanism

A capacitance multiplier operates by incorporating a small physical capacitor into an active circuit configuration, typically involving a feedback loop or buffer stage, where variations in voltage across the capacitor are either amplified or isolated to simulate the behavior of a much larger capacitor. This core mechanism effectively scales down the impedance presented to AC signals, allowing the circuit to filter ripple and noise more efficiently without requiring bulky components. The technique leverages the gain of active elements to enhance the capacitor's apparent value, making it particularly useful in applications demanding low ripple on DC supplies.^[1] Active devices, such as transistors, play a crucial buffering role in this setup by providing low output impedance to drive the load while maintaining high input impedance at the capacitor's connection point. This isolation prevents the load from discharging the capacitor excessively, thereby reducing voltage ripple by a factor proportional to the device's gain. The buffer ensures that the circuit can supply significant current to the load without compromising the filtering action of the small capacitor.^[17] Negative feedback is integral to the mechanism, as it stabilizes the output voltage against fluctuations, causing the circuit to respond primarily to AC components as if the capacitance were multiplied, while allowing DC to pass unimpeded. This feedback loop minimizes variations in the output, enhancing overall stability and ripple rejection.^[1] Unlike passive capacitance multipliers that rely on transformers or inductive elements for multiplication, active versions achieve gain-dependent scaling through semiconductor devices, offering compactness and efficiency without the need for bulky magnetics in most implementations. A common example is the transistor emitter follower configuration, which exemplifies this buffering and feedback approach.^[2]

Mathematical Foundation

The mathematical foundation of the capacitance multiplier rests on the application of Miller's theorem to scale the effective capacitance in feedback configurations. Consider a capacitor

C

connected between the input and output nodes of an amplifier with voltage gain

A_v = V_o / V_i

. Miller's theorem states that this capacitor is equivalent to an input capacitance

C_m = C (1 - A_v)

and an output capacitance

C_{out} = C (1 - 1/A_v)

. For inverting amplifiers where

A_v = -K

with

K > 0

, the input equivalent simplifies to

C_{eff} = C (1 + K)

, effectively multiplying the physical capacitance by the gain factor

K

. This derivation assumes ideal frequency-independent gain and negligible loading effects at the nodes.^[18] In transistor-based realizations, the gain

K

approximates the current gain

\beta

(or

h_{FE}

), yielding

C_{eff} \approx C (\beta + 1)

, where

\beta

is typically 100 or higher for bipolar junction transistors. More generally, across circuit types, the effective capacitance follows

C_{eff} = C \cdot K

, with

K

derived from the open-loop gain or feedback factor. To outline the derivation from a basic RC low-pass filter, start with the standard transfer function

H(s) = \frac{1}{1 + s R C}

, where

s

is the Laplace variable. Applying feedback via the amplifier introduces the Miller-scaled capacitance, transforming the denominator to

1 + s R C_{eff}

, thus

H(s) = \frac{1}{1 + s R K C}

. This assumes high loop gain (

K \gg 1

) and operation at low frequencies where the amplifier bandwidth exceeds the signal frequencies.^[2]^[19] The input impedance of the capacitance multiplier exhibits low-pass filter behavior, approximated as

Z_{in} \approx \frac{1}{s C_{eff}}

for frequencies where the effective capacitance dominates. This impedance scaling enables the circuit to mimic a larger grounded capacitor, with the pole frequency shifted to

f_p = \frac{1}{2\pi R C_{eff}}

. For ripple reduction in power supplies, the output ripple voltage follows from the transfer function: at low frequencies (

\omega \ll 1/(R C_{eff})

), attenuation is minimal.^[20]^[2] The multiplication factor

K

is inherently frequency-dependent, limited by the active device's bandwidth, causing effectiveness to roll off above approximately

f \approx 1/(2\pi R C)

, beyond which the gain

A_v

decreases and

C_{eff}

approaches

C

. This limitation arises from parasitic capacitances and finite amplifier bandwidth, ensuring the model applies primarily to low-frequency signals.^[19]

Circuit Types

Transistor-Based Designs

Transistor-based capacitance multipliers typically employ a bipolar junction transistor (BJT) configured as an emitter follower, where a resistor connects the input voltage to the base, a capacitor is placed from the base to ground, and the load is attached to the emitter.^[3] This simple arrangement acts as a low-pass filter followed by a buffer stage, with the emitter output providing a smoothed voltage to the load while the transistor handles higher current demands.^[21] In operation, the BJT buffers the capacitor by supplying load current through its collector-to-emitter path, effectively multiplying the capacitance value by the transistor's current gain plus one, yielding an effective capacitance of

C_\text{eff} = C \times (h_{fe} + 1)

, where

C

is the physical capacitor and

h_{fe}

(or

\beta

) is the small-signal current gain.^[3] The resistor sets the bias and forms the RC time constant with the capacitor, attenuating ripple at the base, while the emitter follower reproduces this filtered voltage at the output with minimal phase shift for low frequencies.^[2] Field-effect transistor (FET) implementations use a similar source follower configuration, with the capacitor connected from gate to ground and a bias resistor from input to gate.^[3] Due to the FET's negligible gate current, the simple configuration provides limited multiplication compared to BJT designs and behaves primarily as a buffered RC filter; specialized topologies with additional components are often used to achieve effective capacitance multiplication. Variations include using NPN transistors for positive supply rails and PNP for negative rails to accommodate different polarities, often with complementary pairs for bipolar supplies. A Zener diode can be added across the base-emitter junction for voltage regulation, clamping the output to a fixed drop below the input while maintaining ripple reduction.^[2] These designs offer low cost and simple implementation, making them suitable for discrete circuits in power supplies and audio applications where high precision is not required. However, at high frequencies, base (or gate) current loading increases due to the transistor's finite gain and parasitic capacitances, reducing the multiplication factor and raising output impedance, which can limit effectiveness above a few kilohertz.^[2] For example, a 100 μF capacitor with a BJT having

h_{fe} = 100

can achieve an effective capacitance of approximately 10 mF, significantly reducing ripple in a power supply from hundreds of millivolts to microvolts under moderate loads.^[21] Compared to operational amplifier-based designs, transistor versions provide adequate performance for less demanding applications but lack the precision of active feedback loops.^[3]

Operational Amplifier-Based Designs

Operational amplifier-based capacitance multipliers employ an op-amp in a non-inverting configuration to achieve precise control over the multiplication factor, typically using a feedback network of resistors to set the closed-loop gain. The circuit consists of the op-amp's non-inverting input connected to the signal source, with the inverting input fed by a voltage divider from the output to ground, and a small feedback capacitor connected across the output to ground. This setup buffers and amplifies the voltage, making the effective capacitance at the input terminals much larger than the physical capacitor used.^[10] In operation, the multiplication factor

K

is determined by the closed-loop gain of the op-amp, given by

K = 1 + \frac{R_1}{R_2}

, where

R_1

and

R_2

form the feedback divider; for large ratios,

K \approx \frac{R_1}{R_2}

. The effective capacitance is then

C_{\text{eff}} = K \cdot C

, where

C

is the physical capacitor. For instance, a small 1 µF capacitor can behave like a much larger one, potentially equivalent to a supercapacitor depending on the gain factor. This provides performance suitable for applications requiring multiplication ratios set by the resistor values, potentially higher than typical transistor current gains if the op-amp's bandwidth permits.^[10]^[22] Variations include integrations with active filters, where the capacitance multiplier enhances low-frequency response in second-order low-pass filters, achieving cutoff frequencies as low as 65 Hz with minimal capacitor sizes. Dual-supply configurations support bipolar signals, while CMOS op-amps enable low-power implementations suitable for portable or integrated systems, reducing overall power dissipation in continuous-time integrators.^[22]^[23] These designs offer better linearity due to the op-amp's low distortion characteristics and wider bandwidth compared to discrete transistor versions, making them ideal for integrated circuit applications where space constraints limit physical capacitor sizes. However, they are susceptible to instability if the phase margin is inadequate, particularly at high gain settings that approach the op-amp's unity-gain bandwidth. For instance, a 1 μF physical capacitor can be multiplied to an effective 100 μF in precision timing circuits, such as those in switched-capacitor filters, by setting

K = 100

.^[23]^[18]

Autotransformer-Based Designs

Autotransformer-based capacitance multipliers employ passive inductive elements to scale the effective capacitance of a physical capacitor, leveraging transformer turns ratios for multiplication without active components. These designs typically feature an autotransformer or inductive voltage divider (IVD) with a tapped winding, where a reference capacitor is connected across the secondary section to create a synthetic larger capacitance seen at the primary. A representative implementation is the four-terminal configuration using two precision IVDs in series with a 1 μF polystyrene reference capacitor, enabling selectable effective values from 1 μF to 1 F.^[24] The operation relies on the inductive coupling to transform the capacitive impedance according to the square of the turns ratio. For a single autotransformer with turns ratio

N

(secondary to primary), the effective capacitance approximates

C_\text{eff} \approx C \cdot N^2

, where

C

is the physical capacitor value; in multi-stage setups like dual IVDs with division ratios

\alpha

and

\beta

(both less than 1), this becomes

C_\text{eff} \approx C / (\alpha \beta)

, equivalent to multiplication by

(1/\alpha)(1/\beta)

. Low-frequency performance requires compensation for inductive effects, often via padding capacitors to maintain accuracy within 0.25% at frequencies like 100 Hz or 1 kHz.^[24] Such passive designs excel in precision measurement applications, providing isolation through the transformer's magnetic coupling and avoiding semiconductor nonlinearities, but they are bulky due to toroidal cores and exhibit efficiency reductions at low frequencies from residual inductance (approximately 400 H per IVD).^[25] For instance, the GenRad 1417 standard uses decade-switched IVD ratios to multiply a 1 μF capacitor by up to

10^6

, yielding 1 F for calibration of high-capacitance meters, a technique historically prominent in mid-20th-century instrumentation during the tube era.^[26] Today, these are rare in power electronics, supplanted by compact solid-state alternatives, though they persist in RF and high-voltage contexts requiring galvanic isolation and linear scaling.^[24]

Applications

Power Supply Filtering

Capacitance multipliers play a key role in DC power supplies by providing post-rectifier filtering to smooth 50/60 Hz ripple voltages, thereby replacing the need for large electrolytic capacitors that would otherwise be required to achieve similar performance.^[27] In linear power supplies, this technique effectively attenuates low-frequency ripple originating from the mains rectification process, allowing smaller, more cost-effective capacitors—such as a 47 μF unit—to emulate the behavior of much larger ones, like 4700 μF, through the amplification effect of the transistor's current gain.^[27] This reduction in physical capacitance minimizes space and weight in the power supply design while maintaining effective smoothing.^[28] Typically implemented as a pre-regulator stage immediately after the rectifier bridge or following a basic reservoir capacitor, the capacitance multiplier passes the DC supply through a transistor configuration before reaching the load or subsequent voltage regulator.^[14] It is particularly suited to linear supplies where the ripple is predominantly at line frequencies, offering superior performance compared to switching supplies, in which higher-frequency noise may not be as effectively suppressed due to the circuit's low-pass characteristics.^[27] Transistor-based designs are favored for their simplicity in this context, requiring minimal components to achieve the desired filtering.^[27] Performance in power supply filtering often exceeds 60 dB of ripple rejection at 50/60 Hz and 100/120 Hz, with simulations showing reductions to below 1 mV RMS from input ripples of several volts.^[28] For instance, a basic circuit using a Darlington transistor pair can attenuate 100 Hz ripple by approximately 65 dB under a 2.5 A load, ensuring near-DC output suitable for sensitive applications.^[28] This approach has been commonly employed in vintage audio power supplies to eliminate audible hum from mains interference, providing cleaner rails for amplifiers and preamplifiers.^[14] Additionally, capacitance multipliers can handle transient loads better than plain capacitors in certain steady-state scenarios, as the active feedback mechanism helps maintain voltage stability during moderate current demands, though sudden high transients may cause temporary ripple breakthrough.^[27]

Audio and Signal Processing

In audio circuits, capacitance multipliers serve as effective decoupling elements in amplifiers, minimizing power supply noise coupling into the signal path by simulating large capacitance values with smaller components. This approach is particularly beneficial in Class-A amplifiers, where it helps achieve low hum levels by providing high ripple rejection, often reducing output ripple to below 1 mV even at currents up to 1.25 A. For instance, in high-fidelity systems, these circuits ensure stable voltage rails with extremely low noise, preserving audio clarity and fidelity without the need for bulky capacitors.^[17]^[3] A key application in audio preamplification involves phono stages, where capacitance multipliers augment RC filters to suppress 120 Hz hum originating from full-wave rectification of 60 Hz mains power, thereby maintaining signal integrity in low-level inputs. This filtering maintains low distortion while enabling the use of minimal capacitor sizes, such as 0.22 μF multiplied by transistor gain (β ≈ 50) to achieve effective low-pass performance comparable to much larger values. In hi-fi designs, this preference stems from the ability to employ smaller, higher-quality capacitors, sidestepping the leakage and degradation issues associated with large electrolytic types that can introduce subtle audio artifacts.^[29]^[2]^[17] Beyond pure audio, capacitance multipliers find use in signal processing tasks, such as simulating large capacitors in active filters and integrators to define timing constants in oscillators and modulators. In synthesizer circuits, they are integrated into phase-locked loop (PLL) loop filters to minimize area while providing high multiplication factors for the integrating capacitor, enhancing stability and reducing phase noise in voltage-controlled oscillators (VCOs). These implementations support precise signal conditioning in both analog and RF-sensitive environments, including voltage-controlled elements in modulation schemes.^[30]^[31]

Integrated Circuits and RF Applications

In integrated circuits, CMOS-based capacitance multipliers using operational amplifiers or voltage differencing transconductance amplifiers achieve multiplication factors up to 100 with high accuracy (error <0.5%), enabling on-chip filtering, timing, and compensation in mixed-signal and power management ICs.^[4] These are particularly useful in data acquisition systems for noise suppression and stable reference voltages.^[3] In RF circuits, they appear in PLL-based frequency synthesizers for wireless communications, such as in CMOS PLLs operating at GHz frequencies, where they reduce the size of loop filter capacitors while maintaining low phase noise.^[31] Modern designs include electronically tunable grounded multipliers based on voltage differencing buffered amplifiers for versatile low-frequency applications.^[7]

Advantages and Limitations

Key Benefits

Capacitance multipliers provide significant space savings by allowing the use of much smaller physical capacitors to achieve equivalent filtering performance, such as employing a 500 µF capacitor in place of a hypothetical 1 F component, thereby reducing overall board area in electronic designs.^[17] This approach also lowers costs compared to sourcing large electrolytic capacitors or bulky inductors, although additional components like heatsinks may partially offset these savings.^[17] In terms of performance, capacitance multipliers offer superior ripple rejection at low frequencies, achieving up to 73 dB attenuation at 100 Hz with a two-pole filter configuration, which effectively minimizes voltage ripple to less than 1 mV RMS.^[17] They simulate large capacitors with lower equivalent series resistance (ESR) and inductance (ESL), resulting in output impedances as low as milliohms that enhance filtering efficiency over passive solutions.^[17] Reliability is improved by decreasing dependence on large electrolytic capacitors, which are prone to electrolyte drying out over time and exhibit high leakage currents, thus mitigating associated failure risks in long-term operation.^[5] Multiplication ratios as high as 1000 can be realized using Darlington transistor pairs, enabling highly compact designs suitable for portable devices or restorations of vintage audio equipment.^[17] In power supply applications where space is critical, such as in class-A amplifiers, this facilitates efficient integration without compromising output stability.^[5]

Principal Drawbacks

Capacitance multipliers exhibit bandwidth limitations inherent to their design, functioning effectively only at frequencies below the circuit's cutoff, typically defined by the RC time constant where high-frequency noise experiences reduced attenuation and passes through more readily. In standard mirror-based configurations, a zero in the transfer function occurs at

F_z = \frac{1}{2\pi R_s C_i}

, where

R_s

is the series resistance (often

1/g_m

of the transistor), marking the point at which the circuit transitions from capacitive to resistive behavior, thereby limiting its utility for broadband noise suppression.^[32] For common implementations with resistor values around 1 kΩ and capacitors of 1000 µF, the -3 dB point may occur as low as 0.159 Hz, emphasizing their suitability for low-frequency ripple rejection but not higher-frequency signals.^[17] A significant drawback in transistor-based capacitance multipliers is the voltage drop across the active device, requiring 1-2 V of headroom due to the base-emitter junction voltage (approximately 0.7 V) and collector-emitter saturation voltage, which renders them impractical for low-voltage rails below about 5 V.^[17] This dropout can reduce the effective output voltage by up to 2 V or more, depending on the transistor configuration, such as Darlington pairs that exacerbate the loss.^[17] The incorporation of active components adds design complexity, potential instability from feedback loops, and elevated power consumption relative to passive capacitors, as the transistors draw quiescent current even under light loads.^[17] Furthermore, these active elements introduce additional noise, including thermal and shot noise from the transistors, which can degrade the overall signal integrity and limit ripple attenuation to around 60 dB in practice, short of the theoretical maximum. Comprehensive noise analyses of active-element-based multipliers highlight the need for optimization to mitigate these contributions from transconductance cells and multipliers.^[17]^[33] Capacitance multipliers are particularly sensitive to temperature variations, as the transistor's current gain (

\beta

) decreases with rising temperature, altering the effective multiplication factor and potentially reducing filtering performance by 20-50% over typical operating ranges (e.g., 25–125°C).^[34] They also underperform for fast transients compared to physical large capacitors, exhibiting slow recovery times (e.g., 200-300 ms for load steps in audio amplifiers) and ripple breakthrough under dynamic conditions like pulsed loads, due to the limited slew rate and bandwidth of the active path.^[17]

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