DDR2 SDRAM

Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It is a JEDEC standard (JESD79-2); first published in September 2003. DDR2 succeeded the original DDR SDRAM specification, and was itself succeeded by DDR3 SDRAM in 2007. DDR2 DIMMs are neither forward compatible with DDR3 nor backward compatible with DDR.

In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.

Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same bandwidth but with better latency. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules. The maximum capacity on commercially available DDR2 DIMMs is 8 GB, but chipset support and availability for those DIMMs is sparse and more common 2 GB per DIMM are used.^{[citation needed]}

DDR2 SDRAM was first produced by Samsung in 2001. In 2003, the JEDEC standards organization presented Samsung with its Technical Recognition Award for the company's efforts in developing and standardizing DDR2.

DDR2 was officially introduced in the second quarter of 2003 at two initial clock rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200 MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance, unless bandwidth dependent tasks such as integrated graphics rendering are used. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available.

The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length is two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits are read or written to or from a four-bit-deep prefetch queue. This queue receives or transmits its data over the data bus in two data bus clock cycles (each clock cycle transferrs two bits of data). Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data can be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array can be accessed. DDR2 SDRAM is designed with such a scheme to avoid an excessive increase in power consumption.

DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is four bits deep, whereas it is two bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble BGA package as compared to the TSSOP package of the previous memory generations such as DDR SDRAM and SDR SDRAM. This packaging change was necessary to maintain signal integrity at higher bus speeds.