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CTIA and GTIA
CTIA and GTIA
from Wikipedia
NTSC GTIA chip manufactured by Okidata

Color Television Interface Adaptor[1] (CTIA) and its successor Graphic Television Interface Adaptor[1] (GTIA) are custom chips used in the Atari 8-bit computers and Atari 5200 home video game console. In these systems, a CTIA or GTIA chip works together with ANTIC to produce the video display. ANTIC generates the playfield graphics (text and bitmap) while CTIA/GTIA provides the color for the playfield and adds overlay objects known as player/missile graphics (sprites). Under the direction of Jay Miner, the CTIA/GTIA chips were designed by George McLeod with the technical assistance of Steve Smith.[2][3][4]

Color Television Interface Adaptor and Graphic Television Interface Adaptor are names of the chips as stated in the Atari field service manual.[1] Various publications named the chips differently, sometimes using the alternative spelling Adapter[5][6] or Graphics,[3] or claiming that the "C" in "CTIA" stands for Colleen/Candy[5] and "G" in "GTIA" is for George.[3][5][6][7]

History

[edit]

2600 and TIA

[edit]

Atari had built their first display driver chip, the Television Interface Adaptor universally referred to as the TIA, as part of the Atari 2600 console.[8] The TIA display logically consisted of two primary sets of objects, the "players" and "missiles" that represented moving objects, and the "playfield" which represented the static background image on which the action took place. The chip used data in memory registers to produce digital signals that were converted in realtime via a digital-to-analog converter and RF modulator to produce a television display.

The conventional way to draw the playfield is to use a bitmap held in a frame buffer, in which each memory location in the frame buffer represents one or more locations on the screen. In the case of the 2600, which normally used a resolution of 160x192 pixels, a frame buffer would need to have at least 160x192/8 = 3840 bytes of memory. Built in an era where RAM was very expensive, the TIA could not afford this solution.

Instead, the system implemented a display system that used a single 20-bit memory register that could be copied or mirrored on the right half of the screen to make what was effectively a 40-bit display. Each location could be displayed in one of four colors, from a palette of 128 possible colors. The TIA also included several other display objects, the "players" and "missiles". These consisted of two 8-bit wide objects known as "players", a single 1-bit object known as the "ball", and two 1-bit "missiles". All of these objects could be moved to arbitrary horizontal locations via settings in other registers.

The key to the TIA system, and the 2600's low price, was that the system implemented only enough memory to draw a single line of the display, all of which held in registers. To draw an entire screen full of data, the user code would wait until the television display reached the right side of the screen and update the registers for the playfield and player/missiles to correctly reflect the next line on the display. This scheme drew the screen line-by-line from program code on the ROM cartridge, a technique known as "racing the beam".

CTIA

[edit]

Atari initially estimated that the 2600 would have short market lifetime of three years when it was designed in 1976, which meant the company would need a new design by 1979.[8] Initially this new design was simply an updated 2600-like game console, and was built around a similar basic design, simply updated. Work on what would become the CTIA started in 1977, and aimed at delivering a system with twice the resolution and twice the number of colours. Moreover, by varying the number of colours in the playfield, much higher resolutions up to 320 pixels horizontally could be supported. Players and missiles were also updated, including four 8-bit players and four 2-bit missiles, but also allowing an additional mode to combine the four missiles into a fifth player.

Shortly after design began, the home computer revolution started in earnest in the later half of 1977. In response, Atari decided to release two versions of the new machine, a low-end model as a games console, and a high-end version as a home computer.[8] In either role, a more complex playfield would be needed, especially support for character graphics in the computer role. Design of the CTIA was well advanced at this point, so instead of a redesign a clever solution was provided by adding a second chip that would effectively automate the process of racing the beam. Instead of the user's programming updating the CTIA's registers based on its interrupt timing, the new ANTIC would handle this chore, reading data from a framebuffer and feeding that to the CTIA on the fly.

As a result of these changes, the new chips provide greatly improved number and selection of graphics modes over the TIA. Instead of a single playfield mode with 20 or 40 bits of resolution, the CTIA/ANTIC pair can display six text modes and eight graphics modes with various resolutions and color depths, allowing the programmer to choose a balance between resolution, colours, and memory use for their display.

CTIA vs. GTIA

[edit]
The 256 Color Palette used in the GTIA chip, (NTSC only) with 16 hues, and 16 luminance values
This is what the Atari TIA and CTIA used as a palette, (NTSC only) with 16 hue, and only 8 luminance values, making up 128 unique colors.

The original design of the CTIA chip also included three additional color interpretations of the normal graphics modes. This feature provides alternate expressions of ANTIC's high-resolution graphics modes presenting 1 bit per pixel, 2 colors with one-half color clock wide pixels as 4 bits per pixel, up to 16 colors, two-color clock wide pixels. This feature was ready before the computers' November 1979 debut, but was delayed so much in the development cycle that Atari had already ordered a batch of about 100,000 CTIA chips with the graphics modes missing. Not wanting to throw away the already-produced chips, the company decided to use them in the initial release of the Atari 400 and 800 models in the US market. The CTIA-equipped computers, lacking the 3 extra color modes, were shipped until October–November 1981.[5][6] From this point, all new Atari units were equipped with the new chip, now called GTIA, that supported the new color interpretation modes.[6][9]

The original Atari 800/400 operating system supported the GTIA alternate color interpretation modes from the start,[9] which allowed for easy replacement of the CTIA with the GTIA once it was ready. Atari authorized service centers would install a GTIA chip in CTIA-equipped computers free of charge if the computer was under warranty; otherwise the replacement would cost $62.52.[6][7]

GTIA was also mounted in all later Atari XL and XE computers and Atari 5200 consoles.

Features

[edit]

The list below describes CTIA/GTIA's inherent hardware capabilities meaning the intended functionality of the hardware itself, not including results achieved by CPU-serviced interrupts or display kernels driving frequent register changes.

CTIA/GTIA is a television interface device with the following features:

  • Interprets the Playfield graphics data stream from ANTIC to apply color to the display.
  • Merges four Player and four Missile overlay objects (aka sprites) with ANTIC's Playfield graphics. Player/Missile features include:
    • Player/Missile pixel positioning is independent of the Playfield:
      • Player/Missile objects function normally in the vertical and horizontal overscan areas beyond the displayed Playfield.
      • Player/Missile objects function normally without an ANTIC Playfield.
    • Eight-bit wide Player objects and two-bit wide Missile objects where each bit represents one displayed pixel.
    • Variable pixel width (1, 2, or 4 color clocks wide)
    • Each Player/Missile object is vertically the height of the entire screen.
    • Variable pixel height when the data is supplied by ANTIC DMA (single or double scan lines per data)
    • Ability to independently shift each P/M object by one scan line vertically when operating on double scan lines per data.
    • Each Player and its associated Missile has a dedicated color register separate from the Playfield colors.
    • Multiple priority schemes for the order of graphics layers (P/M Graphics vs playfield)
    • Color merging between Players and Playfield producing extra colors.
    • Color merging between pairs of Players producing multi-color Players.
    • Missiles can be grouped together into a Fifth Player that uses a separate color register.
    • Collision detection between Players, Missiles, and Playfield graphics.
  • There are no fixed colors for normal (CTIA) color interpretation mode. All colors are generated via indirection through nine color registers. (Four for Player/Missile graphics, four for the Playfield, and one shared between the Playfield and the Fifth Player feature.)
    • Normal color interpretation mode provides choice of colors from a 128 color palette (16 colors with 8 luminance values for each)
    • A GTIA color interpretation mode can generate 16 luminances per color providing a 256 color palette.
  • The GTIA version of the chip adds three alternate color interpretation modes for the Playfield graphics.
    • 16 shades of a single hue from the 16 possible hues in the Atari palette. This is accessible in Atari BASIC as Graphics 9.
    • 15 hues in a single shade/luminance value plus background. This is accessible in Atari BASIC as Graphics 11.
    • 9 colors in any hue and luminance from the palette accomplished using all the Player/Missile and Playfield color registers for the Playfield colors. This is accessible in Atari BASIC as Graphics 10.
  • Reads the state of the joystick triggers (bottom buttons only for the Atari 5200 controllers).
  • It includes four input/output pins that are used in different ways depending on the system:
    • In Atari 8-bit computers, three of the pins are used to read state of the console keys (Start/Select/Option).
    • The fourth pin controls the speaker built into the Atari 400/800 to generate keyboard clicks. On later models there is no speaker, but the key click is still generated by GTIA and mixed with the regular audio output.
    • In the Atari 5200, the pins are used as part of the process to read the controller keyboards.

Versions

[edit]

by part number

Atari, Inc. intended to combine functions of the ANTIC and GTIA chips in one integrated circuit to reduce production costs of Atari computers and 5200 consoles. Two such prototype circuits were being developed, however none of them entered production.

Pinout

[edit]
Atari GTIA (C014805) pin-out
Pin Name Pin Number(s) Description
A0 - A4 2, 1, 40, 39, 38 Address Input
AN0 - AN2 18, 19, 20 ANTIC Interface Input
COL 21 Color Frequency Output
CS 32 Chip Select Input
CSYNC 25 Composite Sync Output
D0 - D7 7, 6, 5, 4, 37, 36, 35, 34 Data Bus I/O
DEL 17 Color Delay Line Input
FØ0 29 Fast Phase Clock Output
HALT 26 Halt Input
L0 - L3 31, 22, 23, 24 Luminance Output
N/C 16 Not Connected (PAL on later versions)
OSC 28 Oscillator Input
R/W 33 Read/Write Input
S0 - S3 12, 13, 14, 15 Switch Data I/O
T0 - T3 8, 9, 10, 11 Trigger Inputs with internal pull-up
Vcc 27 Power +5 Volts
Vss 3 Ground
Ø2 30 Computer Phase 2 Input

Registers

[edit]

The Atari 8-bit computers map CTIA/GTIA to the $D0xxhex page and the Atari 5200 console maps it to the $C0xxhex page.

CTIA/GTIA provides 54 Read/Write registers controlling Player/Missile graphics, Playfield colors, joystick triggers, and console keys. Many CTIA/GTIA register addresses have dual purposes performing different functions as a Read vs a Write register. Therefore, no code should read Hardware registers expecting to retrieve the previously written value.

This problem is solved for many write registers by Operating System Shadow registers implemented in regular RAM as places to store the last value written to registers. Operating System Shadow registers are copied from RAM to the hardware registers during the vertical blank. Therefore, any write to hardware registers which have corresponding shadow registers will be overwritten by the value of the Shadow registers during the next vertical blank.

Some Write registers do not have corresponding Shadow registers. They can be safely written by an application without the value being overwritten during the vertical blank. If the application needs to know the last state of the register then it is the responsibility of the application to remember what it wrote.

Operating System Shadow registers also exist for some Read registers where reading the value directly from hardware at an unknown stage in the display cycle may return inconsistent results.

Name Description Read/Write Hex Addr Dec Addr Shadow Name Shadow Hex Addr Shadow Dec Addr
HPOSP0 Horizontal Position of Player 0 Write $D000 53248
M0PF Missile 0 to Playfield collisions Read $D000 53248
HPOSP1 Horizontal Position of Player 1 Write $D001 53249
M1PF Missile 1 to Playfield collisions Read $D001 53249
HPOSP2 Horizontal Position of Player 2 Write $D002 53250
M2PF Missile 2 to Playfield collisions Read $D002 53250
HPOSP3 Horizontal Position of Player 3 Write $D003 53251
M3PF Missile 3 to Playfield collisions Read $D003 53251
HPOSM0 Horizontal Position of Missile 0 Write $D004 53252
P0PF Player 0 to Playfield collisions Read $D004 53252
HPOSM1 Horizontal Position of Missile 1 Write $D005 53253
P1PF Player 1 to Playfield collisions Read $D005 53253
HPOSM2 Horizontal Position of Missile 2 Write $D006 53254
P2PF Player 2 to Playfield collisions Read $D006 53254
HPOSM3 Horizontal Position of Missile 3 Write $D007 53255
P3PF Player 3 to Playfield collisions Read $D007 53255
SIZEP0 Size of Player 0 Write $D008 53256
M0PL Missile 0 to Player collisions Read $D008 53256
SIZEP1 Size of Player 1 Write $D009 53257
M1PL Missile 1 to Player collisions Read $D009 53257
SIZEP2 Size of Player 2 Write $D00A 53258
M2PL Missile 2 to Player collisions Read $D00A 53258
SIZEP3 Size of Player 3 Write $D00B 53259
M3PL Missile 3 to Player collisions Read $D00B 53259
SIZEM Size of all Missiles Write $D00C 53260
P0PL Player 0 to Player collisions Read $D00C 53260
GRAFP0 Graphics pattern for Player 0 Write $D00D 53261
P1PL Player 1 to Player collisions Read $D00D 53261
GRAFP1 Graphics pattern for Player 1 Write $D00E 53262
P2PL Player 2 to Player collisions Read $D00E 53262
GRAFP2 Graphics pattern for Player 2 Write $D00F 53263
P3PL Player 3 to Player collisions Read $D00F 53263
GRAFP3 Graphics pattern for Player 3 Write $D010 53264
TRIG0 Joystick 0 trigger. Read $D010 53264 STRIG0 $0284 644
GRAFM Graphics pattern for all Missiles Write $D011 53265
TRIG1 Joystick 1 trigger. Read $D011 53265 STRIG1 $0285 645
COLPM0 Color/luminance of Player and Missile 0. Write $D012 53266 PCOLOR0 $02C0 704
TRIG2 Joystick 2 trigger. Read $D012 53266 STRIG2 $0286 646
COLPM1 Color/luminance of Player and Missile 1. Write $D013 53267 PCOLOR1 $02C1 705
TRIG3 Joystick 3 trigger. Read $D013 53267 STRIG3 $0287 647
COLPM2 Color/luminance of Player and Missile 2. Write $D014 53268 PCOLOR2 $02C2 706
PAL PAL flags. Read $D014 53268
COLPM3 Color/luminance of Player and Missile 3. Write $D015 53269 PCOLOR3 $02C3 707
COLPF0 Color/luminance of Playfield 0. Write $D016 53270 COLOR0 $02C4 708
COLPF1 Color/luminance of Playfield 1. Write $D017 53271 COLOR1 $02C5 709
COLPF2 Color/luminance of Playfield 2. Write $D018 53272 COLOR2 $02C6 710
COLPF3 Color/luminance of Playfield 3. Write $D019 53273 COLOR3 $02C7 711
COLBK Color/luminance of Playfield background. Write $D01A 53274 COLOR4 $02C8 712
PRIOR Priority selection, fifth player, and GTIA modes Write $D01B 53275 GPRIOR $026F 623
VDELAY Vertical Delay P/M Graphics Write $D01C 53276
GRACTL Graphics Control. Write $D01D 53277
HITCLR Clear Collisions Write $D01E 53278
CONSPK Console Speaker Write $D01F 53279
CONSOL Console Keys Read $D01F 53279

In the individual register listings below the following legend applies:

Bit Value Description
0 Bit must be 0
1 Bit must be 1
? Bit may be either 0 or 1, and is used for a purpose.
- Bit is unused, or should not be expected to be a certain value
label Refer to a later explanation for the purpose of the bit.

Player/Missile Horizontal Coordinates

[edit]

These registers specify the horizontal position in color clocks of the left edge (the high bit of the GRAF* byte patterns) of Player/Missile objects. Coordinates are always based on the display hardware's color clock engine, NOT simply the current Playfield display mode. This also means Player/Missile objects can be moved into overscan areas beyond the current Playfield mode.

Note that while Missile objects bit patterns share the same byte for displayed pixels (GRAFM) each Missile can be independently positioned. When the "fifth Player" option is enabled (See PRIOR/GPRIOR register) turning the four Missiles into one "Player" the Missiles switch from displaying the color of the associated Player object to displaying the value of COLPF3. The new "Player's" position on screen must be set by specifying the position of each Missile individually.

Player/Missile pixels are only rendered within the visible portions of the GTIA's pixel engine. Player/Missile objects are not rendered during the horizontal blank or the vertical blank. However, an object can be partially within the horizontal blank. The objects' pixels that fall outside of the horizontal blank are then within the visible portion of the display and can still register collisions. The horizontal position range of visible color clocks is $22hex/34dec to $DDhex/221dec.

To remove a Player/Missile object from the visible display area horizontal positions (left) 0 and (right) $DEhex/222dec (or greater) will insure no pixels are rendered regardless of the size of the Player/Missile object and so no unintentional collisions can be flagged.

HPOSP0 $D000 Write

[edit]

Horizontal Position of Player 0

HPOSP1 $D001 Write

[edit]

Horizontal Position of Player 1

HPOSP2 $D002 Write

[edit]

Horizontal Position of Player 2

HPOSP3 $D003 Write

[edit]

Horizontal Position of Player 3

HPOSM0 $D004 Write

[edit]

Horizontal Position of Missile 0

HPOSM1 $D005 Write

[edit]

Horizontal Position of Missile 1

HPOSM2 $D006 Write

[edit]

Horizontal Position of Missile 2

HPOSM3 $D007 Write

[edit]

Horizontal Position of Missile 3

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
? ? ? ? ? ? ? ?

Below are the color clock coordinates of the left and right edges of the possible Playfield sizes, useful when aligning Player/Missile objects to Playfield components:

Playfield Width in displayed Color Clocks Left Edge First Color Clock Right Edge Last Color Clock
Narrow $80hex/128dec $40hex/64dec $BFhex/191dec
Normal $A0hex/160dec $30hex/48dec $CFhex/207dec
Wide $B0hex/176dec $28hex/40dec $D7hex/215dec

Player/Missile Size Control

[edit]

Three sizes can be chosen: Normal, Double, and Quad width. The left edge (See Horizontal Coordinates) is fixed and the size adjustment expands the Player or Missile toward the right in all cases.

  • Normal - 1 bit (pixel) is 1 color clock wide
  • Double - 1 bit (pixel) is 2 color clocks wide
  • Quad - 1 bit (pixel) is 4 color clocks wide

Note that in Quad size a single Player/Missile pixel is the same width as an Antic Mode 2 text character. Player/Missile priority selection mixed with Quad width Player Missile graphics can be used to create multiple text colors per Mode line.

Each Player has its own size control register:

SIZEP0 $D008 Write

[edit]

Size of Player 0

SIZEP1 $D009 Write

[edit]

Size of Player 1

SIZEP2 $D00A Write

[edit]

Size of Player 2

SIZEP3 $D00B Write

[edit]

Size of Player 3

Player size controls:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - - - Size 1 Size 0

Values:

Size Player Width Bits Value Size 1 Size 0
Normal 8 color clocks $00 0 0
Double 16 color clocks $01 0 1
Normal 8 color clocks $02 1 0
Quad 32 color clocks $03 1 1

SIZEM $D00C Write

[edit]

All Missile sizes are controlled by one register, but each Missile can be sized independently of the others. When the "fifth Player" option is enabled (See PRIOR/GPRIOR register) turning the four Missiles into one "Player" the width is still set by specifying the size for each Missile individually.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
M3 Size 1 M3 Size 0 M2 Size 1 M2 Size 0 M1 Size 1 M1 Size 0 M0 Size 1 M0 Size 0

Values:

Missile Size Missile Width Bits Value Size 1 Size 0
Missile 0 Normal 2 color clocks $00 0 0
Double 4 color clocks $01 0 1
Normal 2 color clocks $02 1 0
Quad 8 color clocks $03 1 1
Missile 1 Normal 2 color clocks $00 0 0
Double 4 color clocks $04 0 1
Normal 2 color clocks $08 1 0
Quad 8 color clocks $0C 1 1
Missile 2 Normal 2 color clocks $00 0 0
Double 4 color clocks $10 0 1
Normal 2 color clocks $20 1 0
Quad 8 color clocks $30 1 1
Missile 3 Normal 2 color clocks $00 0 0
Double 4 color clocks $40 0 1
Normal 2 color clocks $80 1 0
Quad 8 color clocks $C0 1 1

Player/Missile Graphics Patterns

[edit]

Each Player object has its own 8-bit pattern register. Missile objects share one register with 2 bits per each Missile. Once a value is set it will continue to be displayed on each scan line. With no other intervention by CPU or ANTIC DMA to update the values the result is vertical stripe patterns the height of the screen including overscan areas. This mode of operation does not incur a CPU or DMA toll on the computer. It is useful for displaying alternate colored borders and vertical lines separating screen regions.

GRAFP0 $D00D Write

[edit]

Graphics pattern for Player 0

GRAFP1 $D00E Write

[edit]

Graphics pattern for Player 1

GRAFP2 $D00F Write

[edit]

Graphics pattern for Player 2

GRAFP3 $D010 Write

[edit]

Graphics pattern for Player 3

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pixel HPOS+0 Pixel HPOS+1 Pixel HPOS+2 Pixel HPOS+3 Pixel HPOS+4 Pixel HPOS+5 Pixel HPOS+6 Pixel HPOS+7

Each Player is 8 bits (pixels) wide. Where a bit is set, a pixel is displayed in the color assigned to the color register associated to the Player. Where a bit is not set the Player object is transparent, showing Players, Missiles, Playfield pixels, or the background color. Pixel output begins at the horizontal position specified by the Player's HPOS value with the highest bit output first.

GRAFM $D011 Write

[edit]

Graphics pattern for all Missiles

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
M3 Pixel HPOS+0 M3 Pixel HPOS+1 M2 Pixel HPOS+0 M2 Pixel HPOS+1 M1 Pixel HPOS+0 M1 Pixel HPOS+1 M0 Pixel HPOS+0 M0 Pixel HPOS+1

Each Missile is 2 bits (pixels) wide. Where a bit is set, a pixel is displayed in the color assigned to the color register for the Player associated to the Missile. When Fifth Player is enabled (see PRIOR/GPRIOR) the Missiles pixels all display COLPF3. Where a bit is not set the Missile object is transparent, showing Players, Missiles, Playfield pixels, or the background color. Pixel output begins at the horizontal position specified by the Missile's HPOS value with the highest bit output first.

Missile Values:

Missile Bits Value Pixel 1 Pixel 0
Missile 0 $00 0 0
$01 0 1
$02 1 0
$03 1 1
Missile 1 $00 0 0
$04 0 1
$08 1 0
$0C 1 1
Missile 2 $00 0 0
$10 0 1
$20 1 0
$30 1 1
Missile 3 $00 0 0
$40 0 1
$80 1 0
$C0 1 1

Player/Missile Collisions

[edit]

CTIA/GTIA has 60 bits providing automatic detection of collisions when Player, Missile, and Playfield pixels intersect. A single bit indicates a non-zero pixel of the Player/Missile object has intersected a pixel of a specific color register. There is no collision registered for pixels rendered using the background color register/value. This system provides instant, pixel-perfect overlap comparison without expensive CPU evaluation of bounding box or image bitmap masking.

The actual color value of an object is not considered. If Player, Missile, Playfield, and Background color registers are all the same value making the objects effectively "invisible", the intersections of objects will still register collisions. This is useful for making hidden or secret objects and walls.

Obscured intersections will also register collisions. If a Player object priority is behind a Playfield color register and another Player object priority is higher (foreground) than the Playfield, and the foreground Player pixels obscure both the Playfield and the Player object behind the Playfield, then the collision between the Playfield and both the background and foreground Player objects will register along with the collision between the foreground and background Player objects.

Note that there is no Missile to Missile collision.

Player/Missile collisions can only occur when Player/Missile object pixels occur within the visible portions of the display. Player/Missile objects are not rendered during the horizontal blank or the vertical blank. The range of visible color clocks is 34 to 221, and the visible scan lines range from line 8 through line 247. Player/Missile data outside of these coordinates are not rendered and will not register collisions. An object can be partially within the horizontal blank. The objects' pixels that fall outside of the horizontal blank are within the visible portion of the display and can still register collisions.

To remove a Player/Missile object from the visible display area horizontal positions (left) 0 and (right) 222 (or greater) will insure no pixels are rendered regardless of the size of the Player/Missile object and so no unintentional collisions can be flagged.

Finally, Player, Missile, and Playfield objects collision detection is real-time, registering a collision as the image pixels are merged and output for display. Checking an object's collision bits before the object has been rendered by CTIA/GTIA will show no collision.

Once set, collisions remain in effect until cleared by writing to the HITCLR register. Effective collision response routines should occur after the targeted objects have been displayed, or at the end of a frame or during the vertical blank to react to the collisions and clear collisions before the next frame begins.

Because collisions are only a single bit, collisions are quite obviously not additive. No matter how many times and different locations a collision between pixels occurs within one frame there is only 1 bit to indicate there was a collision. A set collision bit informs a program that it can examine the related objects to identify collision locations and then decide how to react for each location.

Since HITCLR and collision detection is real-time, Display List Interrupts can divide the display into sections with HITCLR used at the beginning of each section and separate collision evaluation at the end of each section.

When the "fifth Player" option is enabled (See PRIOR/GPRIOR register) the only change is the Missiles 0 to 3 switch from displaying the color of the associated Player object to displaying the value of COLPF3. The new "Player's" collisions are still reported for the individual Missiles.

Player/Missile to Playfield Collisions

[edit]

Each bit indicates a pixel of the Player/Missile object has intersected a pixel of the specified Playfield color object. There is no collision registered for the background color.

Obscured intersections will also register collisions. If a Player/Missile object priority is behind a Playfield color register and another Player/Missile object priority is higher (foreground) than the Playfield, and the foreground Player/Missile pixels obscure both the Playfield and the Player/Missile object behind the Playfield, then the collision between the Playfield and both the background and foreground Player/Missile objects will register.

High-resolution, 1/2 color clock pixel modes (ANTIC Modes 2, 3, and F) are treated differently. The "background" color rendered as COLPF2 where pixel values are 0 does not register a collision. High-resolution pixels are rendered as the luminance value from COLPF1. The pixels are grouped together in color clock-wide pairs (pixels 0 and 1, pixels 2 and 3, continuing to pixels 318 and 319). Where either pixel of the pair is 1 a collision is detected between the Player or Missile pixels and Playfield color COLPF2.

GTIA modes 9 and 11 do not process playfield collisions. In GTIA mode 10 Playfield collisions will register where Playfield pixels use COLPF0 through COLPF3

M0PF $D000 Read
[edit]

Missile 0 to Playfield collisions

M1PF $D001 Read
[edit]

Missile 1 to Playfield collisions

M2PF $D002 Read
[edit]

Missile 2 to Playfield collisions

M3PF $D003 Read
[edit]

Missile 3 to Playfield collisions

P0PF $D004 Read
[edit]

Player 0 to Playfield collisions

P1PF $D005 Read
[edit]

Player 1 to Playfield collisions

P2PF $D006 Read
[edit]

Player 2 to Playfield collisions

P3PF $D007 Read
[edit]

Player 3 to Playfield collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - COLPF3 COLPF2 COLPF1 COLPF0

Missile to Player Collisions

[edit]

Missiles collide with Players and Playfields. There is no Missile to Missile collision.

M0PL $D008 Read
[edit]

Missile 0 to Player collisions

M1PL $D009 Read
[edit]

Missile 1 to Player collisions

M2PL $D00A Read
[edit]

Missile 2 to Player collisions

M3PL $D00B Read
[edit]

Missile 3 to Player collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - COLPM3 COLPM2 COLPM1 COLPM0

Player to Player Collisions

[edit]

A collision between two players sets the collision bit in both Players' collision registers. When Player 0 and Player 1 collide, Player 0's collision bit for Player 1 is set, and Player 1's collision bit for Player 0 is set.

A Player cannot collide with itself, so its bit is always 0.

P0PL $D00C Read
[edit]

Player 0 to Player collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - COLPM3 COLPM2 COLPM1 0
P1PL $D00D Read
[edit]

Player 1 to Player collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - COLPM3 COLPM2 0 COLPM0
P2PL $D00E Read
[edit]

Player 2 to Player collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - COLPM3 0 COLPM1 COLPM0
P3PL $D00F Read
[edit]

Player 3 to Player collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - 0 COLPM2 COLPM1 COLPM0

Player/Missile and Playfield Color and Luminance

[edit]

All Player/Missile objects' pixels and all Playfield pixels in the default CTIA/GTIA color interpretation mode use indirection to specify color. Indirection means that the values of the pixel data do not directly specify the color, but point to another source of information for color. CTIA/GTIA contain hardware registers that set the values used for colors, and the pixels' information refer to these registers. The palette on the Atari is 8 luminance levels of 16 colors for a total 128 colors. The color indirection flexibility allows a program to tailor the screen's colors to fit the purpose of the program's display.

All hardware color registers have corresponding shadow registers.

COLPM0 $D012 Write

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SHADOW: PCOLOR0 $02C0

Color/luminance of Player and Missile 0.

When GTIA 9-color mode is enabled (PRIOR/GPRIOR value $80) this register is used for the border and background (Playfield pixel value 0), rather than COLBK.

COLPM1 $D013 Write

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SHADOW: PCOLOR1 $02C1

Color/luminance of Player and Missile 1.

COLPM2 $D014 Write

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SHADOW: PCOLOR2 $02C2

Color/luminance of Player and Missile 2.

COLPM3 $D015 Write

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SHADOW: PCOLOR3 $02C3

Color/luminance of Player and Missile 3.

COLPF0 $D016 Write

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SHADOW: COLOR0 $02C4

Color/luminance of Playfield 0.

COLPF1 $D017 Write

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SHADOW: COLOR1 $02C5

Color/luminance of Playfield 1.

This register is used for the set pixels (value 1) in ANTIC text modes 2 and 3, and map mode F. Only the luminance portion is used and is OR'd with the color value of COLPF2. In other Character and Map modes this register provides the expected color and luminance for a pixel.

COLPF2 $D018 Write

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SHADOW: COLOR2 $02C6

Color/luminance of Playfield 2.

This register is used for Playfield background color of ANTIC text modes 2 and 3, and map mode F. That is, where pixel value 0 is used. In other Character and Map modes this register provides the expected color and luminance for a pixel.

COLPF3 $D019 Write

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SHADOW: COLOR3 $02C7

Color/luminance of Playfield 3

COLPF3 is available is several special circumstances:

  • When Missiles are converted to the "fifth Player" they switch from displaying the color of the associated Player object to displaying COLPF3 and change priority. See PRIOR/GPRIOR register.
  • Playfield Text Modes 4 and 5. Inverse video characters (high bit $80 set) cause CTIA/GTIA to substitute COLPF3 value for COLPF2 pixels in the character matrix. (See ANTIC's Glyph Rendering)
  • Playfield Text Modes 6 and 7. When the character value has bits 6 and 7 set (character range $C0-FF) the entire character pixel matrix is displayed in COLPF3. (See ANTIC's Glyph Rendering)
  • This register is also available in GTIA's special 9 color, pixel indirection color mode.

COLBK $D01A Write

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SHADOW: COLOR4 $02C8

Color/luminance of Playfield background.

The background color is displayed where no other pixel occurs through the entire overscan display area. The following exceptions occur for the background:

  • In ANTIC text modes 2 and 3, and map mode F the background of the playfield area where pixels may be rendered is from COLPF2 and the COLBK color appears as a border around the playfield.
  • In GTIA color interpretation mode $8 (9 color indirection) the display background color is provided by color register COLPM0 while COLBAK is used for Playfield pixel value $8.
  • In GTIA color interpretation mode $C (15 colors in one luminance level, plus background) uses COLBK to set the luminance level of all other pixels (pixel value $1 through $F). However, the background itself uses only the color component set in the COLBK register. The luminance value of the background is forced to 0.

Color Registers' Bits:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Color 3 Color 2 Color 1 Color 0 Luminance 3 Luminance 2 Luminance 1 (Luminance 0)

The high nybble of the color register specifies one of 16 colors color ($00, $10, $20... to $F0).

The low nybble of the register specifies one of 16 luminance values ($00, $01, $02... to $0F).

In the normal color interpretation mode the lowest bit is not significant and only 8 luminance values are available ($00, $02, $04, $06, $08, $0A, $0C, $0E), so the complete color palette is 128 color values.

In GTIA color interpretation mode $4 (luminance-only mode) the full 16 bits of luminance values are available for Playfield pixels providing a palette of 256 colors. Any Player/Missile objects displayed in this mode are colored by indirection which still uses the 128 color palette.

In normal color interpretation mode the pixel values range from $0 to $3 ordinarily pointing to color registers COLBK, COLPF0, COLPF1, COLPF2 respectively. The color text modes also include options to use COLPF3 for certain ranges of character values. See ANTIC's graphics modes for more information.

When Player/Missile graphics patterns are enabled for display where the graphics patterns bits are set the color displayed comes from the registers assigned to the objects.

There are exceptions for color generation and display:

  • ANTIC Text modes 2 and 3, and Map mode F:
    • The pixel values in these modes is only $0 and $1. The $0 pixels specify the Playfield background which is color register COLPF2. The $1 pixels use the color component of COLPF2, and the luminance specified by COLPF1. The border around the Playfield uses the color from COLBK.
    • ANTIC Text modes 2 and 3, and Map mode F behave differently with Player/Missile graphics from the other modes. COLPF1 used for the glyph or graphics pixels always has the highest priority and cannot be obscured by Players or Missiles. The color of COLPF1 always comes from the "background" which is ordinarily COLPF2. Therefore, where Players/Missiles and Fifth Player have priority over COLPF2 the COLPF1 glyph/graphics pixels use the color component of the highest priority color (Player or Missile), and the luminance component of COLPF1. This behavior is consistent where Player/Missile priority conflicts result in true black for the "background". In summary, the color CTIA/GTIA finally determines to use "behind" the high-res pixel is then used to "tint" the COLPF1 foreground glyph/graphics pixels.
  • GTIA Exceptions
    • GTIA color interpretation mode $8 (9 color indirection) uses color register COLPM0 for the display background and border color while COLBAK is used for Playfield pixel value $8.
    • GTIA color interpretation mode $C (15 colors in one luminance level, plus background) uses COLBK to set the luminance level of all other pixels (pixel value $1 through $F). However, the background itself uses only the color component set in the COLBK register. The luminance value of the background is forced to 0. Note that the background's color component is also OR'd with the other pixels' colors. Therefore, the overall number of colors in the mode is reduced when the background color component is not black (numerically zero).
  • Player/Missile Exceptions:
    • Player/Missile Priority value $0 (See PRIOR/GPRIOR) will cause overlapping Player and Playfield pixels to be OR'd together displaying a different color.
    • Conflicting Player/Missile Priority configuration will cause true black (color 0, luma 0) to be output where conflicts occur.
    • The Player/Missile Multi-Color option will cause overlapping Player pixels to be OR'd together displaying a different color.

Color Registers' Use per ANTIC Character Modes:

Register ANTIC 2 ANTIC 3 ANTIC 4 ANTIC 5 ANTIC 6 ANTIC 7
COLPM0/PCOLOR0
COLPM1/PCOLOR1
COLPM2/PCOLOR2
COLPM3/PCOLOR3
COLPF0/COLOR0 glyph pixel glyph pixel glyph glyph
COLPF1/COLOR1 glyph pixel (luma) glyph pixel (luma) glyph pixel glyph pixel glyph glyph
COLPF2/COLOR2 background background glyph pixel glyph pixel glyph glyph
COLPF3/COLOR3 glyph pixel glyph pixel glyph glyph
COLBAK/COLOR4 border border background background background background

Color Registers' Use per ANTIC Map Modes:

Register ANTIC 0 (blank lines) ANTIC 8 ANTIC 9 ANTIC A ANTIC B ANTIC C ANTIC D ANTIC E ANTIC F
COLPM0/PCOLOR0
COLPM1/PCOLOR1
COLPM2/PCOLOR2
COLPM3/PCOLOR3
COLPF0/COLOR0 pixel pixel pixel pixel pixel pixel pixel
COLPF1/COLOR1 pixel pixel pixel pixel pixel (luma)
COLPF2/COLOR2 pixel pixel pixel pixel background
COLPF3/COLOR3
COLBAK/COLOR4 background background background background background background background background border

Color Registers' Use per GTIA Modes (ANTIC F):

Register GTIA $4 (BASIC 9) GTIA $8 (BASIC 10) GTIA $C (BASIC 11)
COLPM0/PCOLOR0 background
COLPM1/PCOLOR1 pixel
COLPM2/PCOLOR2 pixel
COLPM3/PCOLOR3 pixel
COLPF0/COLOR0 pixel
COLPF1/COLOR1 pixel
COLPF2/COLOR2 pixel
COLPF3/COLOR3 pixel
COLBAK/COLOR4 background base color pixel background base luma

Player/Missile colors are always available for Player/Missile objects in all modes, though colors may be modified when the special GTIA modes (16 shades/16 color) are in effect.

Miscellaneous Player/Missile and GTIA Controls

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PRIOR $D01B Write

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SHADOW: GPRIOR $026F

This register controls several CTIA/GTIA color management features: The GTIA Playfield color interpretation mode, Multi-Color Player objects, the Fifth Player, and Player/Missile/Playfield priority.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GTIA Mode 1 GTIA Mode 0 Multi-Color Player Fifth Player Priority 3 Priority 2 Priority 1 Priority 0
GTIA Playfield Color Interpretations
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CTIA includes only one default color interpretation mode for the ANTIC Playfield data stream. That is the basic functionality assumed in the majority of the ANTIC and CTIA/GTIA discussion unless otherwise noted. GTIA includes three alternate color interpretations modes for Playfield data. These modes work by pairing adjacent color clocks from ANTIC, thus the pixels output by GTIA are always two color clocks wide. Although these modes can be engaged while displaying any ANTIC Playfield Mode, the full color palette possible with these GTIA color processing options are only realized in the ANTIC Modes based on 12 color clock pixels (ANTIC modes 2, 3, F.) These GTIA options are most often used with a Mode F display. The special GTIA color processing modes also alter the display or behavior of Player/Missile graphics in various ways.

The color interpretation control is a global function of GTIA affecting the entire screen. GTIA is not inherently capable of mixing on one display the various GTIA color interpretation modes and the default CTIA mode needed for most ANTIC Playfields. Mixing color interpretation modes requires software writing to the PRIOR register as the display is generated (usually, by a Display List Interrupt).

PRIOR bits 7 and 6 provide four values specifying the color interpretation modes:

GTIA Mode Bits [7:6] Feature Description
0 0 = $00 Default Same as CTIA. Normal color register usage.
0 1 = $40 GTIA/16 Shades 16 shades of background color ( COLBK )
1 0 = $80 GTIA/9 color All nine Playfield and Player/Missile color registers are available on the Playfield. The background is COLPM0
1 1 = $C0 GTIA/16 Color 15 colors at one luminance level set by the background register (COLBK), plus the background.
16 Shades
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This mode uses the COLBK register to specify the background color. Rather than using indirection, pixel values directly represent Luminance. This mode allows all four luminance bits to be used in the Atari color palette and so is capable of displaying 256 colors.

Player/Missile graphics (without the fifth Player option) display properly in this mode, however collision detection with the Playfield is disabled. Playfield priority is always on the bottom. When the Missiles are switched to act as a fifth Player then where the Missile objects overlap the Playfield the Missile pixels luminance merges with the Playfield pixels' Luminance value.

9 Color
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Unlike the other two special GTIA modes, this mode is entirely driven by color indirection. All nine color registers work on the display for pixel values 0 through 8. The remaining 7 pixel values repeat previous color registers.

The pixels are delayed by one color clock (half a GTIA mode pixel) when output. This offset permits interesting effects. For an example, page flipping rapidly between this mode and a different GTIA mode produces a display with apparent higher resolution and greater number of colors.

This mode is unique in that is uses color register COLPM0 for the border and background (Playfield 0 value pixels) rather than COLBK.

Player/Missile graphics display properly with the exception that Player/Missile 0 are not distinguishable from the background pixels, since they use the same color register, COLPM0. The Playfield pixels using the Player/Missile colors are modified by priority settings as if they were Player/Missile objects and so can affect the display of Players/Missiles. (See discussion later about Player/Missile/Playfield priorities).

The Playfield pixels using Player/Missile colors do not trigger collisions when Player/Missile objects overlay them. However, Player/Missile graphics overlapping Playfield colors COLPF0 to COLPF3 will trigger the expected collision.

16 Colors
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This mode uses the COLBK register to specify the luminance of all Playfield pixels (values 1hex/1dec through Fhex/15dec.) The least significant bit of the luminance value is not observed, so only the standard/CTIA 8 luminance values are available ($0, $2, $4, $6, $8, $A, $C, $E). Additionally, the background itself uses only the color component set in the COLBK register. The luminance value of the background is forced to 0. As with the Luminance mode indirection is disabled and pixel values directly represent a color.

Note that the color component of the background also merges with the playfield pixels. Colors other than black for the background reduce the overall number of colors displayed in the mode.

Player/Missile graphics (without the fifth Player option) display properly in this mode, however collision detection with the Playfield is disabled. Playfield priority is always on the bottom. When the Missiles are switched to act as a fifth Player then where the Missile objects overlap the Playfield the Missile pixels inherit the Playfield pixels' Color value.

Multi-Color Player
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PRIOR bit 5, value 20hex/32dec enables Multi-Color Player objects. Where pixels of two Player/Missile objects overlap a third color appears. This is implemented by eliminating priority processing between pairs of Player/Missile objects resulting in CTIA/GTIA performing a bitwise OR of the two colored pixels to output a new color.

Example: A Player pixel with color value 98hex/152dec (blue) overlaps a Player pixel with color value 46hex/70dec (red) resulting in a pixel color of DEhex/228dec (light green/yellow).

The Players/Missiles pairs capable of Multi-Color output:

  • Player 0 + Player 1
  • Missile 0 + Missile 1
  • Player 2 + Player 3
  • Missile 2 + Missile 3
Fifth Player
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PRIOR bit 4, value $10hex/16dec enables Missiles to become a fifth Player. No functional change occurs to the Missile other than the color processing of the Missiles. Normally the Missiles display using the color of the associated Player. When Fifth Player is enabled all Missiles display the color of Playfield 3 (COLPF3). Horizontal position, size, vertical delay, and Player/Missile collisions all continue to operate the same way. The priority of the Fifth Player for Player objects pixel intersections is COLPF3, but the Fifth Player's pixels have priority over all Playfield colors.

The color processing change also causes some exceptions for the Missiles' display in GTIA's alternative color modes:

  • GTIA 16 Shades mode: Where Missile pixels overlap the Playfield the pixels inherit the Playfield pixels' Luminance value.
  • GTIA 16 Colors mode: Where Missile pixels overlap the Playfield the pixels inherit the Playfield pixels' Color value.

The Fifth Player introduces an exception for Priority value $8 (bits 1000) (See Priority discussion below.)

Priority
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PRIOR bits 3 to 0 provide four Player/Missile and Playfield priority values that determine which pixel value is displayed when Player/Missile objects pixels and Playfield pixels intersect. The four values provide specific options listed in the Priority chart below. "PM" mean normal Player/Missile implementation without the Fifth Player. The Fifth Player, "P5", is shown where its priority occurs when it is enabled.

The chart is accurate for ANTIC Playfield Character and Map modes using the default (CTIA) color interpretation mode. GTIA color interpretation modes, and the ANTIC modes based on high-resolution, 12 color clock pixels behave differently (noted later).

Priority Bits [3:0] 0 0 0 1 = $1 0 0 1 0 = $2 0 1 0 0 = $4 1 0 0 0 = $8 0 0 0 0 = $0
Top PM0 PM0 P5/PF0 P5/PF0 PM0
PM1 PM1 PF1 PF1 PM1
PM2 P5/PF0 PF2 PM0 P5/PF0
PM3 PF1 PF3 PM1 PF1
P5/PF0 PF2 PM0 PM2 PM2
PF1 PF3 PM1 PM3 PM3
PF2 PM2 PM2 PF2 PF2
PF3 PM3 PM3 PF3 PF3
Bottom COLBK COLBK COLBK COLBK COLBK

If multiple bits are set, then where there is a conflict CTIA/GTIA outputs a black pixel—Note that black means actual black, not simply the background color, COLBK.

Although the Fifth Player is displayed with the value of COLPF3, its priority is above all Playfield colors. This produces an exception for Priority value $8 (Bits 1000). In this mode Playfield 0 and 1 are higher priority than the Players, and the Players are higher priority than Playfield 2 and 3. Where Playfield 0 or 1 pixels intersect any Player pixel the result displayed is the Playfield pixel. However, if the Fifth player also intersects the same location, its value is shown over the Playfield causing it to appear as if Playfield 3 has the highest priority. If the Playfield 0 or 1 pixel is removed from this intersection then the Fifth Player's pixel has no Playfield pixel to override and so also falls behind the Player pixels.

When the Priority bits are all 0 a different effect occurs—Player and Playfield pixels are logically OR'd together in the a manner similar to the Multi-Color Player feature. In this situation Players 0 and 1 pixels can mix with Playfield 0 and 1 pixels, and Players 2 and 3 pixels can mix with Playfield 2 and 3 pixels. Additionally, when the Multi-Color Player option is used the resulting merged Players' color can also mix with the Playfield producing more colors. When all color merging possibilities are considered, the CTIA/GTIA hardware can output 23 colors per scan line. Starting with the background color as the first color, the remaining 22 colors and color merges are possible:

Color COLPM0 COLPM1 COLPF0 COLPF1 Color COLPM2 COLPM3 COLPF2 COLPF3
1 X 12 X
2 X 13 X
3 X X 14 X X
4 X 15 X
5 X X 16 X X
6 X X 17 X X
7 X X X 18 X X X
8 X 19 X
9 X X 20 X X
10 X X 21 X X
11 X X X 22 X X X

When Priority bits are all 0 the Missiles colors function the same way as the corresponding Players as described above. When Fifth Player is enabled, the Missile pixels cause the same color merging as shown for COLPF3 in the table above (colors 19 through 22).

Priority And High-Resolution Modes
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The priority result differ for the Character and Map modes using high-resolution, 12 color clock pixels—ANTIC modes 2, 3, and F. These priority handling differences can be exploited to produce color text or graphics in these modes that are traditionally thought of as "monochrome".

In these ANTIC modes COLPF2 is output as the "background" of the Playfield and COLBK is output as the border around the Playfield. The graphics or glyph pixels are output using only the luminance component of COLPF1 mixed with the color component of the background (usually COLPF2).

The priority relationship between Players/Missiles, and COLPF2 work according to the priority chart below. Player/Missile pixels with higher priorities will replace COLPF2 as the "background" color. COLPF1 always has the highest priority and cannot be obscured by Players or Missiles. The glyph/graphics pixels use the color component of highest priority color (Playfield, Player, or Missile), and the luminance component of COLPF1. Note that this behavior is also consistent where Player/Missile priority conflicts result in true black for the "background". In effect, the color value CTIA/GTIA finally uses for the "background" color "tints" the COLPF1 foreground glyph/graphics pixels.

Priority Bits [3:0] COLPF2 vs COLPM0 and COLPM1 COLPF2 vs COLPM2 and COLPM3
0 0 0 0 = $00 Player/Missile Player/Missile OR'd with COLPF2
0 0 0 1 = $01 Player/Missile Player/Missile
0 0 1 0 = $02 Player/Missile COLPF2
0 0 1 1 = $03 Player/Missile True Black
0 1 0 0 = $04 COLPF2 COLPF2
0 1 0 1 = $05 COLPF2 True Black
0 1 1 0 = $06 COLPF2 COLPF2
0 1 1 1 = $07 COLPF2 True Black
1 0 0 0 = $08 Player/Missile Player/Missile
1 0 0 1 = $09 Player/Missile Player/Missile
1 0 1 0 = $0A Player/Missile True Black
1 0 1 1 = $0B Player/Missile True Black
1 1 0 0 = $0C COLPF2 True Black
1 1 0 1 = $0D COLPF2 True Black
1 1 1 0 = $0E COLPF2 True Black
1 1 1 1 = $0F COLPF2 True Black

VDELAY $D01C Write

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Vertical Delay P/M Graphics

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Player 3 Player 2 Player 1 Player 0 Missile 3 Missile 2 Missile 1 Missile 0

This register is used to provide single scan line movement when Double Line Player/Missile resolution is enabled in ANTIC's DMACTL register. This works by masking ANTIC DMA updates to the GRAF* registers on even scan lines, causing the graphics pattern to shift down one scan line.

Since Single Line resolution requires ANTIC DMA updates on each scan line and VDELAY masks the updates on even scan lines, then this bit reduces Single line Player/Missile resolution to Double line.

GRACTL $D01D Write

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Graphics Control

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
? ? ? ? ? Trigger Latch Enable Players Enable Missiles

GRACTL controls CTIA/GTIA's receipt of Player/Missile DMA data from ANTIC and toggles the mode of Joystick trigger input.

Receipt of Player/Missile DMA data requires CTIA/GTIA be configured to receive the data. This is done with a pair of bits in GRACTL that match a pair of bits in ANTIC's DMACTL register that direct ANTIC to send Player data and Missile data. GRACTL's Bit 0 corresponds to DMACTL's Bit 2, enabling transfer of Missile data. GRACTL's Bit 1 corresponds to DMACTL's Bit 3, enabling transfer of Player data. These bits must be set for GTIA to receive Player/Missile data from ANTIC via DMA. When Player/Missile graphics are being operated directly by the CPU then these bits must be off.

The joystick trigger registers report the pressed/not pressed state in real-time. If a program's input polling may not be frequent enough to catch momentary joystick button presses, then the triggers can be set to lock in the closed/pressed state and remain in that state even after the button is released. Setting GRACTL Bit 2 enables the latching of all triggers. Clearing the bit returns the triggers to the unlatched, real-time behavior.

HITCLR $D01E Write

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Clear Collisions

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
? ? ? ? ? ? ? ?

Any write to this register clears all the Player/Missile collision detection bits.

Other CTIA/GTIA Functions

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Joystick Triggers

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TRIG0 $D010 Read
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SHADOW: STRIG0 $0284

Joystick 0 trigger

TRIG1 $D011 Read
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SHADOW: STRIG1 $0285

Joystick 1 trigger.

TRIG2 $D012 Read
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SHADOW: STRIG2 $0286

Joystick 2 trigger.

TRIG3 $D013 Read
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SHADOW: STRIG3 $0287

Joystick 3 trigger

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Trigger
0 0 0 0 0 0 0 ?

Bits 7 through 1 are always 0. Bit 0 reports the state of the joystick trigger. Value 1 indicates the trigger is not pressed. Value 0 indicates the trigger is pressed.

The trigger registers report button presses in real-time. The button pressed state will instantly clear when the button is released.

The triggers may be configured to latch, that is, lock, in the pressed state and remain that way until specifically cleared. GRACTL bit 2 enables the latch behavior for all triggers. Clearing GRACTL bit 2 returns all triggers to real-time behavior.

PAL $D014 Read

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PAL flags.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - Video 3 Video 2 Video 1 Video 0

This register reports the display standard for the system. When Bits 3 to 0 are set to 1 (value $fhex/15dec) the system is operating in NTSC. When the bits are zero the system is operating in PAL mode.

CONSPK $D01F Write

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Console Speaker

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 Speaker - - -

Bit3 controls the internal speaker of the Atari 800/400. In later models the console speaker is removed and the sound is mixed with the regular POKEY audio signals for output to the monitor port and RF adapter. The Atari OS uses the console speaker to output the keyboard click and the bell/buzzer sound.

The Operating System sets the speaker bit during the vertical blank routine. Repeatedly writing 0 to the bit will produce a 60 Hz buzzing sound as the vertical blank resets the value. Useful tones can be generated using 6502 code effectively adding a fifth audio channel, albeit a channel requiring CPU time to maintain the audio tones.

CONSOL $D01F Read

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Console Keys

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
- - - - - Option Select Start

A bit is assigned to report the state of each of the special console keys, Start, Select, and Option. Bit value 0 indicates a key is pressed and 1 indicates the key is not pressed. Key/Bit values:

  • Start Key = Bit value $1
  • Select Key = Bit value $2
  • Option Key = Bit value $4

Player/Missile Graphics (sprites) operation

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A hardware "sprite" system is handled by CTIA/GTIA. The official ATARI name for the sprite system is "Player/Missile Graphics", since it was designed to reduce the need to manipulate display memory for fast-moving objects, such as the "player" and his weapons, "missiles", in a shoot 'em up game.

A Player is essentially a glyph 8 pixels wide and 256 TV lines tall, and has two colors: the background (transparent) (0 in the glyph) and the foreground (1). A Missile object is similar, but only 2 pixels wide. CTIA/GTIA combines the Player/Missile objects' pixels with the Playfield pixels according to their priority. Transparent (0) player pixels have no effect on the Playfield and display either a Playfield or background pixel without change. All Player/Missile objects' normal pixel width is one color clock. A register value can set the Player or Missile pixels' width to 1, 2, or 4 color clocks wide.

The Player/Missile implementation by CTIA/GTIA is similar to the TIA's. A Player is an 8-bit value or pattern at a specified horizontal position which automatically repeats for each scan line or until the pattern is changed in the register. Missiles are 2-bits wide and share one pattern register, so that four, 2-bit wide values occupy the 8-bit wide pattern register, but each missile has an independent horizontal position and size. Player/Missile objects extend the height of the display including the screen border. That is, the default implementation of Player/Missile graphics by CTIA/GTIA is a stripe down the screen. While seemingly limited this method facilitates Player/Missile graphics use as alternate colored vertical borders or separators on a display, and when priority values are set to put Player/Missile pixels behind playfield pixels they can be used to add additional colors to a display. All Players and Missiles set at maximum width and placed side by side can cover the entire normal width Playfield.

CTIA/GTIA supports several options controlling Player/Missile color. The PRIOR/GPRIOR register value can switch the four Missiles between two color display options—each Missile (0 to 3) expresses the color of the associated Player object (0 to 3) or all Missiles show the color of register COLPF3/COLOR3. When Missiles are similarly colored they can be treated as a fifth player, but correct placement on screen still requires storing values in all four Missile Horizontal Position registers. PRIOR/GPRIOR also controls a feature that causes the overlapping pixels of two Players to generate a third color allowing multi-colored Player objects at the expense of reducing the number of available objects. Finally, PRIOR/GPRIOR can be used to change the foreground/background layering (called, "priority") of Player/Missile pixels vs Playfield pixels, and can create priority conflicts that predictably affect the colors displayed.

The conventional idea of a sprite with an image/pattern that varies vertically is also built into the Player/Missile graphics system. The ANTIC chip includes a feature to perform DMA to automatically feed new pixel patterns to CTIA/GTIA as the display is generated. This can be done for each scan line or every other scan line resulting in Player/Missile pixels one or two scan lines tall. In this way the Player/Missile object could be considered an extremely tall character in a font, 8 bits/pixels wide, by the height of the display.

Moving the Player/Missile objects horizontally is as simple as changing a register in the CTIA/GTIA (in Atari BASIC, a single POKE statement moves a player or missile horizontally). Moving an object vertically is achieved by either block moving the definition of the glyph to a new location in the Player or Missile bitmap, or by rotating the entire Player/Missile bitmap (128 or 256 bytes). The worst case rotation of the entire bitmap is still quite fast in 6502 machine language, even though the 6502 lacks a block-move instruction found in the 8080. Since the sprite is exactly 128 or 256 bytes long, the indexing can be easily accommodated in a byte-wide register on the 6502. Atari BASIC lacks a high speed memory movement command and moving memory using BASIC PEEK()s and POKE(s) is painfully slow. Atari BASIC programs using Player/Missile graphics have other options for performing high speed memory moves. One method is calling a short machine language routine via the USR() function to perform the memory moves. Another option is utilizing a large string as the Player/Missile memory map and performing string copy commands which result in memory movement at machine language speed.

Careful use of Player/Missile graphics with the other graphics features of the Atari hardware can make graphics programming, particularly games, significantly simpler.

GTIA enhancements

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The GTIA chip is backward compatible with the CTIA, and adds 3 color interpretations for the 14 "normal" ANTIC Playfield graphics modes. The normal color interpretation of the CTIA chip is limited, per scanline, to a maximum of 4 colors in Map modes or 5 colors in Text modes (plus 4 colors for Player/Missile graphics) unless special programming techniques are used. The three, new color interpretations in GTIA provide a theoretical total of 56 graphics modes (14 ANTIC modes multiplied by four possible color interpretations). However, only the graphics modes based on high-resolution, 12 color clock pixels (that is, Antic text modes 2, 3, and graphics mode F) are capable of fully expressing the color palettes of these 3 new color interpretations. The three additional color interpretations use the information in two color clocks (four bits) to generate a pixel in one of 16 color values. This changes a mode F display from 2 colors per pixel, 320 pixels horizontally, one scan line per mode line, to 16 colors and 80 pixels horizontally. The additional color interpretations allow the following:

  • GTIA color interpretation mode $4 — 16 shades of a single hue (set by the background color, COLBK) from the 16 possible hues in the Atari palette. This is also accessible in Atari BASIC as Graphics 9.
  • GTIA color interpretation mode $8 — This mode allows 9 colors of indirection per horizontal line in any hue and luminance from the entire Atari palette of 128 colors. This is accomplished using all the Player/Missile and Playfield color registers for the Playfield pixels. In this mode the background color is provided by color register COLPM0 while COLBAK is used for Playfield pixel value $8. This mode is accessible in Atari BASIC as Graphics 10,
  • GTIA color interpretation mode $C — 15 hues in a single shade/luminance value, plus the background. The value of the background, COLBK sets the luminance level of all other pixels (pixel value $1 through $F). The least significant bit of the luminance value is not observed, so only the standard/CTIA 8 luminance values are available ($0, $2, $4, $6, $8, $A, $C, $E). Additionally, the background itself uses only the color component set in the COLBK register. The luminance value of the background is forced to 0. This mode is accessible in Atari BASIC as Graphics 11.

Of these modes, Atari BASIC Graphics 9 is particularly notable. It enables the Atari to display grayscale digitized photographs, which despite their low resolution were very impressive at the time. Additionally, by allowing 16 shades of a single hue rather than the 8 shades available in other graphics modes, it increases the amount of different colors the Atari could display from 128 to 256. Unfortunately, this feature is limited for use in this mode only, which due to its low resolution was not widely used.

The Antic 2 and 3 text modes are capable of displaying the same color ranges as mode F graphics when using the GTIA's alternate color interpretations. However, since the pixel reduction also applies and turns 8 pixel wide, 2 color text into 2 pixel wide, 16 color blocks these modes are unsuitable for actual text, and so these graphics modes are not popular outside of demos. Effective use of the GTIA color interpretation feature with text modes requires a carefully constructed character set treating characters as pixels. This method allows display of an apparent GTIA "high resolution" graphics mode that would ordinarily occupy 8K of RAM to instead use only about 2K (1K for the character set, and 1K for the screen RAM and display list.)

The GTIA also fixed an error in CTIA that caused graphics to be misaligned by "half a color clock". The side effect of the fix was that programs that relied on color artifacts in high-resolution monochrome modes would show a different pair of colors.[5][15]

Atari owners can determine if their machine is equipped with the CTIA or GTIA by executing the BASIC command POKE 623,64. If the screen blackens after execution, the machine is equipped with the new GTIA chip. If it stays blue, the machine has a CTIA chip instead.

Bugs

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The last Atari XE computers made for the Eastern European market were built in China. Many if not all have a buggy PAL GTIA chip. The luma values in Graphics 9 and higher are at fault, appearing as stripes. Replacing the chip fixes the problem. Also, there have been attempts to fix faulty GTIA chips with some external circuitry.

See also

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References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia
from Grokipedia
The CTIA (Computer Television Interface Adaptor) and GTIA (Graphics Television Interface Adaptor) are custom integrated circuits developed by , Inc., serving as the primary video output chips in the Atari 8-bit family of home computers—such as the , , and subsequent XL/XE models—and the home video game console. The CTIA, introduced in 1979 with the initial launch of the and ( versions), handled essential graphics functions including color and luminance generation, sprite (player and missile) management, , and input from joysticks and console keys, supporting up to nine graphics modes (GR.0 through GR.8) from a 128-color palette at resolutions up to 320x192 pixels. The GTIA, released in early 1982 as a direct upgrade and replacement for the CTIA, expanded these capabilities with three additional graphics modes (GR.9 through GR.11), a 256-color palette, and refinements such as shifted video timing for better sprite-playfield integration, while maintaining that allowed simple chip swaps in existing systems. These chips worked in tandem with Atari's other custom hardware, notably the ANTIC chip for display list management and data fetching from RAM, and the chip for sound and input processing, enabling the sophisticated that defined Atari's 8-bit . In the console, launched in 1982, the GTIA was the standard video chip, generating TV signals for sprite overlays (four 8-pixel-wide players and four 2-pixel-wide missiles, each up to 256 pixels tall), per-line color changes across the full 256-color palette, and between elements, while also interfacing with the system's controllers. The transition from CTIA to GTIA during production runs of the Atari and 800—initially limited to about 100,000 units with CTIA—reflected Atari's rapid iteration on hardware to support more advanced games and applications, with the upgrade provided free under warranty or at service centers. A SECAM variant, the FGTIA, was used in European PAL/ systems, adapting the palette to 128 colors with eight levels per hue. Overall, the CTIA and GTIA were pivotal in establishing the 8-bit platform's reputation for high-quality color graphics in the early , influencing through features like hardware sprites and collision handling that were advanced for the era. Their memory-mapped registers at addresses D000D000–D01F allowed programmers to control priorities, sizes, and colors dynamically, supporting titles from simple to complex arcade ports. Despite the platform's eventual supersession by 16-bit systems, these chips remain emulated in modern software and hardware recreations, underscoring their enduring technical legacy.

History

Origins in the Atari 2600 TIA

The Television Interface Adaptor (TIA), also known as the Stella chip during development, served as the core graphics, audio, and input processor for the Atari Video Computer System (VCS), later renamed the Atari 2600, which was released in September 1977. Designed primarily by integrated circuit engineers Jay Miner and Joseph Decuir at Atari, Inc., the TIA was a custom MOS Technology-fabricated chip that integrated video signal generation, sound synthesis, and controller reading into a single 40-pin IC, minimizing hardware costs for the second-generation home video game console. This design choice was pivotal to the Atari 2600's commercial success, with over 30 million units sold worldwide by the end of its production run in 1992, establishing Atari as the dominant force in the early home gaming market. The TIA featured a 20-register architecture, consisting of writable control registers for configuring video output, audio channels, and input handling, with many addresses mirrored across the 6502 CPU's memory map from $0000 to $00FF for efficient access. Video functions were managed through registers like those for playfield graphics (PF0–PF2), player sprites (GRP0–GRP1), missiles (ENAM0–ENAM1), ball (ENABL), colors (COLUBK, COLUPF, COLUP0–1), and positioning (RESPx, HMPx), enabling the generation of composite video signals including sync, luminance, and chroma modulation. Audio was handled by two independent channels via frequency (AUDF0–1), volume (AUDV0–1), and distortion (AUDC0–1) registers, producing simple waveforms for sound effects. Input processing included six ports (INPT0–5) for reading analog paddles and digital joystick buttons, with latching mechanisms to capture controller states during vertical blanking. Central to the TIA's operation was the "racing the beam" technique, in which the 6507 CPU (a variant of the MOS 6502) synchronized its execution with the cathode-ray tube's electron beam scanning the display line by line. Without dedicated video RAM or interrupts, programmers wrote code kernels to update TIA registers precisely 76 CPU cycles (228 color clocks) per scanline, using the WSYNC register to halt the CPU until the horizontal blanking interval ended, ensuring timely graphics reconfiguration for each of the 192 visible lines in NTSC mode. This real-time approach allowed dynamic content but demanded meticulous timing to avoid visual artifacts, as the beam's progress could not be paused. Despite its innovations, the TIA imposed significant constraints that defined Atari 2600 game design. It supported only four colors per scanline—background, playfield, player 0, and player 1—from a palette of 128 possible hues (16 base colors with 8 levels), requiring mid-line register changes for multicolored effects. Horizontal resolution was fixed at 160 pixels, with vertical positioning limited to even-numbered scanlines unless using the VDELPx delay registers. covered 15 pairwise interactions (e.g., player-playfield or player-player) but omitted playfield-playfield checks, forcing software emulation. Finally, the system's reliance on CPU-driven beam synchronization left minimal cycles for logic, often consuming over 90% of processing time per frame.

Development and Release of CTIA

The CTIA (Complex Television Interface Adaptor) chip was developed by in 1977 as part of the design effort for its first personal computers, the Atari 400 and 800, under the direction of with contributions from Decuir and the engineering team, with key design reviews and specification finalizations occurring by December of that year. The primary goal was to automate graphics generation and color handling, moving beyond the manual, scanline-by-scanline control required by the earlier TIA (Television Interface Adaptor) chip in the console, thereby enabling more sophisticated display capabilities suitable for computing applications. This automation allowed the CPU to focus on higher-level tasks while the CTIA interpreted display data from the companion ANTIC chip. Production units of the Atari 400 and 800, both equipped with the CTIA, began shipping in November 1979 and continued through 1981, marking the chip's primary deployment in early models of these 8-bit computers. Key upgrades from the TIA included a 128-color palette (16 hues with 8 levels each) for richer visuals and support for doubled horizontal resolution up to 320 pixels in certain modes when combined with ANTIC's playfield data interpretation. Additionally, the CTIA handled playfield coloring directly from ANTIC's output, streamlining the rendering of text and . Despite these advances, the CTIA had notable limitations, including a half-color-clock shift that caused sprite (player/) misalignment relative to the playfield by half a color clock cycle, leading to visual artifacts in high-resolution displays. The chip also integrated input handling for triggers (via ports for four controllers) and console keys (Start, Select, Option), reading these through dedicated registers to support interactive applications without additional hardware. These features were exposed via memory-mapped registers in the range D000D000–D01F, enabling software control over and . In 1981, introduced the GTIA as a revised version to address such flaws.

Introduction and Evolution of GTIA

The GTIA (Graphic Television Interface Adaptor) was introduced in late 1981 as a revised version of the CTIA chip, led by the same design team under , serving as the primary graphics processor for the Atari 8-bit family of computers, including the Atari , , and subsequent XL and XE series models. This upgrade coincided with the full production rollout of the Atari 5200 home video game console, where the GTIA handled color, , and player-missile graphics generation in tandem with the ANTIC chip. Unlike the initial CTIA-equipped units, which were limited to early production runs of the Atari and from 1979 to mid-1981, the GTIA became the standard component, enabling enhanced visual capabilities that standardized graphics across 's 8-bit ecosystem. The evolution of the GTIA addressed key limitations in the CTIA while expanding the palette, building briefly on the foundational 128-color support of its predecessor to achieve a full 256-color palette through 16 distinct hues multiplied by 16 levels. It corrected alignment issues in the CTIA, such as the half-color-clock shift that misaligned player and graphics with high-resolution mode 8 displays, by adjusting the playfield timing for precise synchronization. Additionally, the GTIA introduced three new display modes—modes 9, 10, and 11—derived from ANTIC's high-resolution mode F, allowing for 16 levels of a single hue (mode 9), nine independent colors (mode 10), and 16 hues at a single (mode 11), which significantly broadened options for static and dynamic visuals without altering core compatibility. From its 1981 debut, the GTIA remained in production for all 8-bit systems through 1992, powering over two million units and ensuring consistent graphics performance across the lineup until the line's discontinuation. Its design maintained full with CTIA-based software, with programs able to detect the GTIA's presence via specific register reads to enable enhanced features like the new modes. This longevity stemmed from the chip's role in supporting advanced color handling demanded by early software, including ports of arcade games like , which benefited from the expanded palette to approximate original visuals more faithfully. Although Atari explored prototypes combining ANTIC and GTIA functions into a single cost-saving chip (CGIA), none advanced beyond testing to reach full production.

Technical Overview

Core Architecture and Functions

The CTIA and GTIA chips share a core centered around 32 registers mapped at addresses D000D000–D01F in Atari 8-bit computer systems or C000C000–C01F in the console, with varying read/write properties including write-only for configuration and read-only for status. This register set enables precise management of graphical elements without requiring dedicated processor cycles for rendering. The of the architecture illustrates a streamlined where input streams are processed in real-time to generate synchronized video signals, emphasizing efficiency in sprite handling and color modulation. At their core, these chips perform the essential function of merging playfield data supplied by the ANTIC chip—such as background and —with four independently controllable player sprites and four sprites to form the complete display image. The resulting output is a signal, with distinct chroma and luma components that ensure compatibility with standard television standards, including artifact color generation for enhanced visual fidelity. This integration allows for dynamic overlays where sprites can appear in front of or behind playfield elements based on priority settings, supporting smooth animations and interactive in and applications. Operationally, the CTIA and GTIA synchronize to the color clock of 3.579545 MHz, which dictates the timing for horizontal resolution and color subcarrier generation across each scanline. Player sprite widths are adjustable to 8, 16, or 32 pixels and missile sprite widths to 2, 4, or 8 pixels, providing flexibility for scaling objects while maintaining performance within the fixed clock cycle budget. For color handling, the CTIA employs phase-shift encoding to produce 128 distinct colors by modulating the chroma signal's phase relative to levels. The GTIA builds on this by adding independent control, expanding the palette to 256 colors through finer in adjustments without altering the phase-based hue selection.

Integration with ANTIC Chip

The CTIA and GTIA chips integrate closely with the ANTIC chip in 8-bit systems to enable automated graphics generation, where ANTIC serves as the display list processor responsible for fetching and formatting playfield data from memory, while CTIA/GTIA handles the final rendering by overlaying sprites and applying visual priorities. ANTIC processes display list instructions, including Load Memory Scan (LMS) commands that specify memory locations for character modes or data, and outputs this information as serialized streams to CTIA/GTIA via the three-bit AN0-AN2 bus. This bus encodes playfield colors (PF0-PF3), background (BAK), signals, and blanking, allowing ANTIC to drive up to five colors per playfield mode without direct CPU intervention during active display. In character modes, ANTIC fetches mode data and character sets from RAM using (DMA), streamlining rendering for resolutions from low-resolution text to high-resolution bitmaps, with GTIA supporting enhanced modes (9, 10, 11) that interpret four-bit data for greater . The data flow from ANTIC to CTIA/GTIA involves ANTIC buffering fetched playfield pixels in a 48-byte line buffer before shifting them out at color clock rates, typically during horizontal active periods (color clocks $30 to $CF for normal width), where GTIA then composites this with player-missile graphics and collision information. ANTIC provides collision detection inputs by signaling playfield occupancy, which GTIA uses to set hardware flags in registers like P0PF through M3PF, detecting overlaps between sprites and playfield elements without CPU polling during rendering. GTIA applies priority logic based on the PRIOR register to determine layering, such as whether sprites appear in front of or behind the playfield, ensuring seamless overlay of up to four players and four missiles. This pipeline frees the 6502 CPU from graphics tasks in Atari 8-bit computers, as ANTIC's DMA handles all memory access for playfields and sprites, reducing overhead to as low as 1/8 CPU cycles in efficient modes. Synchronization between ANTIC and CTIA/GTIA relies on the vertical blanking interval (VBI) for safe register updates, occurring at scan line 248 () or during vertical sync lines (251-253 ), where ANTIC suspends DMA to allow the CPU to modify display lists, colors, or positions without artifacts. The WSYNC register in GTIA halts the CPU until the end of the current scan line (cycle 105), coordinating horizontal timing, while ANTIC's horizontal blank signals via the ANx bus ensure GTIA aligns sprite rendering correctly. Horizontal fine , controlled by ANTIC's HSCROL register (0-15 color clocks), shifts the playfield output on the ANx bus, indirectly affecting relative sprite positioning by delaying delivery, with even values required in GTIA modes to maintain bit pairing. Vertical via VSCROL adjusts mode line heights across scan lines, further integrating ANTIC's control over dynamic displays. In the console variant, integration differs due to the absence of ANTIC's full programmable display list processor, relying instead on direct CPU control for setup without the automated DMA-driven modes of 8-bit computers, though ANTIC still provides basic DMA for sprite and playfield data to CTIA/GTIA. This setup simplifies video output for console gaming, mapping GTIA to $C000-CFFF and limiting features like display list interrupts, but maintains core data flow via the ANx bus for collision handling and sprite overlay. ANTIC's DMA in the 5200 frees the CPU similarly for playfield fetches, but the fixed display structure requires more manual programming compared to the flexible lists in 400/800/XL systems.

Versions and Variants

CTIA Revisions and Production Details

The primary revision of the CTIA chip bore the CO12295 and served as the initial graphics interface for 's 8-bit computer line. Introduced in 1979, it was produced in collaboration with semiconductor fabricators to meet launch timelines for the Atari 400 and 800 models. Production of the CO12295 spanned from 1979 to approximately 1981, equipping the early runs of Atari 400 and 800 units before being phased out due to hardware bugs, such as misalignment between players, missiles, and the playfield by half a color clock cycle. Estimates place the total units manufactured at approximately 100,000, aligning with initial sales of the Atari 8-bit computers prior to the transition to improved hardware. This short production window reflected Atari's rapid iteration to address limitations in the original design. No major sub-revisions of the CTIA were documented, maintaining a consistent implementation across units. Compatibility with later software, which often assumed the successor GTIA chip, was achieved through programmatic detection, such as entering GRAPHICS 9 (yielding a blue screen on CTIA versus black on GTIA) or using POKE 623,64 to test register responses. Available documentation on CTIA manufacturing remains incomplete, with scant details on fabrication yields, specific process technologies, or defect rates from the era. Modern emulators, such as Altirra, must incorporate models of CTIA-specific quirks—like collision detection anomalies and artifacting behaviors—to faithfully replicate early hardware performance.

GTIA Revisions and Compatibility

The GTIA chip, introduced in early 1982 as a successor to the CTIA, featured the primary NTSC revision under part number C014805, which served as the standard implementation for Atari's XL and XE series computers as well as the Atari 5200 console. This revision expanded upon the CTIA's capabilities by adding three new graphics modes (9 through 11) and support for a 256-color palette, while maintaining full backward compatibility for existing CTIA-based software through emulation of CTIA register behaviors and display functions. Later variants included PAL-optimized versions, such as the C014889, tailored for European markets with adjustments to color phasing and burst signals to accommodate PAL video standards, and the rare FGTIA (part number C020120) for SECAM systems, which featured modified luminance handling in certain modes. Production of GTIA chips was handled by Atari and its semiconductor contractors, with over one million units manufactured to support the Atari 8-bit family and 5200 systems, reflecting the combined sales of approximately four million 8-bit computers and one million 5200 consoles during their run. Manufacturing continued through the mid-1980s for official Atari products. These extended runs ensured availability for hobbyist and clone markets into the 1990s, though no integrated ANTIC-GTIA combined chips reached production despite prototype explorations. GTIA achieves compatibility with CTIA systems by emulating core functions like player-missile graphics, collision detection, and priority handling via identical register mappings, allowing CTIA software to execute unchanged on GTIA-equipped machines; however, GTIA-specific features like modes 9-11 produce invalid or garbled output on CTIA hardware. Software detection of GTIA presence typically involves reading the PAL register at $D014, which returns $0F on NTSC GTIA, $01 on PAL GTIA, and a different value (often $00) on CTIA due to the absence of the dedicated PAL register, enabling programs to branch to GTIA-enhanced routines accordingly. Alternative detection methods include attempting to enter graphics mode 9 via the OS, where a successful black screen confirms GTIA while a blue screen indicates CTIA, as documented in early 1980s Atari magazines. Modern FPGA recreations, such as those in VBXE upgrades, aim to replicate GTIA behavior with exact register timing for seamless compatibility across original and emulated systems. Original GTIA chips, particularly the common C014805 NTSC revision, remain available in the secondary market for retro computing enthusiasts and collectors. Recent eBay sold listings for used or tested C014805 chips show typical prices ranging from $17 to $25 USD, with examples including a fixed-price listing that sold 141 units at $24.95 (plus shipping), tested working chips at $19.99, and single chips at $16.99. This reflects common market values for this vintage Atari 8-bit/5200 component.

Interfaces and Pinouts

CTIA Pinout and Electrical Characteristics

The CTIA (C010232 or similar variants) is packaged in a 40-pin (DIP), designed for integration into the 400 and early 800 motherboards. The pinout is identical to that of the GTIA, facilitating connections to the ANTIC chip for graphics data input, the 6502 CPU for register access, , and video output circuits. Power and ground connections are pin 27 as VCC (+5 V) and pin 3 as VSS (ground). Address inputs (A0–A4) are on pins 2, 1, 40, 39, 38, enabling direct memory-mapped I/O for the chip's registers via the system data bus (D0–D7 on pins 7, 6, 5, 4, 37, 36, 35, 34). Inputs from the ANTIC chip, including playfield data lines (PF0–PF3 via AN0–AN2 on pins 18, 19, 20) are used for mode select and rendering synchronization. Video output pins include chroma (COL on pin 21), luma (L0–L3 on pins 31, 22, 23, 24), and composite sync (CSYNC on pin 25), providing NTSC-compatible signals for RF modulation or direct monitor output. Additional pins include oscillator input (OSC on pin 28 at 3.579545 MHz colorburst frequency for NTSC), phase 2 clock (Ø2 on pin 30), chip select (CS on pin 32), read/write (R/W on pin 33), color delay (DEL on pin 17), halt (HALT on pin 26), and trigger inputs (T0–T3 on pins 8–11). Collision detection is handled internally, with no dedicated output pins listed. Console keys and speaker are managed via switch data I/O (S0–S3 on pins 12–15).
Pin GroupPinsFunctions (Examples)
Power/Ground3, 27VSS (ground on 3), VCC (+5 V on 27)
ANTIC Inputs17–20DEL (17), AN0–AN2 (18–20, playfield data and mode select)
Video Outputs21–25, 22–24, 31COL (chroma on 21), L0–L3 (luma on 31,22,23,24), CSYNC (25), fast phase clock (FØ0 on 29)
Address/Data Bus1–2, 4–7, 34–40A0–A4 (2,1,40,39,38), D0–D7 (7,6,5,4,37,36,35,34 bidirectional)
Controls/Triggers8–15, 32–33T0–T3 (triggers on 8–11), S0–S3 (console/speaker on 12–15), CS (32), R/W (33), HALT (26)
The CTIA requires a nominal 5 V DC supply with a maximum current consumption of approximately 100 mA under full load, ensuring compatibility with the system's regulated power rail. All I/O pins operate at TTL logic levels (high: 2.0–5.5 V, low: 0–0.8 V), with input around 5–10 pF and output drive capability sufficient for bus loading in the architecture. The color clock is synchronized via pin 28, while horizontal and vertical timing is derived from ANTIC's display signals. In comparison to the GTIA, the CTIA's interface is identical, but lacks support for advanced modes, resulting in no need for certain internal configurations. This design prioritizes compatibility with early Atari systems but limits extensibility. The core pin assignments for power, data bus, and basic video outputs are the same as the GTIA, enabling straightforward upgrades in compatible hardware.

GTIA Pinout and Signal Mapping

The GTIA chip, part number C014805, is packaged in a 40-pin dual in-line package (DIP) configuration, sharing the identical pinout with the CTIA for backward compatibility. Pin 27 provides +5 V supply (VCC) and pin 3 is ground (VSS). Pins 18–20 form the primary interface with the ANTIC chip, handling playfield data inputs (PF0–PF3 via AN0–AN2) and synchronization signals such as color delay (DEL on pin 17). Sprite positioning is controlled via memory-mapped registers rather than dedicated clock input pins; horizontal positioning occurs during ANTIC-generated display timing. Pins 21, 22–24, and 31 manage video signal outputs, generating chroma (COL on pin 21) and (L0–L3 on pins 31, 22, 23, 24) signals, along with composite sync (CSYNC on pin 25) for or PAL standards with 1 V peak-to-peak luma output. Graphics modes 9–11 are selected via registers, not a dedicated pin. Pins 8–11 serve as inputs for triggers (T0–T3), and pins 12–15 for console keys and speaker control (S0–S3). Pin 16 is not connected (or PAL clock in later variants). The signal mapping in the GTIA is compatible with the CTIA, with enhancements for multicolored sprites and additional modes handled internally. Address inputs (A0–A4) are on pins 2, 1, 40, 39, 38, and data bus (D0–D7) on pins 7, 6, 5, 4, 37, 36, 35, 34. Electrically, it operates at 5 V with approximately 100 mA current consumption, matching the CTIA while offering improved performance. This design allows the GTIA to serve as a for the CTIA in 8-bit systems. Detailed signal timings and characteristics are outlined in Atari's engineering documentation, which remains essential for pin-accurate modeling in modern hardware emulators and reproductions.

Registers and Controls

Player and Missile Positioning Registers

The Player and Missile Positioning Registers in the CTIA and GTIA chips are responsible for defining the horizontal starting positions of the four players and four , enabling precise placement of these sprites on the display. These 8-bit registers accept write operations to set positions in discrete units relative to the horizontal synchronization pulse, allowing for dynamic and interaction in games and applications. The functionality is identical between the CTIA and its successor GTIA for basic operation, ensuring compatibility across 8-bit systems. The player positioning registers consist of HPOSP0 (D000),HPOSP1(D000), HPOSP1 (D001), HPOSP2 (D002),andHPOSP3(D002), and HPOSP3 (D003). Each is an 8-bit write register that sets the starting position for the corresponding player in a range of 0 to 227 color clocks from the horizontal sync reference point. Writing a value to these registers immediately latches the position for the next display line, with values wrapping around if exceeding the screen width due to the modular nature of the timing. The positioning registers operate analogously and include HPOSM0 (D004),HPOSM1(D004), HPOSM1 (D005), HPOSM2 (D006),andHPOSM3(D006), and HPOSM3 (D007). These 8-bit write registers define the horizontal start for each , also in the 0-227 color clock range, and are latched upon write to synchronize with the display timing. Like the player registers, positions are independent but can be coordinated for effects such as projectiles attached to players. In operation, these registers position sprites relative to the horizontal sync pulse, independent of the playfield background generated by ANTIC. The ANTIC fine horizontal scroll value (from the HSCROL register at $D404) introduces an offset to the playfield, effectively shifting the background relative to the fixed sprite positions and enabling smooth relative movement without constant register updates. The effective pixel position of a sprite, accounting for this interaction, is calculated as (register value × 4) − ANTIC scroll value, where the multiplication by 4 converts the register units to color clocks (each unit representing four color clocks). This formula provides sub-unit precision for alignment when combined with scroll adjustments. To prevent visible glitches during active display, these registers are typically updated during the vertical blanking interval (VBI), a safe period when the screen is not being scanned. While the core positioning mechanics are the same in CTIA and GTIA, the GTIA introduces mode-specific scaling in its extended graphics modes (such as modes 9–11), where player and missile widths may be interpreted differently based on the display mode selected via the PRIOR register, allowing for finer control in luminance-based rendering. Positioning integrates briefly with size registers to form complete sprite definitions, but detailed scaling is handled separately.

Size and Graphics Pattern Registers

The player and missile size registers in the CTIA and GTIA chips control the horizontal scaling of sprites, allowing for variable widths to accommodate different visual needs in rendering. The SIZEP0 (D008)throughSIZEP3(D008) through SIZEP3 (D00B) registers each govern one player (0 to 3), respectively. These write-only registers use the low two bits to set the width multiplier: a value of 0 or 2 (binary 00 or 10) selects normal width, where each of the 8 bits in the pattern spans 1 color clock for a total of 8 color clocks; a value of 1 (binary 01) selects double width, spanning 2 color clocks per bit for 16 total; and a value of 3 (binary 11) selects quadruple width, spanning 4 color clocks per bit for 32 total. Higher bits in these registers are unused and have no effect on operation. The SIZEM register ($D00C) similarly controls missile scaling in a single write-only byte, with paired bits dedicated to each missile: bits 1–0 for missile 0, 3–2 for missile 1, 5–4 for missile 2, and 7–6 for missile 3. The encoding mirrors that of the player registers—00 or 10 for normal (1 color clock per bit, 2 clocks total per missile since missiles use 2 bits in pattern data), 01 for double (4 clocks total), and 11 for quadruple (8 clocks total)—enabling independent sizing across the four missiles. These size settings apply uniformly across the sprite's height and interact with horizontal positioning to define sprite boundaries on the display. The graphics pattern registers define the bitmapped data for sprite visibility on each scanline. GRAFP0 (D00D)throughGRAFP3(D00D) through GRAFP3 (D010) are write-only registers, each holding an 8-bit value for one player, where bit 0 represents the leftmost position and bit 7 the rightmost (1 for visible , 0 for transparent). These patterns render sprites 8 s (color clocks in normal size) wide by default, expanding to 16 or 32 clocks based on the SIZEP settings, for effective widths of 8, 16, or 32 s in high-resolution modes. The GRAFM register ($D011) handles s in a single 8-bit write-only format, with bits 0–3 corresponding to s 0–3 (1 visible, 0 transparent) and bits 4–7 unused; each spans 2 bits in this scheme but renders as 2, 4, or 8 color clocks wide per SIZEM configuration. In operation, ANTIC fetches pattern data via DMA from dedicated player-missile RAM (typically 128 bytes per player for 256 scanlines and 128 bytes shared for all missiles) and latches it into the GRAFP and GRAFM registers at the start of each scanline, ensuring the aligns with the current display row. This latching supports sprites up to 256 lines tall by sequentially updating every 8 lines, though the registers themselves define only the current scanline's data. The CTIA version exhibits a hardware bug causing player and missile to shift left by half a color clock (one in medium-resolution modes) relative to the playfield, particularly noticeable in graphics mode 8; the GTIA revision corrects this alignment for precise overlay.

Color and Luminance Registers

The color and luminance registers in the CTIA and GTIA chips control the visual appearance of graphical elements in 8-bit computers by specifying hue and intensity values for players, missiles, playfield planes, and the background. These registers are write-only hardware locations accessed via the system's I/O space, with corresponding shadow registers in the operating system for safer manipulation. The four player color registers, COLPM0 through COLPM3 at addresses D012toD012 to D015, assign colors to the four player sprites and their associated s, where each missile inherits the color of its corresponding player by default. Similarly, the playfield color registers COLPF0 through COLPF3 at D016toD016 to D019 define colors for the four playfield planes generated by the ANTIC chip, while COLBK at $D01A sets the background color behind all elements. Each register is an 8-bit value encoding both hue and luminance in a color-luminance (CL) format derived from the (or PAL) color clock system. The upper 4 bits (bits 7-4) represent the hue, providing 16 possible phases (0-15) that cycle through the at the system's color clock frequency of approximately 1.79 MHz for . The lower 4 bits (bits 3-0) represent , intended for 16 intensity levels (0-15), but the CTIA chip effectively utilizes only 8 levels (0-7), with bit 0 ignored, resulting in a 128-color palette (16 hues × 8 ). In contrast, the GTIA chip supports the full 16 levels, enabling a 256-color palette (16 hues × 16 ) in standard modes, though higher values may exhibit clipping or reduced distinction on some displays. The color value is constructed using the formula: color = (hue << 4) | luma, where hue and luma are 4-bit integers; for example, a medium red might use hue 4 and luma 8, yielding $48. To achieve flicker-free color changes, especially during animations or palette rotations, these registers are typically updated during the vertical blank interval (VBI), when the display beam is off-screen and no graphics are being rendered. The operating system shadows these values at locations 02C002C0-02C3 for players and 02C402C4-02C8 for playfield/background, transferring them to the hardware registers automatically at the start of each frame unless direct hardware access is enabled via the SDMCTL register. This mechanism allows programmers to redefine colors mid-frame using display list interrupts for effects like multicolored text, but the core assignment remains tied to these dedicated registers for consistent rendering of players, missiles, playfield, and background. The PRIOR register ($D01B) can briefly reference these colors for blending decisions, but does not alter their assignment.

Collision Detection Registers

The collision detection registers in the CTIA and GTIA chips provide hardware support for identifying overlaps between players, missiles, and playfield elements during display rendering, enabling efficient event detection in software without pixel-by-pixel scanning. These read-only registers are located in the I/O space at addresses D000toD000 to D00F and capture collision events in real time within the visible display area (horizontally from color clock 34 to 221, vertically lines 8 to 247). There is no detection for playfield-to-playfield collisions, focusing instead on sprite-playfield and sprite-sprite interactions. The missile-to-playfield collision registers, M0PF (D000)throughM3PF(D000) through M3PF (D003), each consist of an 8-bit value where bits 0 through 3 correspond to collisions with playfield sections PF0 through PF3, respectively (bit 0 for PF0, bit 1 for PF1, bit 2 for PF2, bit 3 for PF3); a set bit (1) indicates a collision has occurred for that missile with the specified playfield segment. Similarly, the player-to-playfield registers, P0PF (D004)throughP3PF(D004) through P3PF (D007), follow the same bit layout, detecting collisions for each player (P0 through P3) against the four playfield quadrants. The missile-to-player registers, M0PL (D008)throughM3PL(D008) through M3PL (D00B), use bits 0 through 3 to flag collisions between each missile and players P0 through P3 (bit 0 for P0, etc.), while the player-to-player registers, P0PL (D00C)throughP3PL(D00C) through P3PL (D00F), detect mutual overlaps among players with the same bit mapping (noting no self-collision, e.g., P0 with itself). Bits 4 through 7 in all these registers are unused or reserved. Upon detecting a collision during a color clock cycle (typically within a 1-2 clock window), the corresponding bit latches to 1 and remains set until explicitly cleared, allowing software to poll these registers during the vertical blank interval (VBI) to process events that may have occurred across multiple frames. Clearing is achieved by writing any value to the HITCLR register at $D01E, which resets all collision latches simultaneously across the eight registers. Programmers test specific bits using bitwise operations, such as checking for a player collision with if (register & (1 << player_index)), where player_index is 0-3 for P0-P3, to determine if an event has latched. While the core collision mechanics are identical between CTIA and GTIA, the GTIA corrects the CTIA's half-color-clock shift for better sprite-playfield alignment, potentially improving detection precision in overlay scenarios. Both chips disable playfield collisions in certain GTIA-specific modes (e.g., modes 9 and 11). In game logic, these registers facilitate immediate response to collisions, such as triggering sound effects or altering trajectories, by integrating detection results into the main program loop.

Priority and Miscellaneous Control Registers

The PRIOR register, located at address $D01B, is a key control mechanism in the CTIA and GTIA chips for establishing the rendering order of graphical elements, including players, missiles, and playfield segments, as well as selecting enhanced display modes unique to the GTIA. This 8-bit write-only register uses bits 0-2 to select one of eight standard priority schemes that determine whether players and missiles appear behind, in front of, or interleaved with playfield elements such as PF0, PF1, PF2, and PF3. For instance, mode 0 places all players and missiles behind the playfield, while mode 7 positions them in front, allowing for complex layering in games and applications. Bit 4 enables fifth player mode (merging all missiles into a single entity using PF3's color and priority), and bit 5 enables player multicolor blending (where overlapping players 0/1 or 2/3 combine to a third color derived from the two instead of the background). Bits 6-7 select the display mode: 00 for normal operation with ANTIC modes 0-8; 01 for GTIA mode 9 (16 luminance levels of background color, used with ANTIC mode F for grayscale); 10 for GTIA mode 10 (9-color mode using all color registers, with one color clock delay); 11 for GTIA mode 11 (16 hues at background luminance, used with ANTIC mode F). Bit 3 is unused. The VDELAY register at $D01C provides fine vertical positioning control for player and missile sprites by introducing targeted delays in their display timing, particularly useful in two-line resolution modes to achieve single-scanline accuracy. This 8-bit write-only register dedicates individual bits to each sprite: bits 0 through 3 control players 0 to 3, respectively (bit 0 for P0, etc.), while bits 4 through 7 manage missiles 0 to 3 (bit 4 for M0, etc.). Setting a bit to 1 delays the corresponding sprite's data fetch and update to occur on every odd scanline rather than every scanline, effectively shifting the sprite downward by one scanline relative to the playfield; this mechanism masks DMA fetches from ANTIC, allowing programmers to adjust sprite starts without altering horizontal positioning registers. Although described in some contexts as supporting cumulative delays up to 255 scanlines, in practice, each bit enables a binary (0 or 1 scanline) delay per sprite, enabling precise alignment in interlaced or high-resolution scenarios while conserving memory bandwidth. This feature is essential for smooth sprite movement in vertically scrolling displays or when synchronizing with ANTIC's display list. The GRACTL register, addressed at $D01D, governs the enabling and configuration of player-missile graphics subsystems, including DMA operations and input latching. This 8-bit write-only register's primary bits include bit 4 (player DMA enable: 1 activates ANTIC fetches for player graphics data) and bit 5 (missile DMA enable: 1 activates fetches for missile data), which must be set in conjunction with ANTIC's DMACTL to render sprites; bit 2 latches joystick trigger inputs (TRIG0-TRIG3) until read, preventing momentary glitches in input handling (1=latched). Bit 6 serves as the overall graphics enable for player-missile output to the display (1 activates rendering). Bits 0, 1, 3, and 7 are unused or revision-specific, with no effect in CTIA. Writing to this register can strobe the light pen input in some implementations. Clearing collision detection, such as via the HITCLR register, may be referenced alongside GRACTL to reset sprite interactions after enabling graphics. These controls ensure efficient resource allocation, as disabling DMA conserves CPU cycles during non-graphical scanlines. Missile integration with players for composite sprites is achieved via positioning or the fifth player mode in PRIOR, not a dedicated GRACTL bit.

Console Input and Output Registers

The console input and output registers in the CTIA and GTIA chips handle user interactions from console keys and joystick triggers, as well as basic audio output via the internal speaker. These registers are mapped at $D01F for the primary console interface (CONSOL) and support read operations for key states alongside write operations for speaker control. In Atari 8-bit computers, the CONSOL register provides direct access to the Option, Select, and Start keys, while in the Atari 5200 console, it is repurposed for reading multiplexed controller inputs due to the absence of dedicated console keys. The CONSOL register at D01F is read-only for input detection but writable for speaker toggling. When reading, bits 7–4 always return 1, bit 3 reflects the speaker control state (typically reading as 0), bit 2 indicates the [Option key](/page/Option_key) (0 if pressed, 1 if released), bit 1 indicates the Select key (0 if pressed, 1 if released), and bit 0 indicates the Start key (0 if pressed, 1 if released). To accurately detect key presses, software must first write &#36;08 (setting bit 3 to 1) to enable pull-up on the input lines, then read the register; pressed keys pull the corresponding bits low. This debouncing and pull-up mechanism ensures reliable input without hardware debounce capacitors. In the [Atari 5200](/page/Atari_5200), the same register reads multiplexed states from controller keypads and top fire buttons after selecting the input line via writes to adjacent GTIA color registers (D012–$D017), with bits 0–4 used for specific button states (e.g., bit 0 for keypad 0/10, bit 4 for top fire). Speaker control, known as CONSPK when writing to $D01F, generates simple tones by toggling bit 3 between 0 and 1 during vertical blank intervals, effectively dividing the system clock (approximately 1.79 MHz NTSC) to produce audible beeps at around 1–2 kHz depending on toggle frequency. Writing $00 sets bit 3 low (enabling tone output), while $08 sets it high (silencing the speaker); rapid toggling creates the beep, with the speaker connected directly to this bit via a simple RC filter for decay. The Atari 5200 lacks a physical speaker, rendering this function inoperable, though the register remains for software compatibility. Audio is limited to this monaural, low-fidelity output with no volume or waveform control beyond on/off toggling. Joystick triggers are handled via dedicated GTIA registers at D010D010–D013 (TRIG0–TRIG3), each a single-bit read-only input where 0 indicates pressed and 1 indicates released; these directly sense bottom fire buttons on Atari 8-bit joysticks and Atari 5200 controllers without multiplexing. In the Atari 5200, top fire buttons are instead read via debounced scans of D01Faftercontrollerselection,integratingwiththePOT0POT7analoginputs(D01F after controller selection, integrating with the POT0–POT7 analog inputs (D200–D207)forpaddle/joystickposition,whichrequireastrobewritetoPOTGO(D207) for paddle/joystick position, which require a strobe write to POTGO (D20B) to initiate RC-timing reads (values 0–228, where lower indicates farther deflection). Latching for triggers can be enabled via GRACTL ($D01D) bit 2 to hold states until acknowledged. These inputs are debounced in software by the operating system, sampling during vertical blank to avoid jitter. GTIA compatibility with CTIA systems is detectable via the PAL register at D014,whichreadsaconstantD014, which reads a constant FF in GTIA (indicating latched state) but a varying value in CTIA due to unlatched color clock phase feedback. This allows software to probe for GTIA presence and adjust for enhanced features, though console input registers function identically between chips. In the Atari 5200, color registers are multiplexed with controller selection lines, requiring writes to D012D012–D017 to scan up to four controllers sequentially before reading $D01F or POT registers for complete input.
RegisterAddressFunctionRead/WriteKey Details
CONSOL$D01FConsole keys (Option/Select/Start) & speaker toggleRead (keys), Write (speaker)Bits 2:0 for keys (0=pressed after $08 write); bit 3 for speaker toggle
TRIG0–3D010D010–D013Joystick bottom triggersRead-only0=pressed; direct for ports 0–3
POT4–7D204D204–D207Analog joystick/paddle positions (5200 multiplexing)Read-only0–228 values; strobe via D20B;toptriggersviaD20B; top triggers via D01F in 5200
PAL$D014GTIA detection & video standardRead-only$FF=GTIA (NTSC); varying=CTIA; $01=PAL GTIA

Player-Missile Graphics Operation

Sprite Rendering and Display Mechanics

The rendering of sprites, known as player-missile graphics (PMG) in the Atari 8-bit ecosystem, occurs on a per-scanline basis during the active display period, synchronized between the ANTIC chip and the CTIA or GTIA video processor. ANTIC handles the playfield generation and, when player-missile DMA is enabled via the DMACTL register (D400,bits2formissilesand3forplayers),fetchesspritedatafromadedicatedRAMareastartingattheaddressspecifiedbyPMBASE(D400, bits 2 for missiles and 3 for players), fetches sprite data from a dedicated RAM area starting at the address specified by PMBASE (D407), which must align to a 1K or 2K boundary depending on resolution mode. This data—stored as 256 bytes per player or 128 bytes total for all four missiles in single-line resolution (one scanline per byte), or half that in double-line mode—is latched into the GRAFP0–3 (D00DD00D–D010) registers for the four players and GRAFM (D011)forthefourmissilesatthebeginningofeachscanline,withANTICdeliveringitduringspecificcycles(missilesatcycle0,playersatcycles25ina228colorclockNTSCscanline(114CPUcycles)).GTIA(orCTIA)thenprocessesthis8bitdata,shiftingoutbitstoformthespriteshapestartingfromthehorizontalpositiondefinedbytheHPOSP03(D011) for the four missiles at the beginning of each scanline, with ANTIC delivering it during specific cycles (missiles at cycle 0, players at cycles 2–5 in a 228-color-clock NTSC scanline (114 CPU cycles)). GTIA (or CTIA) then processes this 8-bit data, shifting out bits to form the sprite shape starting from the horizontal position defined by the HPOSP0–3 (D000–D003)andHPOSM03(D003) and HPOSM0–3 (D004–$D007) registers, which specify the left-edge position in color clocks (typically 0–227, with visible range 47–208 for safe alignment). Sprite width is determined by the SIZEP0–3 (D008D008–D00B) registers for individual players and the SIZEM (D00C)registerforallmissilescollectively,witheachbitofthegraphicsdatacorrespondingtoonecolorclock(approximately1pixelinhighresolutionmodes).Innormal(1x)size,aplayerspans8pixels(onecolorclockperbitacrossthe8bitbyte);double(2x)sizestretchesthisto16pixelsbyduplicatingeachbitoutput;andquadruple(4x)sizeexpandsitto32pixels,effectivelyreplicatingbitsfourfoldhorizontally.Missilesfollowthesamescalinglogicbutstartas2pixelwideobjects(twobitsperbyte),allowingcollectivewidthsupto8pixelsinnormalmodeor32pixelsinquadruple.Vertically,spritescanspanupto240scanlines(scanlines8247)inNTSCsystems,thoughtypicaldisplaysuse192lines,achievedbyfillingtheentirePMGRAMbuffer,thoughdoublelinemodehalvesthebuffersizewhiledoublingverticalresolutionforsquarerpixelsonNTSCdisplays.ColoringisappliedindependentlyviatheCOLPM03(D00C) register for all missiles collectively, with each bit of the graphics data corresponding to one color clock (approximately 1 pixel in high-resolution modes). In normal (1x) size, a player spans 8 pixels (one color clock per bit across the 8-bit byte); double (2x) size stretches this to 16 pixels by duplicating each bit output; and quadruple (4x) size expands it to 32 pixels, effectively replicating bits fourfold horizontally. Missiles follow the same scaling logic but start as 2-pixel-wide objects (two bits per byte), allowing collective widths up to 8 pixels in normal mode or 32 pixels in quadruple. Vertically, sprites can span up to 240 scanlines (scanlines 8–247) in NTSC systems, though typical displays use 192 lines, achieved by filling the entire PMG RAM buffer, though double-line mode halves the buffer size while doubling vertical resolution for squarer pixels on NTSC displays. Coloring is applied independently via the COLPM0–3 (D012–D015)registersforplayersandCOLPF03(D015) registers for players and COLPF0–3 (D016–$D019) for missiles, using 8-bit color values from the 128-color palette in CTIA or the 256-color palette in GTIA, with hues and luminances selected via the register values, missiles often sharing playfield colors (e.g., COLPF3 for a "fifth player" mode). Once processed, the sprite pixels are merged with the playfield generated by ANTIC, overlaying it according to priorities set in the PRIOR (D01B)register,whichdefinesafivelayerhierarchy(playfieldplanesPF0PF3,playersP0P3,andbackground)wherespritescanappearbehind,infrontof,orblendedwithspecificplayfieldelements(e.g.,bit03valueslikeD01B) register, which defines a five-layer hierarchy (playfield planes PF0–PF3, players P0–P3, and background) where sprites can appear behind, in front of, or blended with specific playfield elements (e.g., bit 0–3 values like %1000 prioritize PF0 over P0 over PF2 over P3). In GTIA, bits 6–7 of PRIOR enable enhanced modes when paired with ANTIC mode F (luminance-only playfield): mode 9 provides 16 discrete luminance levels of a single hue for smoother gradients; mode 10 uses nine color registers for 9 hues and 9 luminances; and mode 11 offers 16 hues at a single luminance, all of which integrate PMG by adding their colors or luminances atop the playfield without altering the core sprite pipeline. These GTIA modes expand blending flexibility beyond CTIA's uniform overlay, allowing up to 16 color changes per scanline in high-resolution contexts. The GRACTL (D01D) register (bits 0 for players, 1 for missiles) latches and enables the graphics data, ensuring synchronization. Performance-wise, the system supports up to eight sprites (four players plus four missiles) per scanline, with ANTIC's DMA stealing approximately 2 cycles per sprite (totaling ~16 cycles in a 114-cycle NTSC line), leaving ample CPU time for updates but introducing contention in complex scenes. Horizontal repositioning is instantaneous via register writes, effective mid-scanline after a 3–5 color clock delay, while vertical movement requires shifting the entire RAM buffer, incurring ~4 ms overhead for a full 256-byte player in single-line mode—a legacy of "racing the beam" techniques where the CPU must preload data before each scanline in dynamic displays. CTIA and GTIA share this pipeline, though GTIA's expanded modes slightly increase processing latency in luminance-blended scenarios due to additional hue-luminance separation.

Collision Detection and Response

In the CTIA and GTIA chips, collision detection occurs during the rendering of player-missile graphics, where pixel-level checks are performed per color clock cycle—approximately 560 nanoseconds (NTSC color clock at 1.79 MHz), with PAL systems operating at about 1.77 MHz. These checks compare the bits of player and missile sprites against the playfield bits and other sprites, identifying overlaps only within the visible screen region (horizontal positions $22 to $DD and scanlines 8 to 247), excluding blanking periods. This hardware-based process offloads collision computation from the CPU, enabling efficient real-time detection in games. Upon detecting a collision, the GTIA sets dedicated latches in its internal registers to record the event, such as player-playfield, missile-playfield, player-player, or missile-player overlaps. Software responds by polling dedicated collision registers (e.g., D02Eforplayer0vs.playfield)eitherinthemainprogramlooporviaDisplayListInterrupts(DLIs)tocheckforsetbits;forinstance,adevelopermightuseabitmaskoperationlikeif(PEEK(D02E for player 0 vs. playfield) either in the main program loop or via Display List Interrupts (DLIs) to check for set bits; for instance, a developer might use a bitmask operation like `if (PEEK(D02E) & %1111) > 0 then ...` to isolate specific interactions and trigger game logic, such as object destruction or scoring. To reset the latches after handling, the CPU writes to the HITCLR register, preventing persistent flags from accumulating. In GTIA, this latching mechanism is faster and more reliable than in CTIA, reducing the likelihood of missed events due to timing sensitivities in the earlier chip's priority and signal processing. Despite these capabilities, has inherent limitations, including the absence of vertical resolution—only horizontal overlaps are sensed, requiring software to manage vertical positioning manually. False positives can arise, particularly with merged missiles where overlapping sprites may incorrectly register as collisions even without playfield interaction. Workarounds include double-buffering sprite positions to synchronize updates with scanlines, minimizing timing artifacts and erroneous detections in dynamic scenes. These constraints highlight the need for careful programming to achieve accurate interaction simulation in 8-bit applications.

GTIA Enhancements

New Color Display Modes

The GTIA introduced three exclusive graphics modes—9, 10, and 11—that reinterpret the four-bit pixel data supplied by the ANTIC chip, enabling enhanced color and luminance options not available in the CTIA's standard operations. These modes are activated by setting the high bits of the PRIOR register (D01B): bits D7=0 and D6=1 (&#36;40–&#36;7F) for Mode 9, D7=1 and D6=0 (&#36;80–BF) for Mode 10, and D7=1 and D6=1 (C0C0–FF) for Mode 11. All three modes operate at a resolution of 80 pixels wide by 192 lines tall, based on ANTIC's Graphics Mode F (luminance-only data), and require software detection of the GTIA chip, as the CTIA produces unpredictable multicolored artifacts when these PRIOR values are used. Mode 9 provides 16 levels of a single hue applied to the playfield, creating a monochrome-like effect suitable for detailed shading in artwork. The hue is derived from the background color register (COLBK, $D01A), while the four-bit ANTIC data directly specifies the value (0–15), with 0 being black and 15 the brightest. Player and use their independent color registers, allowing additional hues beyond the playfield's single-hue . This mode is ideal for applications requiring subtle tonal variations, such as black-and-white simulations or high-contrast illustrations. Mode 10 employs nine fixed colors for the playfield, selected from the system's color registers (background, four playfield, and four player colors at D012D012–D01A), offering a limited but vibrant palette for multicolored scenes. ANTIC's four-bit data selects among these: values 0 for background, 1–4 for playfield colors 0–3, and 5–8 for player colors 0–3, with values 9–15 remapping to 1–7 to avoid unused slots. Player and missile sprites use their independent color registers (D012D012–D015) for coloring, functioning as in standard modes. This restriction limits the playfield to nine colors but enables versatile use of the registers. Mode 11 delivers 15 distinct hues against a background (from value 0), with all playfield elements using the full 128-color palette for maximum vibrancy. The background register provides a fixed for the entire display, while ANTIC selects the hue: value 0 yields ( 0), and 1–15 map to hues 1–15 at the chosen , effectively providing 15 colored levels plus . Player and sprites retain their independent color registers (D012D012–D015), allowing them to appear in any of the 128 colors regardless of playfield , which supports dynamic overlays in complex scenes. Notably, playfield collisions are disabled in this mode, simplifying interaction handling. These modes' implementation via the PRIOR register's high bits ensures backward compatibility fallback to standard operation if bits are not set, but their sprite limitations—such as background-only rendering in Mode 10 or luminance-only in Mode 9—necessitate careful design for games and applications. A prominent example is Rescue on Fractalus! (1984), which leverages Mode 11 for its fractal mountain landscapes, using the 15-hue capability to render varied terrain colors with fixed brightness for atmospheric depth during flight sequences.

Performance Improvements over CTIA

The GTIA chip addressed a key alignment issue present in the CTIA by eliminating the half-color-clock shift that misaligned player and missile sprites relative to the playfield graphics, particularly in high-resolution modes like ANTIC mode 8, thereby ensuring precise pixel-perfect positioning without software workarounds. This fix improved sprite rendering accuracy, allowing developers to achieve better overlap and visual consistency in games and applications that relied on exact synchronization between sprites and background elements. In terms of color capabilities, the GTIA expanded the available palette from the CTIA's 128 colors (16 hues with 8 levels) to 256 colors by supporting all four bits in its special modes, such as mode 9, which enables 16 values for a single hue or 16 hues at a fixed . Additionally, the GTIA incorporated improved chroma encoding optimized for both and PAL standards, resulting in more stable and accurate color reproduction compared to the CTIA's limitations in handling -chrominance separation. Collision detection in the GTIA saw significant reliability enhancements over the CTIA, with reduced instances of dropped detections due to more precise latching of collision registers that occurs faster during the electron beam sweep, ensuring that hits are captured consistently within visible scan line regions (horizontally 2222-DD and vertically 0808-F7). This upgrade minimized false negatives in dynamic scenarios, such as fast-moving sprites, by improving the timing of register updates and priority logic, which had been prone to errors in the CTIA. The GTIA also refined the accuracy of the VDELAY register ($D01C), providing finer control over vertical delay for sprite positioning and display list interrupts, which allowed for more precise two-line resolution masking on odd scan lines and better synchronization with ANTIC's DMA fetches. Following the introduction of the GTIA in late 1981, Atari ceased production of the early CTIA variants that suffered from these alignment and detection bugs, standardizing on the revised chip for all subsequent 400/800 models and upgrades.

Known Limitations and Bugs

Hardware Constraints and Workarounds

The CTIA and GTIA chips in Atari 8-bit computers support a limited set of eight sprites in total, comprising four player sprites and four sprites, each with a maximum width of eight pixels but variable height determined by software. These sprites lack dedicated hardware capabilities, requiring the 6502 CPU—operating at 1.79 MHz—to manually shift sprite data within dedicated 2 KB memory areas for vertical positioning, which can constrain real-time animations in complex scenes. Additionally, playfield rendering is restricted to a maximum of four simultaneous colors from a 128-color palette (16 hues across eight luminances) in standard modes, with support available in specific ANTIC modes (e.g., GR.7 and GR.8), where the ANTIC chip fetches data via display lists for coloring by CTIA/GTIA, often leading to flicker in multi-color displays without additional techniques like screen banking. To mitigate these constraints, programmers employed display list interrupts (DLIs), which trigger at specific scan lines to enable mid-screen modifications such as palette swaps or sprite repositioning, allowing for dynamic color transitions that exceed the four-color limit in segmented displays. Kernel routines, implemented as chained DLIs, synchronize operations with the electron beam's horizontal blanking period—often using the WSYNC register ($D40A) for precise timing—facilitating line-by-line control over graphics updates and reducing visible artifacts in or animated effects. Shadow registers in RAM, such as those for color intensities at locations 708–712, served as software mirrors of hardware registers, preventing operating system overwrites during direct POKE operations and enabling stable, repeated access without hardware reads. These hardware limitations fostered a distinctive programming paradigm on Atari systems, emphasizing interrupt-driven techniques and cycle-precise code to maximize visual complexity within tight constraints, a style that persists in modern emulators like Altirra, which accurately replicates CTIA/GTIA behaviors for authentic reproduction of era-specific software.

Specific Defects in Revisions

The CTIA chip exhibited a notable alignment defect in its sprite rendering, where players and missiles were offset by half a color clock relative to the playfield graphics in certain modes, such as graphics mode 8, resulting in a one-pixel misalignment. This issue stemmed from internal timing discrepancies in the CTIA's video processing pipeline, affecting precise positioning in games and applications relying on sprite-playfield synchronization. Software developers often had to account for this misalignment in positioning. In later revisions of the GTIA, particularly those used in Chinese-manufactured PAL XE models from production weeks 9040 to 9152, a fabrication error caused striped artifacts in GTIA-specific graphics modes 9 through 11. These modes, which enable multicolored character and displays, displayed incorrect values, manifesting as horizontal stripes due to faulty internal color decoding logic. The defect did not impact basic functionality but degraded visual quality in high-resolution multicolored output, prompting to recommend replacement with earlier GTIA revisions such as CO14889 revision 1A. Additional documented anomalies include potential overflow behavior in the VDELAY register under configurations, leading to unexpected vertical delay wraparound that could disrupt scanline timing in custom display setups. Similarly, the CONSPK register for console speaker control occasionally produced erratic tone glitches immediately following power-up, attributable to initialization transients in the chip's audio output circuitry. Remedies for these defects primarily involved software workarounds, such as accounting for misalignment in CTIA or palette tweaks to mitigate issues in affected GTIA modes. Hardware modifications were uncommon due to the chips' integration, though chip swaps resolved the PAL GTIA stripe problem effectively. Modern emulators like Altirra accurately model these revision-specific behaviors, including the Chinese GTIA fault, to preserve authentic reproduction, whereas some older emulators may incompletely replicate PAL-specific artifacts.

References

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