Community hub
Recent from talks
Knowledge base stats:
Talk channels stats:
Members stats:
HLH Orion
The Orion was a series of 32-bit super-minicomputers designed and produced in the 1980s by High Level Hardware Limited (HLH), a company based in Oxford, UK. The company produced four versions of the machine:
All four machines employed the same I/O sub-system.
High Level Hardware was an independent British company formed in early 1982 by David G. Small and Timothy B. Robinson. David Small was previously a founder shareholder and director of Oxford-based Research Machines Limited. Both partners were previously senior members of Research Machine's Special Projects Group. In 1984, as a result of that research, High Level Hardware launched the Orion, a high performance, microcodeable, UNIX superminicomputer targeted particularly at scientific applications such as mathematical modeling, artificial intelligence and symbolic algebra.
In April 1987 High Level Hardware introduced a series of Orions based upon the Fairchild Clipper processor but abandoned the hardware market in late 1989 to concentrate on high-end Apple Macintosh sales.
The original Orion employed a processor architecture based on Am2900-series devices. This CPU was novel in that its microcode was writable; in other words, its instruction set could be redefined. This facility was used to customise some Orions with instruction sets optimised to run the Occam and LISP programming languages or even to compute fractals.
The CPU consisted of an ALU that was built around the Am2901 bit-sliced microprocessor. To this a byte manipulation unit was added which could perform the shifting, rotating and masking operation required for handling eight and sixteen bit data. Additional logic was provided to support both signed and unsigned two's complement comparisons in a single operation, multiple precision arithmetic and floating point normalization. Most operations could be performed in 150 ns, however the cycle time was variable from 125 ns to 200 ns under microprogram control so that timing could be optimized. A microsequencer, based around the Am2910, directed the control flow through the microprogram. It could perform branches, loops and subroutine calls most of which could be conditional on any of several CPU status conditions.
The CPU instruction decoder, decoded machine level instructions (as opposed to micro-instructions). This was achieved by using map tables held in fast parity checked RAM which mapped one byte opcodes onto micro-instruction addresses. Control was transferred to these addresses using a special sequencer operation which was performed in parallel with other CPU functions. Hence instruction decoding overlapped instruction execution.
An escape mechanism was provided to allow the instruction set to be expanded beyond the 256 entries selected by any one opcode. A further mechanism existed to switch between several sets of dispatch tables, allowing the machine to support multiple instruction sets concurrently. Using this mechanism a different instruction set could be selected each time a context switch occurred. This mechanism was also used to implement privileged instruction, dynamic profiling (for performance monitoring) and multiple CPU modes (e. g. User and Kernel).
Hub AI
HLH Orion AI simulator
(@HLH Orion_simulator)
HLH Orion
The Orion was a series of 32-bit super-minicomputers designed and produced in the 1980s by High Level Hardware Limited (HLH), a company based in Oxford, UK. The company produced four versions of the machine:
All four machines employed the same I/O sub-system.
High Level Hardware was an independent British company formed in early 1982 by David G. Small and Timothy B. Robinson. David Small was previously a founder shareholder and director of Oxford-based Research Machines Limited. Both partners were previously senior members of Research Machine's Special Projects Group. In 1984, as a result of that research, High Level Hardware launched the Orion, a high performance, microcodeable, UNIX superminicomputer targeted particularly at scientific applications such as mathematical modeling, artificial intelligence and symbolic algebra.
In April 1987 High Level Hardware introduced a series of Orions based upon the Fairchild Clipper processor but abandoned the hardware market in late 1989 to concentrate on high-end Apple Macintosh sales.
The original Orion employed a processor architecture based on Am2900-series devices. This CPU was novel in that its microcode was writable; in other words, its instruction set could be redefined. This facility was used to customise some Orions with instruction sets optimised to run the Occam and LISP programming languages or even to compute fractals.
The CPU consisted of an ALU that was built around the Am2901 bit-sliced microprocessor. To this a byte manipulation unit was added which could perform the shifting, rotating and masking operation required for handling eight and sixteen bit data. Additional logic was provided to support both signed and unsigned two's complement comparisons in a single operation, multiple precision arithmetic and floating point normalization. Most operations could be performed in 150 ns, however the cycle time was variable from 125 ns to 200 ns under microprogram control so that timing could be optimized. A microsequencer, based around the Am2910, directed the control flow through the microprogram. It could perform branches, loops and subroutine calls most of which could be conditional on any of several CPU status conditions.
The CPU instruction decoder, decoded machine level instructions (as opposed to micro-instructions). This was achieved by using map tables held in fast parity checked RAM which mapped one byte opcodes onto micro-instruction addresses. Control was transferred to these addresses using a special sequencer operation which was performed in parallel with other CPU functions. Hence instruction decoding overlapped instruction execution.
An escape mechanism was provided to allow the instruction set to be expanded beyond the 256 entries selected by any one opcode. A further mechanism existed to switch between several sets of dispatch tables, allowing the machine to support multiple instruction sets concurrently. Using this mechanism a different instruction set could be selected each time a context switch occurred. This mechanism was also used to implement privileged instruction, dynamic profiling (for performance monitoring) and multiple CPU modes (e. g. User and Kernel).