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IBM System z9
IBM System z9
IBM System z9
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IBM System z9
IBM 2094 System z9
ManufacturerIBM
Product familyIBM Z
TypeMainframe
Release date2005; 20 years ago (2005)
Discontinued2008
PredecessorIBM eServer zSeries
SuccessorIBM System z10
History of IBM mainframes, 1952–present
Market name
Architecture
IBM 2094 System z9, open front with one Support Element
IBM 2094 System z9, rear
IBM 2094 System z9, open rear

IBM System z9 is a line of IBM mainframe computers. The first models were available on September 16, 2005. The System z9 also marks the end of the previously used eServer zSeries naming convention. It was also the last mainframe computer that NASA ever used.[1]

Background

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System z9 is a mainframe using the z/Architecture, previously known as ESAME. z/Architecture is a 64-bit architecture which replaces the previous 31-bit-addressing/32-bit-data ESA/390 architecture while remaining completely compatible with it as well as the older 24-bit-addressing/32-bit-data System/360 architecture. The primary advantage of this arrangement is that memory intensive applications like DB2 are no longer bounded by 31-bit memory restrictions while older applications can run without modifications.

Name change

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With the announcement of the System z9 Business Class server, IBM has renamed the System z9 109 as the System z9 Enterprise Class server. IBM documentation abbreviates them as the z9 BC and z9 EC, respectively.

Notable differences

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There are several functional enhancements in the System z9 compared to its zSeries predecessors. Some of the differences include:

Support Element & HMC

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The Support Element is the most direct and lowest level way to access a mainframe. It circumvents even the Hardware Management Console and the operating system running on the mainframe. The HMC is a PC connected to the mainframe and emulates the Support Element. All preceding zSeries mainframes used a modified version of OS/2 with custom software to provide the interface. System z9's HMC no longer uses OS/2, but instead uses a modified version of Linux with an OS/2 lookalike interface to ease transition as well as a new interface. Unlike the previous HMC application on OS/2, the new HMC is web-based which means that even local access is done via a web browser. Remote HMC access is available, although only over an SSL encrypted HTTP connection. The web-based nature means that there is no longer a difference between local console access and remote access, which means a remote user potentially has full control if authorized, allowing more flexibility for locating systems within data centers. IBM refers to the new HMC as a "closed platform" which does not allow the user to install software or access the command line interface to increase security and stability. The HMC is also firewalled by default with a minimal number of open ports for remote access.

Program Directed Re-IPL

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Program Directed Re-IPL is a new feature for Linux on System z9. It allows Linux systems running in an LPAR to re-IPL (reboot) themselves without operator intervention. This is accomplished by the System z9 storing the device and load parameters used to initially IPL the system.

DB2 and VSAM features

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DB2, VSAM, and other data storage formats achieve greater I/O performance thanks to a new System z9 feature called a MIDAW. Also, the System z9 introduces the zIIP, a new type of processor that accelerates certain specific DB2 tasks. Modified Indirect Data Address Words (MIDAWs) are a channel programming capability of the IBM System z9 processor range, and all subsequent ranges.[2] The MIDAW facility is an extension to the pre-existing Indirect Data Address Word (IDAW) channel programming capability, providing support for more efficient FICON channel programs. MIDAWs allow ECKD channel programs to read and write to many storage locations using one channel command, which means fewer signals up and down the channel are required to transfer the same amount of data. This reduction is particularly noticeable for Extended Format data sets, accessed through Media Manager. Examples include Extended Format Sequential data sets, Extended Format VSAM data sets and certain types of DB2 tablespaces. While each of these data set organizations have alternatives, each has a distinct set of advantages, whether in the area of performance, space saving (through hardware-assisted data compression), or scalability (by allowing an individual data set to exceed 4 GiB).

Java features

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Java 1.4 and higher support both 32-bit and 64-bit operation on z9. The System z9 also supports the zAAP processor, which allows most of the Java workload to be offloaded from the normal instruction processors. Java workloads executed by the zAAP processor do not count towards the IBM-rated capacity of the z9. This reduces the z9's total cost of ownership compared with other IBM platforms, as otherwise IBM would raise a customer's (software) license fees after installing an additional (hardware) processor. The zAAP also enables integration of new Java based Web applications with core z/OS backend database environment for high performance, reliability, availability, and security.

Cryptography

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The System z9 adds 128-Bit Advanced Encryption Standard (AES) to the list of hardware-based cryptographic algorithms. Other hardware-boosted features include additional random number generation and SHA algorithms. This specialized encryption hardware means System z9 potentially outperforms[citation needed] other platforms[which?] which must rely on encryption software.

LPARs

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The System z9 supports up to 60 LPARs, up from the previous maximum of 30.

Larger memory capacity

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The System z9 supports twice its immediate predecessors' maximum memory configurations: now up to 512 GB for the z9 EC and up to 64 GB for the z9 BC.

Concurrent system board replacement

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The System z9 supports nondisruptive processor and memory replacement. That means a technician can replace an entire system board[3] without ending any applications and without restarting any operating systems. In most configurations a System z9 can even manage this feat without any reduction in performance or capacity for the running applications.

4 Gbit FICON and FCP

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In May 2006, IBM added 4 Gigabit FICON and FCP support to the System z9 for faster I/O to storage devices. IBM also added a lower cost 2-port 4 Gbit FICON/FCP I/O adapter to the System z9 option list.

Smooth subcapacity increments

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Also in May 2006, IBM introduced subcapacity settings to its high end model. For the first time mainframe processors now allow small, smooth steps through the entire processor range. This feature allows IBM's customers to control their software costs precisely and to pay for only exactly as much capacity as they need without harsh price discontinuities at certain capacity increments. (IBM started offering variable subcapacity software pricing in 2000, and some other software vendors now offer similar terms, so hardware subcapacity settings are of primary interest when running so-called full capacity software products.)

Group capacity limits

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Available with z/OS Release 8, Group Capacity Limits allows an installation to define a group of LPARs within a single z9 or z10 machine whose capacity usage can be limited to a specific number of MSUs. Usage is based on the rolling 4 hour average CPU consumption, also in MSUs. A group need not necessarily be the same as an LPAR Cluster. LPARs can participate whether they are in a sysplex or not.

Separate processor pools

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While previous mainframe generations (including the predecessor zSeries z990) supported specialty processors, such as zAAPs and ICFs, these were all managed by PR/SM out of the same processor pool (Pool 2). The IBM System z9 EC introduced the concept of separate pools for different types of specialty processor. This greatly eases the tasking of managing and measuring the performance of the different processor types. With z9 (and IBM System z10) the following pools are defined:

  • 1 General-purpose processors
  • 3 IFLs
  • 4 zAAPs
  • 5 ICFs
  • 6 zIIPs

Pool 2 is no longer used.

In addition to these 5 pools of characterized processors, there are three other categories of processor:

  • Service Assist Processors (for assisting with I/O operations) which all machines have.
  • Spare processors (to replace characterized processors in the event of a failure) which all machines have.
  • Unpurchased processors (which can be purchased and then characterized) which all but the most fully characterized machines have.

Models

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IBM System z9 product line
2004 2005 2006 2007 2008
Main frames
Dual-rack zSeries z990 z9 S08 z10 EC
z9 S18
z9 S28
z9 S38
z9 S54
Single-rack zSeries z890 z9 S07 z10 BC
z9 R07

Enterprise Class

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The System z9 Enterprise Class server, formerly known as the System z9 109, was the flagship of the System z9 series until the announcement of the IBM System z10. The most powerful model, the 2094-S54, achieves approximately twice the transactional performance of its most powerful predecessor, the zSeries z990 (2084-332). A single 2094-S54 machine provides up to 54 main processors (plus scores of secondary processors), at least two spare main processors, and up to 512 GB of main memory. Minimum memory is 16 GB.

The System z9 EC is available in five hardware model configurations:

  • 2094-S08
  • 2094-S18
  • 2094-S28
  • 2094-S38
  • 2094-S54

Business Class

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On April 27, 2006, IBM announced the System z9 Business Class, also known as the z9 BC, as the successor to the zSeries z890 mainframe. IBM is positioning the z9 BC as a midrange system with a low cost of acquisition with up to twice the performance of the z890. The first z9 BCs began shipping on May 26, 2006. The z9 BC supports up to seven main processors (plus a dozen or more secondary processors). While the z9 BC can provide general purpose central processors (CPs), IBM is actively marketing the use of low cost specialty processors such as IFLs, zAAPs, and the new zIIPs. (Every z9 BC can support at least three specialty engines even when maximally configured with CPs.) The z9 BC comes with a minimum of 8 GB of RAM and is expandable up to 64 GB. IBM offers kits that allow current z800 and z890 customers to upgrade to the z9 BC. A z9 BC customer can then upgrade to the z9 EC if extra capacity is required.

The System z9 BC is available in two hardware model configurations:

  • 2096-R07
  • 2096-S07

The seven System z9 hardware configurations support scores of software model configurations: 2094-401 through 2094-754 for the EC and 2096-A01 through 2096-Z04 for the BC (plus IFL-only models).

Pricing

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The acquisition price for the System z9 ranges from "about $100,000" (IBM reported U.S. 2006 price, 2096-A01 model) to millions of dollars for the 2094-S54. (These prices are for new installations. Generally there are lower prices when upgrading from the immediate predecessor model, more like many software products and quite unlike most other hardware products.) For comparison, when new, the zSeries z890 had a starting price about twice that of the System z9 BC.

Successor machine

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In February 2008, the IBM System z10 Enterprise Class was announced (and later in 2008 the z10 Business Class (BC) was announced). The z10 features quad-core technology, for up to 64 processors. The z10 has a number of power-saving, space-saving and throughput improvements compared to the z9.[4]

References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

IBM System z9

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from Grokipedia
The System z9 is a family of mainframe servers from , consisting of the Enterprise Class (z9 EC) and (z9 BC) models, designed for high-performance, scalable, and secure enterprise computing workloads. Introduced in July 2005, the z9 EC (machine type 2094) succeeded the zSeries 990 and was built on the 64-bit , featuring a with up to four books for a maximum of 54 processor units (PUs) across five models (S08 to S54). The z9 EC supported up to 60 logical partitions (LPARs), 512 GB of memory, and enhanced I/O capabilities including up to 1,024 channels and 64 self-timed interfaces (STIs) at 2.7 GB/s each. In April 2006, announced the z9 BC (machine type 2096) as a more compact variant targeted at small- to medium-sized enterprises, offering two models (R07 and S07) with up to eight PUs, 64 GB of memory, and support for up to 30 LPARs. Key technologies in the System z9 emphasized (RAS), including redundant I/O interconnects for non-disruptive maintenance, the ability to remove books without system downtime, and the Server Time Protocol (STP) for precise time synchronization across LPARs. Security features were bolstered by the Crypto Express2 and the CP Assist for Cryptographic Function (CPACF) integrated into processors, enabling hardware-accelerated encryption for data in transit and at rest. The architecture also introduced innovations like multiple subchannel sets (MSS) for expanded device addressing (up to approximately 128,000 addresses) and the Modified Indirect Data Address Word (MIDAW) facility to optimize I/O efficiency for large-block transfers. The System z9 supported a wide range of operating systems, including , , z/VSE, and , facilitating consolidation of workloads from distributed systems onto a single mainframe for cost savings and improved manageability. Capacity upgrades were flexible via options like Capacity Upgrade on Demand (CUoD) and On/Off Capacity on Demand, allowing dynamic scaling without hardware changes. Overall, the z9 family represented IBM's focus on on-demand , enabling businesses to handle mission-critical applications with high transaction volumes while reducing operational complexity and storage requirements.

Overview

Announcement and Development

The IBM System z9 was developed as the direct successor to the zSeries 990 (z990) and z890 mainframes, evolving 's enterprise server lineup to address escalating computational demands in the mid-2000s. Announced on July 27, 2005, the initial System z9 Enterprise Class (z9 EC) model became generally available with first customer shipments on September 16, 2005, following three years of intensive development involving thousands of engineers focused on enhancing core mainframe reliability and scalability. This release also introduced the broader "System z" branding for 's mainframe family, shifting from the previous eServer zSeries nomenclature to emphasize integrated enterprise solutions. Key drivers for the System z9's development stemmed from enterprise needs for advanced virtualization to consolidate workloads, strengthened security to protect sensitive in shared environments, and optimized I/O to support high-volume and data analytics. IBM positioned the z9 EC as a critical bridge toward fuller exploitation of the 64-bit , allowing customers to expand memory utilization and processing efficiency for legacy and emerging applications without full system overhauls, thereby extending the value of existing mainframe investments. Complementing the z9 EC, announced the System z9 (z9 BC) on April 27, 2006, tailored for enterprise requirements with a more affordable entry point; first shipments of the z9 BC occurred on May 26, 2006. This dual-class approach underscored 's strategy to broaden mainframe accessibility while maintaining high standards for availability and performance across varying business scales.

Naming and Branding

The System z9 introduced a pivotal shift in branding for 's mainframe lineup, moving away from the eServer zSeries nomenclature that had been in use since to the new System z family designation. Announced on July 27, 2005, the System z9 Enterprise Class (z9 EC) was the inaugural product under this branding, signaling 's intent to position its mainframes as integral components of a unified enterprise systems portfolio. This change occurred alongside similar rebrandings for other server lines, such as eServer pSeries to System p and eServer iSeries to System i, creating a consistent "System" theme across 's hardware offerings. The rationale behind the to System z emphasized the integrated, holistic nature of IBM's enterprise solutions, moving beyond siloed product names to highlight and for on-demand business environments. By aligning the mainframe with the broader Systems portfolio, IBM aimed to broaden its appeal to diverse enterprise customers, including those seeking consolidated infrastructure for , data serving, and emerging workloads like . The "z" in System z specifically evoked "zero ," underscoring the platform's design for continuous and resilience. In terms of marketing impact, the System z9 branding reinforced the mainframe's reputation for "always on" reliability, with promotional efforts focusing on enhanced business continuity features such as improved redundancy, dynamic capacity upgrades, and robust disaster recovery capabilities. This positioning helped differentiate the System z9 in a competitive landscape, portraying it as a foundational element for mission-critical operations rather than a legacy technology. The subsequent announcement of the System z9 (z9 BC) on April 27, 2006, further solidified this branding by extending accessible entry points for mid-sized enterprises while maintaining the family-wide emphasis on integrated system reliability.

Technical Architecture

Processor and Cache Design

The IBM System z9 processors are based on the , a 64-bit that enables advanced capabilities for enterprise workloads. The core design features dual-core processor units (PUs) in higher-capacity models, such as the z9 Enterprise Class (EC) S54, where eight dual-core chips contribute to a total of up to 64 PUs per system, with 54 configurable as customer engines including Central Processors (CPs) for general-purpose , Integrated Facility for (IFLs) for workloads, Internal Coupling Facility processors (ICFs) for clustering, z Application Assist Processors (zAAPs) for Java offloading, and z Integrated Information Processors (zIIPs) for database processing. In contrast, the z9 (BC) employs single-core designs with up to eight PUs in a single book, configurable similarly but scaled for smaller environments. Clock speeds reach up to 1.72 GHz in EC dual-core configurations, with a cycle time of approximately 0.58 nanoseconds, while BC models operate at around 1.42 GHz to balance performance and cost. The is optimized for high-throughput , featuring a Level 1 (L1) cache of 512 KB per core—comprising 256 KB for instructions and 256 KB for , both 4-way set associative—in a store-through that facilitates quick access to frequently used . The Level 2 (L2) cache, shared across cores on the (MCM), provides 36 to 40 MB per book in a store-in buffer configuration, connected via a high-speed ring topology across books for coherent access and reduced latency. These processors incorporate superscalar, capabilities, allowing up to three instructions per cycle with dynamic reordering of memory accesses to minimize stalls. Branch prediction is enhanced by an 8K-entry Branch History Table (BHT) that is 4-way set associative, achieving high accuracy rates such as 98% in repetitive loops to reduce pipeline disruptions. Reliability, Availability, and Serviceability (RAS) are integral to the design, with chip-level redundancy including internal mirroring within each PU for error detection via asymmetric comparisons and two system-wide spare PUs for seamless failover. Additional RAS mechanisms encompass chip sparing in the cache structure, enhanced book availability for concurrent maintenance, and dynamic reconfiguration to maintain operations during failures. This processor architecture integrates with Logical Partition (LPAR) facilities to distribute workloads across engine types efficiently.

Memory Capacity and Configuration

The IBM System z9 Enterprise Class (z9-EC) featured a modular book-based , with up to four books per system, each supporting a maximum of 128 GB of central storage using technology for improved access speeds compared to prior generations. This design allowed for a total maximum physical capacity of 512 GB, doubling the 256 GB limit of the preceding z990 system, while configurations were available in 16 GB increments starting from a minimum of 16 GB. cards within each book were populated in pairs of 4 GB, 8 GB, or 16 GB units across eight slots, ensuring balanced interleaving for optimal performance and reliability through features like Chipkill error correction. In contrast, the System z9 Business Class (z9-BC) employed a single-book design with a maximum memory capacity of 64 GB, configured in 8 GB increments from a base of 8 GB, utilizing the same memory technology as the z9-EC for consistency in deployment and upgrades. This single-book approach simplified the architecture for midrange environments, with memory upgrades possible concurrently up to the installed physical limit via Capacity Upgrade on Demand (CUoD), though adding cards beyond initial installation required disruption. Both z9 models supported large page sizes of 1 MB alongside standard 4 KB pages, enhancing efficiency by reducing (TLB) overhead in logical partitions (LPARs) and improving for workloads like . The architecture leveraged 64-bit addressing to enable expansive spaces up to 16 EB system-wide, with dynamic storage reconfiguration allowing nondisruptive reallocation across LPARs via Processor Resource/System Manager (PR/SM). Features such as partial memory restart and reserved storage further ensured by permitting system operation with degraded memory components.

I/O Connectivity and Channels

The IBM System z9 introduced enhanced (I/O) connectivity designed to support high-volume and data-intensive workloads in enterprise environments. Its I/O leverages self-timed interconnects (STIs) operating at 2.7 GBps each, with up to 16 STIs per processor book, enabling aggregated bandwidth of up to 43.2 GBps per book across up to four books in the Enterprise Class (z9-EC) model. This setup, combined with redundant I/O interconnects, ensures by maintaining connectivity during hardware maintenance or upgrades. A key advancement in storage networking was the support for FICON Express4 channels, which operate at speeds of 1, 2, or 4 Gbit/sec, doubling the maximum link speed of the previous FICON Express2 in the z990. These channels facilitate native FICON for mainframe storage devices and (FCP) for open-systems attachments, with throughput improvements of up to 65% for read operations and 25% for mixed workloads compared to Express2. FICON Express4 cards provide up to four ports each using optics, supporting distances up to 10 km for long-wavelength (LX) variants and enabling features like N_Port ID (NPIV) for secure, shared access to storage resources. FCP integration over these channels allows point-to-point or connectivity, enhancing interoperability with and open environments while incorporating options for data-in-flight protection. The z9 supports up to 1,024 physical channel IDs (PCHIDs) and channel path identifiers (CHPIDs) in the z9-EC across four channel subsystems (CSSs), with 256 CHPIDs per CSS, significantly expanding device addressing via multiple subchannel sets (up to 127,750 per logical partition). In the (z9-BC), capacity is scaled to 512 CHPIDs across two CSSs. Networking connectivity is provided by OSA-Express2 adapters, supporting (GbE) at 1 Gbit/sec (LX/SX variants up to 5-10 km) and 10 GbE Long Reach (LR) at 10 Gbit/sec (up to 10 km), with up to 48 ports system-wide in the z9-EC and 24 in the z9-BC. These adapters include queued direct I/O (QDIO) for low-latency TCP/IP processing, jumbo frames, and Layer 2/3 bridging, optimizing without support in this generation. For Parallel Sysplex clustering, the z9 employs Internal Coupling Facility (ICF) processors, configurable up to 16 in the z9-EC or 7 in the z9-BC, which can be dynamically allocated from general-purpose central processors via Capacity Upgrade on Demand (CUoD). Coupling connectivity uses Internal Coupling (IC) channels or external links like Inter-System Coupling-3 (ISC-3) at 2 Gbit/sec (up to 20 km) and Internal Coupling Bay-4 (ICB-4) at 2 GBps aggregate (improved from 1 GBps in ICB-3 on the z990), supporting up to 64 links for multisystem configurations spanning up to 100 km with Server Time Protocol . This enhanced bandwidth and internal integration reduce latency in shared cache and structure operations, bolstering for multi-system environments.

Key Features

Virtualization and LPAR Capabilities

The IBM System z9 mainframe introduced advanced capabilities through its implementation of Logical Partitions (LPARs), managed by the Processor Resource/Systems Manager (PR/SM) . This allows the system to be divided into multiple isolated partitions, each capable of running independent operating system instances such as , , z/VSE, z/TPF, on System z, and Coupling Facility Control Code (CFCC). PR/SM treats the physical hardware as a unified (SMP) environment, enabling dynamic allocation of central processors (CPs), Integrated Facility for Linux (IFLs), Internal Coupling Facility (ICFs), application assist processors (zAAPs), and Integrated Information Processors (zIIPs) across partitions. Resources like and I/O channels can be shared or dedicated, with configurable weights and pools to optimize distribution, supporting server consolidation and . A key enhancement in the System z9 is its support for up to 60 LPARs in the Enterprise Class (z9-EC) models and up to 30 LPARs in the (z9-BC) models, organized across up to four Logical Channel Subsystems (LCSSs), each accommodating a maximum of 15 LPARs. This scalability facilitates the simultaneous execution of diverse workloads, including traditional mainframe applications, guests, and Java/database processing on specialty engines. Multiple Subchannel Sets (MSS) extend I/O addressing to approximately 128,000 devices per LCSS, with up to 63,750 subchannels per LPAR, enabling efficient resource sharing without performance degradation. The operating system further augments these capabilities by virtualizing hundreds of guest virtual machines within an LPAR, providing features like virtual I/O, HiperSockets for internal networking, and N_Port ID Virtualization (NPIV) for (FCP) sharing among instances. Dynamic reconfiguration is a cornerstone of System z9 virtualization, allowing nondisruptive adjustments to LPAR resources during operation. Features such as Dynamic Storage Reconfiguration (DSR) permit online additions or reallocations in increments as small as 1 GB, while concurrent processor conversions and I/O channel support Capacity Upgrade on Demand (CUoD) and Customer Initiated Upgrade (CIU) without system downtime. Enhanced Book Availability () enables the removal and replacement of processor books while maintaining LPAR operations through reserved resources and remapping. These mechanisms, combined with the Server Time Protocol (STP) for precise timing synchronization across partitions, ensure continuous availability and workload balancing, with PR/SM enforcing strict isolation to prevent interference between LPARs.

Security and Cryptography Enhancements

The IBM System z9 introduced significant advancements in hardware-based and , embedding cryptographic acceleration directly into the processor to support high-performance encryption for enterprise workloads such as secure sockets layer (SSL) transactions, virtual private networks (VPNs), and data protection. These enhancements leverage the Central Processor Assist for Cryptographic Functions (CPACF), an integrated on every central processor (CP) and Integrated Facility for (IFL), enabling efficient symmetric key operations without offloading to external hardware. Complementing this, the Crypto Express2 feature provides robust support for the Common Cryptographic Architecture (CCA), ensuring secure key management in a tamper-resistant environment. The CPACF facilitates hardware-accelerated processing for key symmetric algorithms, including (AES) with 128-bit keys, (DES) in single, double, and triple-length variants (TDES), and Secure Hash Algorithm (SHA) variants such as and SHA-256. It introduces specialized instructions like KM and KMC for AES-128 encryption/decryption and , KIMD and KLMD for SHA-256 hashing, and KMC for pseudorandom number generation (PRNG), all optimized for clear-key operations to achieve high throughput in applications requiring frequent cryptographic tasks. AES and SHA functions are enabled by default, while DES/TDES require a no-charge feature code (FC 3863) for activation, allowing seamless integration with operating systems like V1.6 and distributions. This design ensures low-latency performance for bulk data encryption, reducing CPU overhead compared to software-only implementations. CCA support is realized through the Crypto Express2 coprocessor, which offers tamper-resistant secure key storage certified to FIPS 140-2 Level 4 standards, protecting keys against physical and logical attacks via encrypted storage under a master key and automatic zeroization upon tamper detection. Integrated with the Integrated Cryptographic Service Facility (ICSF) and Resource Access Control Facility (RACF), it enables secure key generation, distribution, and usage for functions like RSA operations up to 2048-bit keys, PIN processing, Derived Unique Key Per Transaction (DUKPT), and EMV 2000 compliance. The architecture supports up to eight Crypto Express2 features, each with two PCI-X adapters configurable across 16 domains, allowing isolated key environments for multiple logical partitions while facilitating standards-compliant key exchange, such as ISO/IEC 11770-3 for remote loading. Management is enhanced by the Trusted Key Entry (TKE) 5.0 workstation, providing a graphical interface for secure key operations. Enhanced secure boot mechanisms in the z9 ensure integrity during initialization by verifying and hardware components against trusted states, preventing unauthorized modifications. Pervasive extends protection to data in transit over I/O channels, utilizing CPACF and Crypto Express2 to encrypt traffic on Fibre Connection (FICON) interfaces at speeds up to 4 Gbps, thereby securing inter- communications without impacting performance. This integration with I/O connectivity supports high-bandwidth, encrypted data flows, such as 2.7 GB/s per self-timed interconnect (STI) link, fostering a comprehensive posture for mainframe environments.

Management and Hardware Support

The IBM System z9 employed the Hardware Management Console (HMC) and Support Element (SE) as primary tools for system management, enabling remote monitoring and control of the central processor complex (CPC) and logical partitions. The HMC, a dedicated appliance connected via Ethernet, provided a web-based interface for centralized administration across multiple z9 servers, supporting tasks such as resource allocation, performance monitoring via the System Activity Display, and automated problem notification through the Remote Support Facility with SSL encryption. The SE, integrated as redundant Lenovo ThinkPad workstations within the system frame, handled local hardware initialization, event buffering, and failover operations, complementing the HMC by allowing direct control of CPC power-on resets and activation profiles without disrupting ongoing workloads. Together, these components supported up to 32 HMCs per SE and facilitated secure, real-time status updates using server-push technology. Hardware maintenance on the z9 was enhanced by concurrent system board replacement capabilities, utilizing hot-swap technology to minimize . In the z9 Enterprise Class (z9-EC), Enhanced Book Availability (EBA) and Concurrent Book Repair (CBR) allowed the nondisruptive exchange of processor by evacuating resources to spares, enabling field replaceable units (FRUs) like and I/O components to be swapped while the system remained operational, without requiring an initial program load (IPL). Similarly, the z9 Business Class (z9-BC) supported hot-swap for elements such as power supplies, STI ports, and I/O interconnects through redundant designs, ensuring no impact on processing during repairs. This approach achieved , with over 95% of repairs executable concurrently via the Repair and Verify process guided by the HMC and SE. Program Directed Re-IPL further improved targeted maintenance by permitting selective restarts of individual partitions without affecting the entire CPC. This feature, exploitable by operating systems like on z9, used predefined load profiles in the HMC and SE to initiate controlled reinitializations, such as normal or clear IPLs, for error recovery or software updates. It integrated with dynamic LPAR adjustments, allowing administrators to reconfigure resources post-restart seamlessly.

Innovations and Software Support

Performance and Scalability Improvements

The IBM System z9 delivered up to 1.35 times the central processor (CP) performance compared to the preceding z990 generation, driven by architectural enhancements in and I/O subsystems. This gain was achieved through a larger L1 cache of 512 KB per processing unit (256 KB for instructions and 256 KB for data) and an expanded L2 cache reaching 40 MB per book, scalable to 160 MB across a four-book system, which minimized latency in data access for compute-intensive workloads. Concurrently, I/O improved with a 35% increase in self-timed interconnect (STI) bandwidth to 2.7 GBps per connection and the adoption of FICON Express4 channels operating at 4 Gbps, enabling up to 65% better throughput for all read or write large sequential native FICON operations. Scalability was enhanced through flexible subcapacity provisioning, offering 24 granular capacity settings (model capacity identifiers 401 through 608) for configurations with up to eight CPs, allowing organizations to increment processing power in fine increments without necessitating complete hardware upgrades. These settings, based on four-hour rolling averages under Workload License Charges (WLC), supported precise alignment of capacity with demand, reducing overprovisioning and associated costs. expansions to 512 GB and I/O connectivity upgrades further complemented this by providing balanced resource growth for expanding workloads. In multi-system environments, the z9 introduced logical partition (LPAR) group capacity limits, enabling administrators to define shared caps across groups of partitions to prevent resource contention in Parallel Sysplex clusters. Complementing this, separate processor pools for CPs, integrated facility for (IFLs), internal coupling facilities (ICFs), zAAPs, and zIIPs allowed independent weight management and dynamic reallocation, optimizing utilization in up to 32-system Parallel Sysplex setups with enhanced coupling links up to 2 GBps via ICB-4. These features collectively supported seamless scaling for high-availability configurations while maintaining workload isolation.

Database and Application Features

The IBM System z9 mainframe introduced significant optimizations for database management systems, particularly through its integration with DB2 9 for z/OS, which leveraged the platform's architecture to enhance data handling efficiency. DB2 9 implemented index compression as a dictionaryless, software-managed feature that compresses index data at the page level during writes, while decompressing it for reads in buffer pools. This capability achieved up to eightfold reductions in disk space for 32 KB page-sized indexes, substantially lowering storage and I/O costs for data warehousing applications. The System z9's processor design, including its support for larger index page sizes of 4 KB, 8 KB, 16 KB, and 32 KB, further minimized page splits and contention during sequential inserts, improving overall query performance without requiring hardware-specific acceleration for the compression itself. Additionally, DB2 9's support for indexes on expressions enabled optimized access paths for computed columns, such as caseless text searches, enhancing application responsiveness on the z9 platform. VSAM Record Level Sharing (RLS) on the System z9 facilitated high-performance data access in multisystem environments by enabling concurrent read and update operations across z/OS instances in a Parallel Sysplex configuration. This access mode utilized the coupling facility for record-level serialization and caching, allowing applications like and batch jobs to share VSAM datasets with full update capabilities while maintaining through forward recovery via DFSMStvs. On the z9, RLS support integrated seamlessly with the platform's sysplex capabilities, reducing lock contention and improving throughput for shared workloads compared to traditional VSAM access methods. Java application support on the System z9 was advanced through the introduction of the zSeries Application Assist Processor (zAAP), an optional specialty engine dedicated to executing Java workloads under z/OS, thereby offloading them from general-purpose central processors to expand capacity cost-effectively. The IBM SDK for Java on z9 exploited zAAP by routing eligible Java execution, including XML parsing, to these processors, with no associated software licensing fees for qualifying IBM products. The Just-In-Time (JIT) compiler in the SDK featured optimizations tailored to the z/Architecture, such as asynchronous method compilation, profiling-driven recompilation, and multiple optimization levels (from cold to scorching), which compiled Java bytecode into native code to reduce execution latency and boost throughput for standalone and enterprise Java applications. These enhancements allowed Java-based applications to scale efficiently on z9 hardware, supporting 64-bit addressing for larger memory footprints.

Models

z9 Enterprise Class (z9-EC)

The IBM System z9 Enterprise Class (z9-EC), designated as the model 2094 series, represents the high-end configuration within the z9 family, engineered for large-scale enterprise environments requiring maximum processing power and reliability. It supports up to 54 characterized processing units (PUs), configurable as central processors (CPs), integrated facility for (IFLs), internal coupling facilities (ICFs), zApplication Assist Processors (zAAPs), or zIntegrated Information Processors (zIIPs), enabling flexible allocation for diverse workloads. The z9-EC is available in five models: S08 (8 PUs), S18 (18 PUs), S28 (28 PUs), S38 (38 PUs), and S54 (54 PUs). Memory capacity extends to a maximum of 512 GB, distributed across up to four processor books with options for 4 GB, 8 GB, or 16 GB memory cards per book, facilitating scalable partitioning up to 60 logical partitions (LPARs). Designed specifically for mission-critical applications in sectors such as banking and , the z9-EC emphasizes full to ensure continuous operation, including enhanced book availability for concurrent book replacement, redundant I/O interconnects, dynamic oscillator switch-over, and power supplies with dual feeds. These features support high-availability environments like Parallel Sysplex, where system-managed coupling facility structure duplexing provides robust recovery mechanisms for enterprise and transaction handling. I/O connectivity is provisioned through up to three I/O cages, each accommodating up to 28 slots for features like FICON Express, OSA-Express, and Crypto Express2 adapters, allowing for extensive channel path management with up to 1024 CHPIDs. This model shares core architectural elements, such as 64-bit real and virtual storage support, with the z9 Business Class but scales to larger capacities for demanding consolidation and e-business scenarios.

z9 Business Class (z9-BC)

The IBM System z9 Business Class (z9-BC), designated as the 2096 model series, was announced on April 27, 2006, serving as the successor to the zSeries z890 and providing a cost-effective entry point into the System z platform for smaller businesses and departmental workloads. This mid-range server emphasized affordability and simplicity, enabling organizations to leverage mainframe reliability and performance without the scale of larger enterprise systems. The z9-BC employs a compact, single-frame design that matches the physical footprint of the z890, facilitating deployment in space-constrained environments through and an optional non-raised floor configuration. It features 8 physical processor units (PUs) total (one reserved as a system assist processor), configurable across two hardware models—R07 (maximum 3 central processors) and S07 (maximum 4 central processors)—with memory expandable to 64 GB in 8 GB increments starting from a base of 8 GB. These specifications allow for flexible configuration of central processors (CPs), integrated facility for (IFLs), internal coupling facilities (ICFs), and specialty engines like zAAPs and zIIPs. Integrated I/O features enhance efficiency by minimizing cabling requirements, including up to 16 self-timed interfaces (STIs) operating at 2.7 GBps for internal connectivity between processors, , and I/O subsystems, along with support for FICON Express4 channels. This design reduces installation complexity and relocation costs, particularly in environments with limited space for external cabling or directors. The z9-BC also provides non-disruptive upgrade capabilities to the z9 Enterprise Class for growing workloads.

Capacity Planning and Pricing

Subcapacity and Increment Options

The IBM System z9 introduced flexible subcapacity licensing options measured in Millions of Service Units (MSUs), enabling customers to pay for only the utilized processor capacity rather than the full hardware potential. This approach, part of the Enterprise Workload License Charges (EWLC), divides capacity into tiers (e.g., Levels 1-7 for 3-261+ MSUs and Tier A-F for 1-1501+ MSUs), allowing partial utilization in increments as small as 5% of full capacity without requiring hardware modifications. For instance, the z9 Enterprise Class (z9-EC) supports 24 additional low-end capacity settings for models with up to 8 central processors, providing granular MSU adjustments from 28 MSUs (capacity identifier 401) up to 2409 MSUs (identifier 754). On/Off Capacity on Demand (On/Off CoD) further enhances this flexibility by permitting temporary activation of additional processors for short-term workload peaks, with no permanent commitment. Customers can enable or disable central processors (CPs), Integrated Facility for Linux (), Internal Coupling Facilities (), and specialty engines like zAAPs and zIIPs via the Resource Link, incurring charges only for the excess MSUs above the permanent baseline multiplied by usage days (e.g., activating 13 MSUs for less than 24 hours on a z9 model results in a single MSU-day charge). This feature supports up to double the installed capacity, with a 60-minute for deactivation, and includes an administrative test option for validation without cost. These mechanisms enable smooth capacity upgrades from 5% to 100% of a model's potential through software-based adjustments, such as Customer Initiated Upgrades (CIU) or Capacity Upgrade on Demand (CUoD), avoiding disruptions and hardware changes. For the z9-EC, this allows scaling from 580 MIPS (Model S08) to 17,801 MIPS (Model S54) in increments, with up to 19% MSU reductions compared to prior z990 models. Similarly, the z9 (z9-BC) offers upgrades from 26 MIPS to 1782 MIPS across up to 7 processor units, maintaining compatibility with subcapacity licensing. Such options optimize costs for fluctuating workloads while ensuring scalability.

Processor Pools and Group Limits

In the IBM System z9 environment, processor pools enable the logical separation and management of different types of processing units (PUs) within a central processor complex (CPC), facilitating workload isolation in Parallel Sysplex configurations where multiple images share resources across coupled systems. These pools include dedicated groupings for central processors (CPs) handling general workloads, integrated facility for (IFL) processors for and environments, internal coupling facility (ICF) processors for sysplex data sharing, zApplication Assist Processors (zAAPs) for and XML processing, and zIntegrated Information Processors (zIIPs) for database and network workloads. By maintaining these as distinct pools, the z9 ensures that specialized workloads do not compete directly with general-purpose tasks, optimizing resource allocation in clustered setups without incurring additional software licensing charges for non-CP pools. Group capacity limits on the System z9 provide a mechanism to enforce total capacity boundaries across multiple logical partitions (LPARs) within a Parallel Sysplex, capping the aggregate million service units per hour (MSU/h) to prevent over-provisioning in multi-system environments. Defined through the Processor Resource/Systems Manager (PR/SM) via the Hardware Management Console (HMC), these limits apply to groups of LPARs running version 1.8 or later, using soft-capping based on a rolling four-hour average of CPU utilization to maintain compliance with defined MSU thresholds. In coupled z9 systems, this feature aggregates capacity across the sysplex, ensuring that the combined MSU usage of interconnected LPARs does not exceed the group limit, thereby avoiding unintended escalation in software costs while supporting scalable clustering. Reporting tools integrated with the z9 facilitate monitoring and compliance for software licensing in processor pool and group limit scenarios, focusing on peak usage metrics derived from actual resource consumption. The Resource Measurement Facility (RMF) generates partition data reports and coupling facility activity logs that track LPAR management time, dispatch utilization, and MSU peaks across the sysplex, enabling administrators to verify adherence to group caps. Additionally, the HMC provides real-time views of pool usage and capacity markers, while the Workload License Charge (WLC) reporting through IBM's Resource Link service aggregates four-hour rolling averages for subcapacity licensing, ensuring accurate billing based on verified peak demands without exceeding provisioned limits.

Legacy and Successors

Transition to z10

The IBM System z10 served as the direct successor to the System z9, marking a significant evolution in IBM's mainframe lineup with enhanced processing capabilities designed for enterprise-scale workloads. Announced on February 26, 2008, for the Enterprise Class (z10-EC) model and on October 21, 2008, for the (z10-BC) model, the z10 introduced quad-core processor chips that delivered substantial performance improvements over the z9's dual-core design. The z10-EC featured processors operating at 4.4 GHz, enabling up to 50% greater capacity on average compared to equivalent z9 configurations, while the z10-BC utilized the same quad-core architecture but at 3.5 GHz with configurable active cores for needs. A key aspect of the transition was the z10's full with z9 software environments, ensuring that applications and operating systems such as , , z/VSE, and distributions running on z9 could operate on z10 hardware with minimal or no modifications. This compatibility extended to instructions, ESA/390 mode support, and features like the MIDAW facility, allowing seamless migration without requiring extensive retesting or recoding. IBM's design maintained continuity for critical components, including cryptographic accelerators (Crypto Express2/3) and I/O interfaces (FICON Express and OSA-Express), which carried forward from z9 systems. Upgrade paths from z9 to z10 emphasized non-disruptive migrations through enhancements in Logical Partition (LPAR) management and dynamic resource allocation. Customers could perform concurrent upgrades, such as adding processors (CPs, IFLs, zAAPs, zIIPs), memory, or I/O features without system outages, leveraging Processor Resource/Systems Manager (PR/SM) for up to 60 LPARs and Dynamic I/O reconfiguration. Temporary capacity options like On/Off Capacity on Demand (CoD) and Capacity Backup (CBU) facilitated testing and phased transitions, while features like Concurrent Book Add and Enhanced Book Availability minimized downtime for larger-scale upgrades from z9 EC or BC models.

End-of-Life and Migration Considerations

The IBM System z9 Enterprise Class (z9-EC) reached its marketing withdrawal date on June 30, 2010, with end-of-service support extended until January 31, 2019. Similarly, the (z9-BC) was withdrawn from marketing on the same date, but with service discontinuance on January 31, 2012 for most models, though some configurations received extensions up to 2019 under specific support agreements. These timelines aligned with IBM's standard mainframe lifecycle policy, providing approximately five years of post-withdrawal service to facilitate orderly migrations without abrupt disruptions to mission-critical operations. Migration from the System z9 typically involved upgrading to the successor System z10 through IBM's hardware upgrade programs, such as Miscellaneous Equipment Special Bids (MES), which enabled processor swaps or full frame replacements to minimize and leverage trade-in credits for older equipment. Virtualization via offered another path, allowing z9 workloads to run as guest systems on z10 hardware with high compatibility, as the ensures binary-level upward compatibility for applications and operating systems like . Key considerations for legacy applications included verifying software levels against newer hardware requirements—such as updating to 1.10 or later for full z10 support—and testing for any dependencies on z9-specific features like certain cryptographic modules, though most enterprise workloads required minimal code changes due to the architecture's design for seamless transitions. Post-migration to modern IBM Z systems, such as the z16, z17 (announced April 8, 2025), and later, organizations gain access to advanced capabilities including quantum-safe cryptography (e.g., CRYSTALS-Kyber and algorithms integrated since the z16) to protect against future quantum threats, and on-chip AI acceleration via the Telum processor for real-time fraud detection and directly in . These enhancements address evolving security and performance demands, enabling z9 users to modernize without sacrificing the reliability of their , transaction, and data-intensive applications.

References

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  2. https://www.redbooks.ibm.com/redbooks/pdfs/sg246669.pdf
  3. https://www.redbooks.ibm.com/redbooks/pdfs/sg247241.pdf
  4. https://www.ibm.com/docs/en/announcements/archive/ENUS105-241
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  15. https://www.redbooks.ibm.com/redbooks/pdfs/sg247291.pdf
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  23. https://www.redbooks.ibm.com/redbooks/pdfs/sg247516.pdf
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  29. https://www.ibm.com/support/pages/ibm-mainframe-life-cycle-history
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  31. https://newsroom.ibm.com/2022-04-05-Announcing-IBM-z16-Real-time-AI-for-Transaction-Processing-at-Scale-and-Industrys-First-Quantum-Safe-System
  32. https://www.ibm.com/products/z/telum
  33. https://www.ibm.com/support/pages/system/files/inline-files/IBM%2520Mainframe%2520Life%2520Cycle%2520History%2520V3.0%2520-%2520April%25208%2C%25202025.pdf
  34. https://www.redbooks.ibm.com/abstracts/sg248525.html
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