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Intel 8255
Intel 8255
Intel 8255
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Intel D8255
Pinout of i8255

The Intel 8255 (or i8255) Programmable Peripheral Interface (PPI) chip was developed and manufactured by Intel in the first half of the 1970s for the Intel 8080 microprocessor. The 8255 provides 24 parallel input/output lines with a variety of programmable operating modes.

The 8255 is a member of the MCS-85 family of chips, designed by Intel for use with their 8085 and 8086 microprocessors and their descendants.[1] It was first available in a 40-pin DIP and later a 44-pin PLCC packages.[2] It found wide applicability in digital processing systems and was later cloned by other manufacturers. The 82C55 is a CMOS version for higher speed and lower current consumption.

The functionality of the 8255 is now mostly embedded in larger VLSI processing chips as a sub-function. A CMOS version of the 8255 is still being made[3] by Renesas but mostly used to expand the I/O of microcontrollers.

Similar chips

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The 8255 has a similar function to the Motorola 6820 PIA (Peripheral Interface Adapter) from the Motorola 6800 family, also originally packaged as 40-pin DIL. The 8255 provides 24 I/O pins with four programmable direction bits: one for Port A(7:0) (i.e., all pins in the port), one for Port B(7:0), one for Port C(3:0) and one for Port C(7:4). By contrast, the Motorola and MOS chips provide only 16 I/O pins plus 4 control pins, but the Motorola/MOS chips allow the direction (input or output) of all I/O pins to be individually programmed. Both have configurations that will do a certain amount of automatic handshaking and interrupt generation.

Other comparable microprocessor I/O chips are the 2655 Programmable Peripheral Interface from the Signetics 2650 family, the Z80 PIO, the Western Design Center WDC 65C21 (equivalent to the Motorola 6820/6821), and the MOS Technology 6522 VIA and 6526 CIA which had considerable additional functionality such as timers and shift registers.

Variants

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MHB8255A by Tesla

The industrial grade version of Intel ID8255A was available for US$17.55 in quantities of 100 and up.[4] The available Intel 8255A-5 version was for USD $6.55 in quantities of 100 or more.[5] The available 82C55A CMOS version was outsourced to Oki Electronic Industry Co., Ltd.[6] The available package from Intel branded 82C55 in 44-pin PLCC of sampling at fourth quarter of 1985.[7] In Eastern Europe, equivalent circuits were manufactured as the KR580VV55A in the Soviet Union and as the MHB8255A by Tesla in Czechoslovakia.

Applications

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The 8255 was widely used in many microcomputer/microcontroller systems and home computers such as the SV-328 and all MSX models. The 8255 was used in the original IBM PC,[8] PC/XT, PC/jr and clones, along with numerous homebuilt computers such as the N8VEM.

Function

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The 8255 gives a CPU or digital system access to programmable parallel I/O.[9] The 8255 has 24 input/output pins.[10] These are divided into three 8-bit ports (A, B, C).[11] Port A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit input/output port or as two 4-bit input/output ports or to produce handshake signals for ports A and B.

The three ports are further grouped as follows:

  1. Group A consisting of port A and upper part of port C.
  2. Group B consisting of port B and lower part of port C.

Eight data lines (D0–D7) are available (with an 8-bit data buffer) to read/write data into the ports or control register under the status of the RD (pin 5) and WR (pin 36), which are active-low signals for read and write operations respectively. Address lines A1 and A0 allow to access a data register for each port or a control register, as listed below:

A1 A0 Port selected
0 0 port A
0 1 port B
1 0 port C
1 1 control register

The control signal chip select CS (pin 6) is used to enable the 8255 chip. It is an active-low signal, i.e., when CS = 0, the 8255 is enabled. The RESET input (pin 35) is connected to the RESET line of system like 8085, 8086, etc., so that when the system is reset, all the ports are initialized as input lines. This is done to prevent 8255 and/or any peripheral connected to it from being destroyed due to mismatch of port direction settings. As an example, consider an input device connected to 8255 at port A. If from the previous operation, port A is initialized as an output port and if 8255 is not reset before using the current configuration, then there is a possibility of damage of either the input device connected or 8255 or both, since both 8255 and the device connected will be sending out data.

The control register (or the control logic, or the command word register) is an 8-bit register used to select the modes of operation and input/output designation of the ports.[12]

Operational modes of 8255

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There are two basic operational modes of 8255:

  • Bit Set/Reset mode (BSR mode).
  • Input/Output mode (I/O mode).

The two modes are selected on the basis of the value present at the D7 bit of the control word register. When D7 = 1, 8255 operates in I/O mode, and when D7 = 0, it operates in the BSR mode.

Bit Set/Reset (BSR) mode

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The Bit Set/Reset (BSR) mode is available on port C only. Each line of port C (PC7 - PC0) can be set or reset by writing a suitable value to the control word register. BSR mode and I/O mode are independent and selection of BSR mode does not affect the operation of other ports in I/O mode.[13]

8255 BSR mode
  • D7 bit is always 0 for BSR mode.
  • Bits D6, D5 and D4 are don't care bits.
  • Bits D3, D2 and D1 are used to select the pin of Port C.
  • Bit D0 is used to set/reset the selected pin of Port C.

Selection of port C pin is determined as follows:

D3 D2 D1 Bit/pin of port C selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

As an example, if it is needed that PC5 be set, then in the control word,

  1. Since it is BSR mode, D7 = '0'.
  2. Since D4, D5, D6 are not used, assume them to be '0'.
  3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
  4. PC5 has to be set, hence, D0 = '1'.

Thus, as per the above values, 0B (Hex) will be loaded into the Control Word Register (CWR).

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 1 1

Input/Output mode

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This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:[14]

  1. Mode 0 - Simple I/O
  2. Mode 1 - Strobed I/O
  3. Mode 2 - Strobed Bi-directional I/O

Control Word format

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I/O Control Word Format
  • D0, D1, D3, D4 are assigned for port C lower, port B, port C upper and port A respectively. When these bits are 1, the corresponding port acts as an input port. For e.g., if D0 = D4 = 1, then lower port C and port A act as input ports. If these bits are 0, then the corresponding port acts as an output port. For e.g., if D1 = D3 = 0, then port B and upper port C act as output ports.
  • D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected.
  • D5 & D6 are used for mode selection of Group A ( port A and upper port C). The selection is done as follows:
D6 D5 Mode
0 0 0
0 1 1
1 X 2
  • As it is I/O mode, D7 = 1.

For example, if port B and upper port C have to be initialized as input ports and lower port C and port A as output ports (all in mode 0):

  1. Since it is an I/O mode, D7 = 1.
  2. Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation.
  3. Port B and upper port C should operate as Input ports, hence, D1 = D3 = 1.
  4. Port A and lower port C should operate as Output ports, hence, D4 = D0 = 0.

Hence, for the desired operation, the control word register will have to be loaded with "10001010" = 8A (hex).

Mode 0 – simple I/O

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In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port.

The input/output features in mode 0 are as follows:

  1. Output ports are latched.
  2. Input ports are buffered, not latched.
  3. Ports do not have handshake or interrupt capability.
  4. With 4 ports, 16 different combinations of I/O are possible.

'Latched' means the bits are put into a storage register (array of flip-flops) which holds its output constant even if the inputs change after being latched. A buffer is a non-storage element that simply passes the current signal through when enabled.

The 8255's outputs are latched to hold the last data written to them. This is required because the data only stays on the bus for one cycle. So, without latching, the outputs would become invalid as soon as the write cycle finishes.

The inputs are not latched because the CPU only has to read their current values, then store the data in a CPU register or memory if it needs to be referenced at a later time. If an input changes while the port is being read then the result may be indeterminate.

Mode 0 – input mode

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  • In the input mode, the 8255 gets data from the external peripheral ports and the CPU reads the received data via its data bus.
  • The CPU first selects the 8255 chip by making CS low. Then it selects the desired port using A0 and A1 lines.
  • The CPU then issues an RD signal to read the data from the external peripheral device via the system data bus.

Mode 0 – output mode

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  • In the output mode, the CPU sends data to 8255 via system data bus and then the external peripheral ports receive this data via 8255 port.
  • CPU first selects the 8255 chip by making CS low. It then selects the desired port using A0 and A1 lines.
  • CPU then issues a WR signal to write data to the selected port via the system data bus. This data is then received by the external peripheral device connected to the selected port.

Mode 1 - Strobed Input/output mode

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When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1 (port A and port B can be initialised to operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1). Some of the pins of port C function as handshake lines.

For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines.

If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines.

The mode 1 which supports handshaking has following features:

  1. Two ports i.e. port A and B can be used as 8-bit i/o ports.
  2. Each port uses three lines of port С as handshake signal and remaining two signals can be used as i/o ports.
  3. Interrupt logic is supported.
  4. Input and Output data are latched.

Input Handshaking signals

1. IBF (Input Buffer Full) - It is an output indicating that the input latch contains information.
2. STB (Strobed Input) - The strobe input loads data into the port latch, which holds the information until it is input to the microprocessor via the IN instruction.
3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the data are input from the port by the microprocessor.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit programmed via the port PC4(port A) or PC2(port B) bit position.

Output Handshaking signals

1. OBF (Output Buffer Full) - It is an output that goes low whenever data are output(OUT) to the port A or port B latch. This signal is set to a logic 1 whenever the ACK pulse returns from the external device.
2. ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK signal is a response from an external device, indicating that it has received the data from the 82C55A port.
3. INTR (Interrupt request) - It is a signal that often interrupts the microprocessor when the external device receives the data via the signal. this pin is qualified by the internal INTE(interrupt enable) bit.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit programmed to enable or disable the INTR pin. The INTE A bit is programmed using the PC6 bit and INTE B is programmed using the PC2 bit.

Mode 2 - Strobed Bidirectional Input/Output mode

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Only port A can be initialized in this mode. Port A can be used for bidirectional handshake data transfer. This means that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0 or as handshaking for port B if group B is initialized in mode 1. In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller. Acknowledgement and handshaking signals are provided to maintain proper data flow and synchronisation between the data transmitter and receiver.

References

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Intel 8255

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The Intel 8255 is a programmable peripheral interface (PPI) chip, originally developed by Intel Corporation in the early 1970s as a general-purpose input/output (I/O) device for microprocessors such as the 8080 and 8085. It features 24 programmable I/O lines divided into three 8-bit ports (A, B, and C), enabling flexible interfacing with external peripherals like keyboards, displays, analog-to-digital converters, and sensors in microcomputer systems. The chip supports three distinct operating modes—Mode 0 for basic input/output, Mode 1 for strobed I/O with handshaking and interrupt capabilities, and Mode 2 for bidirectional data transfer on Port A—allowing configuration via control words written by the CPU to adapt to various application requirements. Housed in a 40-pin (DIP), the 8255 includes essential components such as data bus buffers for 8-bit bidirectional communication, read/write control logic, and three internal registers for port and mode selection, all TTL-compatible for direct integration with Intel's family. The later 8255A , introduced as an enhanced version, offers improved electrical characteristics including a maximum operating of 5 MHz and better immunity, while maintaining full compatibility with the original design. Programming involves sending a control word to set port directions (input or output) and modes, with subsequent I/O operations addressed via A0 and A1 pins for port selection. The 8255 series represented a foundational advancement in I/O expansion for early computing, serving as a versatile tool for peripheral interfacing in applications ranging from industrial automation to the initial waves of personal computers and embedded systems during the and . Its design influenced subsequent parallel I/O controllers, and compatible clones were produced by other manufacturers, extending its legacy in legacy hardware and modern emulations. Despite being superseded by more integrated solutions in contemporary systems, the 8255 remains a key example of modular peripheral design in microprocessor architecture.

History and Development

Origins and Design

The Intel 8255 Programmable Peripheral Interface (PPI) was developed in the early 1970s as a key component of Intel's MCS-80 family of microcomputer chips, introduced to support the 8080 microprocessor launched in April 1974. This family aimed to provide a complete set of support devices for building microprocessor-based systems, addressing the limitations of earlier designs like the 8008, which required extensive external logic for operations. The 8255 was specifically created to offer flexible parallel I/O capabilities, enabling efficient interfacing between the CPU and peripheral devices such as keyboards, displays, and sensors without relying heavily on discrete TTL components. Designed by engineer Peter Salmon, the 8255 was part of a broader effort to simplify and promote adoption of ecosystem. Development occurred concurrently with other peripherals like the 8251 USART and 8253 timer, with the 8255 originally slated for a different but renamed to 8255 before its was finalized to align with 8xxx for the MCS-80 series. The chip's emphasized programmability, featuring three independent 8-bit ports (A, B, and C) that could be configured via software for , or bidirectional modes, along with strobe and signals for controlled data transfer. This choice prioritized versatility and ease of integration, allowing a single chip to handle up to 24 I/O lines in various configurations to meet diverse application needs in embedded and control . The origins of the 8255 reflect Intel's strategic shift toward offering solutions for development, responding to customer feedback on the need for standardized I/O peripherals. By encapsulating common parallel interface functions into a single MOS integrated circuit, the chip reduced board space, power consumption, and design complexity compared to prior solutions using multiple discrete gates. Fabricated using Intel's NMOS process, it operated at speeds compatible with the 8080's clock rates, ensuring seamless system performance. An enhanced version, the 8255A, later improved timing characteristics and added features like higher output drive capability, but the original 8255 established the foundational design that became widely emulated in subsequent generations.

Release and Adoption

The Intel 8255 Programmable Peripheral Interface was introduced in the early 1970s as a key support component in Intel's MCS-80 family, designed specifically to complement the 8080 microprocessor released in 1974. By September 1975, it was fully documented and available for integration in microcomputer systems, providing versatile parallel I/O functionality in a single 40-pin package powered by +5V. The chip's adoption accelerated with the rise of hobbyist and commercial microcomputers, where its three 8-bit ports enabled straightforward interfacing for peripherals like keyboards, displays, and storage media without requiring custom hardware. It became a staple in early systems based on the 8080 and compatible Z80 processors, supporting applications from basic input scanning to interrupt-driven I/O operations. A prominent example of its integration occurred in the (model 5150), launched in 1981, where the 8255A variant on the system board handled keyboard data input via Port A (I/O 0x60), speaker and timer control via Port B (0x61), and status monitoring via Port C (0x62), while also supporting cassette I/O and printer signaling in expansion adapters. This configuration facilitated essential user interactions and peripheral connectivity in one of the first mass-market PCs. Beyond PCs, the 8255 found broad use in home computing platforms, notably all models of the standard introduced in , where it—or compatible implementations—managed inputs, paddle controls, and operations, often integrated into cost-reducing custom "MSX-Engine" ICs alongside sound and logic functions. Its reliability and programmability also drove adoption in industrial controllers and embedded systems throughout the , cementing its role in the transition from discrete logic to integrated peripherals.

Overview and Features

Purpose and Capabilities

The 8255 is a general-purpose programmable peripheral interface (PPI) designed for use in microcomputer systems to facilitate parallel operations between the and external devices. It functions as a versatile I/O adapter, enabling the connection of peripherals such as keyboards, displays, printers, and analog-to-digital converters by providing configurable digital ports for data transfer. The chip's primary purpose is to expand the limited I/O capabilities of early microprocessors like the 8080 and , allowing flexible interfacing without requiring dedicated hardware for each peripheral. At its core, the 8255 offers three 8-bit I/O ports (A, B, and C), delivering a total of 24 programmable lines that can be independently set as inputs or outputs via software commands. Port A supports 8 bits, Port B provides another 8 bits, and Port C can operate as a single 8-bit port or be split into two 4-bit sections (upper and lower) for finer control, such as generating timing signals or status flags. This structure supports up to 16 different I/O configurations in basic modes, making it suitable for applications ranging from simple switch monitoring to multi-device control in embedded systems. The ports interface through an 8-bit bidirectional data bus, with read/write logic ensuring compatibility with TTL-level signals in a 40-pin . The 8255's capabilities extend to three primary operating modes that enhance its utility for synchronized data exchange. In Mode 0 (basic I/O), ports function as simple latched outputs or unlatched inputs without handshaking, ideal for straightforward digital interfacing. Mode 1 (strobed I/O) introduces handshaking via dedicated Port C lines (e.g., output buffer full, input buffer full, acknowledge, and ), enabling reliable data transfer with peripherals that require signals. Mode 2 (bidirectional bus) applies only to Port A, allowing 8-bit data flow in both directions with five Port C lines for control, supporting advanced protocols like those in printer interfaces. Additionally, a Bit Set/Reset (BSR) mode permits individual on Port C independently of other operations, useful for status bit control or LED driving. Interrupt generation on Port C lines further allows efficient CPU notification of peripheral events, reducing polling overhead. These features collectively position the 8255 as a foundational component in and , compatible with Intel's 8-bit and higher microprocessors through standard control signals (RD, WR, CS, A0, A1, and RESET). Its programmable nature via a single control word register minimizes hardware complexity while maximizing adaptability for diverse I/O tasks in industrial control, , and early personal computers.

Key Specifications

The Intel 8255 is a general-purpose programmable I/O device featuring 24 parallel I/O lines organized into three 8-bit ports: Port A, Port B, and Port C, with Port C capable of being divided into two independent 4-bit ports. It supports three major operating modes (0, 1, and 2) for flexible configurations, including basic I/O, strobed I/O with handshaking, and bidirectional bus operation, along with bit set/reset functionality for individual pins. The device interfaces via an 8-bit bidirectional data bus and is designed for compatibility with 's 8080 family, enabling requests. Housed in a 40-pin dual in-line package (DIP), the 8255 operates on a single +5 V power supply with ±5% tolerance and is fabricated using NMOS technology, providing TTL-compatible logic levels. The 8255A variant draws a maximum supply current of 120 mA under typical operating conditions and dissipates up to 1 W of power. The device's I/O pins support sink currents up to 2.5 mA and source currents up to 250 μA, suitable for direct interfacing with TTL devices, though buffering may be required for heavier loads like Darlington transistor arrays. Key electrical and physical specifications are summarized in the following table:
ParameterValueUnitConditions/Notes
Package Type40-pin DIP-Ceramic or plastic variants available
Supply Voltage (VCC)+5 ±5%VSingle supply; ground (VSS) at 0 V
Supply Current (ICC)120 max (8255A)mAVCC = 5 V, TA = 0°C to 70°C
Input High Voltage (VIH)2.0 minVLogic 1 input threshold
Input Low Voltage (VIL)0.8 maxVLogic 0 input threshold
Output High Voltage (VOH)2.4 min (IOH = -400 μA)VFor ports A, B, C and data bus
Output Low Voltage (VOL)0.45 max (IOL = 1.7 mA)VFor ports A, B, C (data bus: 0.45 max at 2.5 mA)
Input Leakage Current±10 maxμAVIN = 0 V to VCC
Power Dissipation1 maxWTypical under full load
Operating Temperature0 to 70°CCommercial grade
I/O Pins24 (3 × 8-bit ports)-Programmable as input/output; Port C split into 4-bit upper/lower
These specifications enable the 8255 to handle diverse peripheral interfacing tasks, such as keyboards, displays, and sensors, while maintaining compatibility with early systems. Timing for read/write operations aligns with 8080 cycles, with access times typically under 230 ns for NMOS implementations.

Architecture

Internal Components

The Intel 8255A Programmable Peripheral Interface (PPI) features a modular internal designed to facilitate flexible I/O operations with microprocessors, primarily through an 8-bit data bus interface. At its core, the chip integrates a data bus buffer that serves as the primary interface between the system data bus and internal registers, allowing bidirectional data transfer to and from the . This buffer ensures efficient communication by latching data during read and write cycles, supporting the chip's role as a general-purpose I/O device. The read/write control logic forms another essential block, decoding input signals such as (CS), read (RD), write (WR), and address lines A1 and A0 to manage internal operations. This logic determines whether the chip is being accessed for reading from ports, writing to ports, or programming the control registers, thereby coordinating all data movements within the device. Complementing this are the and control logic sections, which independently manage the configuration and operation of the ports. The logic oversees Port A and the upper half of Port C (PC7-PC4), while Group B handles Port B and the lower half of Port C (PC3-PC0), enabling independent mode selection and direction control for each group via a single control word. Ports A, B, and C constitute the I/O endpoints, each comprising 8 bidirectional lines that can be programmed as inputs or outputs. Port A and Port B include dedicated output to hold data stable when configured for output, preventing glitches on the external lines during bus cycles. Port C, uniquely, is divided into two 4-bit nibbles (upper and lower), allowing finer-grained control for handshaking or status signals, and supports bit set/reset operations independently of the main modes. Additionally, logic is integrated to support Mode 1 and Mode 2, for example in Mode 2 bidirectional operations on Port A using –PC7 for control signals including requests based on strobe inputs, enhancing the chip's utility in -driven systems. These components interconnect via internal buses, with the control logics routing signals to configure port directions, data, and handle mode-specific behaviors like strobing in Mode 1. The overall illustrates these elements in a hierarchical flow: external signals enter through the control logic, which decodes and routes via the bus buffer to the appropriate port groups, ensuring isolation between input and output paths to maintain . This design allows the 8255A to support up to 24 I/O lines while minimizing external circuitry needs.

Pin Configuration

The 8255 is housed in a 40-pin (DIP), providing 24 programmable I/O lines divided into three 8-bit ports (A, B, and C), an 8-bit bidirectional bus, and control signals for with a bus. These pins enable flexible configuration for , or bidirectional operations depending on the programmed mode. The I/O ports occupy pins 1 through 24, allowing connection to peripheral devices such as keyboards, displays, or sensors. The control and address pins (25 through 30) manage register selection and transfer, while pins 31 through 38 form the bus for communication with the host processor. Power and ground pins complete the configuration, supporting a single +5V supply. The following table details the pin assignments, including numbers, names, types, and functions:
PinSymbolTypeFunction
1PA0I/OPort A lower bit (LSB)
2PA1I/OPort A bit 1
3PA2I/OPort A bit 2
4PA3I/OPort A bit 3
5PA4I/OPort A bit 4
6PA5I/OPort A bit 5
7PA6I/OPort A bit 6
8PA7I/OPort A upper bit (MSB)
9PB0I/OPort B lower bit (LSB)
10PB1I/OPort B bit 1
11PB2I/OPort B bit 2
12PB3I/OPort B bit 3
13PB4I/OPort B bit 4
14PB5I/OPort B bit 5
15PB6I/OPort B bit 6
16PB7I/OPort B upper bit (MSB)
17PC0I/OPort C lower bit (LSB)
18PC1I/OPort C bit 1
19PC2I/OPort C bit 2
20PC3I/OPort C bit 3
21PC4I/OPort C bit 4
22PC5I/OPort C bit 5
23PC6I/OPort C bit 6
24PC7I/OPort C upper bit (MSB)
25RESETInputActive-high reset; initializes all ports as inputs
26A1InputAddress input 1 for register selection
27A0InputAddress input 0 for register selection
28CSInputActive-low ; enables the device
29RDInputActive-low read; outputs data from 8255 to bus
30WRInputActive-low write; latches data from bus to 8255
31D0I/OData bus lower bit (LSB)
32D1I/OData bus bit 1
33D2I/OData bus bit 2
34D3I/OData bus bit 3
35D4I/OData bus bit 4
36D5I/OData bus bit 5
37D6I/OData bus bit 6
38D7I/OData bus upper bit (MSB)
39VCCPower+5V supply
40GNDPowerGround
All I/O pins are TTL-compatible and can be programmed individually or in groups via the . The RESET pin, when asserted high, sets all ports to input mode and clears internal registers, ensuring a safe startup state. Address lines A0 and A1, combined with CS, allow selection of Port A, Port B, Port C, or the during write operations. Read and write strobes (RD and WR) synchronize data transfers, with the data bus serving as the bidirectional pathway for control words and port data. This configuration supports integration into systems like the or 8085 microprocessor buses, where the 8255 acts as a memory-mapped or I/O-mapped device.

Registers and Programming

Ports and Control Register

The Intel 8255 Programmable Peripheral Interface (PPI) incorporates three 8-bit I/O ports labeled A, B, and C, along with an 8-bit , enabling flexible parallel data transfer between a and external peripherals. These components are addressed using the two least significant lines (A1 and A0) from the , allowing selection of Port A ( offset 0), Port B (offset 1), Port C (offset 2), or the (offset 3) relative to the device's base . The ports feature internal latches and buffers to handle data direction and timing, ensuring compatibility with 's family. Port A, consisting of eight bidirectional lines (PA0 through PA7), serves as a versatile data port configurable as either input or output through the control register. It includes an output latch for driving external loads when configured as an output and a buffer for reading data when in input mode, supporting all three operational modes (0, 1, and 2) of the 8255. In Mode 2 (bidirectional), Port A functions as a transceiver for two-way data exchange, with Port C providing associated control signals. Port B, also an 8-bit bidirectional port (PB0 through PB7), mirrors Port A's basic structure with input buffers and output latches but is restricted to Mode 0 (simple I/O) and Mode 1 (strobed I/O). It is commonly used for less critical peripheral connections due to its mode limitations compared to Port A, and its direction is independently programmable. In Mode 1, Port B can interface with handshaking signals from Port C's upper or lower , facilitating controlled data transfers. Port C comprises eight lines (PC0 through PC7), which can operate as a single 8-bit I/O port or be divided into two independent 4-bit : the upper nibble (PC4–PC7) and lower nibble (PC0–PC3). Each nibble supports individual direction control, allowing mixed configurations, and Port C lines often serve dual purposes as simple I/O in Mode 0 or as and signals (e.g., STB for strobe, IBF for input buffer full) in Modes 1 and 2. This flexibility makes Port C ideal for status monitoring or control functions in peripheral interfacing. The control register, an 8-bit write-only register, governs the configuration of all ports by accepting control words that define operational modes, port directions, and group activations. Writing to this register (with bit 7 set to 1 for mode control) programs the 8255's internal logic, dividing the ports into two groups—Group A (Ports A and upper C) and Group B (Ports B and lower C)—each with independent mode settings. Changes to the control register take effect immediately upon write operations, enabling dynamic reconfiguration during system runtime without resetting the device.

Control Word Format

The control word of the Intel 8255 is an 8-bit value loaded into the to configure the device's operating modes, port directions, or to set/reset individual bits in Port C. This register is accessed when the (CS) is active low and address lines A1 and A0 are both high, allowing the CPU to write the control word via the data bus. The format of the control word determines whether it configures I/O modes or performs bit set/reset (BSR) operations, with bit 7 (D7) serving as the distinguishing flag. When D7 is set to 1, the control word operates in mode definition format, enabling selection of one of three I/O modes (Mode 0, Mode 1, or Mode 2) for the port groups and specifying input or output directions for Ports A, B, and the two halves of Port C. The 8255 organizes its ports into two groups: (Port A and Port C bits 7-4) and (Port B and Port C bits 3-0). Mode selection applies to these groups, with Mode 2 available only for (bidirectional bus on Port A using Port C for handshaking). Bits 6 and 5 jointly define the mode for : 0X for Mode 0 (basic input/output, X=don't care), 10 for Mode 1 (strobed input/output), and 11 for Mode 2 (bidirectional). Bit 3 selects the mode for : 0 for Mode 0 or 1 for Mode 1 (Mode 2 not supported for ). Direction bits (0 for output, 1 for input) apply to the full ports in Mode 0, but in Modes 1 and 2, certain Port C bits are dedicated to control signals (e.g., strobes or interrupts), overriding direction settings for those bits. In Mode 2, bits 1 and 0 enable interrupts for Port A and Port B, respectively, instead of defining directions for Port C halves. The mode definition format is detailed in the following table:
BitFunctionDescription
7Mode Set Flag1 = Mode definition active; configures modes and directions.
6Group A Mode Select (MSB)0 = Mode 0; 1 = Mode 1 or 2 for Port A and upper Port C.
5Group A Mode Select (LSB)Combined with bit 6: 0 = Mode 0/1; 1 = Mode 2 (requires bit 6 = 1).
4Port A Direction0 = Output; 1 = Input (bidirectional in Mode 2).
3Group B Mode Select0 = Mode 0; 1 = Mode 1 for Port B and lower Port C.
2Port B Direction0 = Output; 1 = Input.
1Port C Upper (bits 7-4)0 = Output; 1 = Input (or interrupt enable in Mode 1/2).
0Port C Lower (bits 3-0)0 = Output; 1 = Input (or interrupt enable in Mode 1/2 for Port B).
For example, the control word 0x86 (binary 10000110) sets Port A to output in Mode 0, Port B to input in Mode 0, upper Port C to input, and lower Port C to output. When D7 is 0, the control word enters BSR mode, which exclusively affects Port C by setting or resetting a single bit without altering other configurations or modes. This mode is useful for generating control signals, such as strobes, on individual Port C lines while keeping the rest of the 8255 unchanged. Bits 6 through 4 are don't care, bits 3-1 form a 3-bit to select the Port C bit (000 for PC0, 001 for PC1, up to 111 for PC7), and bit 0 determines the action (0 to reset/clear the bit to 0, 1 to set the bit to 1). BSR mode does not support Port A or B and requires a separate control word for each bit operation. The BSR format is shown below:
BitFunctionDescription
7BSR Flag0 = BSR mode active.
6-4Don't CareIgnored in BSR.
3-1Port C Bit Select000-111 selects PC0-PC7.
0Set/Reset Control0 = Reset (0); 1 = Set (1).
For instance, to set PC2 to 1, the control word is 0x05 (binary 00000101). A reset of the 8255 (via the RESET pin high) initializes all ports as inputs and clears the control register, requiring a mode definition control word to begin operations.

Operating Modes

Bit Set/Reset Mode

The Bit Set/Reset (BSR) mode enables individual control over the eight bits of Port C in the 8255, allowing each bit to be set high or reset low independently without impacting other bits in Port C or the states of Ports A and B. This functionality is essential for applications needing granular signal manipulation, such as driving discrete outputs for status indicators, enabling interrupts, or interfacing with simple peripherals like switches and displays, thereby minimizing software overhead compared to reading-modifying-writing the entire port. Activation of BSR mode occurs by writing a dedicated 8-bit control word to the 8255's , distinct from the mode definition control words used for I/O operations. The BSR control word format prioritizes specificity to a single bit, with the following structure:
BitName/FunctionDescription
D7Mode Select0 (indicates BSR mode; 1 would select I/O mode configuration)
D6Don't CareIgnored by the device
D5Don't CareIgnored by the device
D4Don't CareIgnored by the device
D3Bit Select (MSB)Part of the 3-bit field (D3-D1) selecting the Port C bit (000 = PC0, 001 = PC1, ..., 111 = PC7)
D2Bit SelectPart of the 3-bit field selecting the Port C bit
D1Bit Select (LSB)Part of the 3-bit field selecting the Port C bit
D0Set/Reset1 to set the selected Port C bit high (logic 1); 0 to reset it low (logic 0)
This format ensures that only the targeted bit changes state upon execution of the output instruction to the , with the selected bit latching the new value until a subsequent BSR command alters it. For instance, to set PC4 high while leaving other Port C bits unchanged, the control word is 00010101 binary (05h decimal: D7=0, D6-D4=000, D3-D1=101 for bit 4, D0=1). The assembly instruction might be MVI A, 05H followed by OUT control_port, assuming the control register is mapped to control_port. Conversely, resetting PC4 requires 00010100 binary (04h: D0=0). These operations execute immediately and are non-destructive to the overall port configuration. BSR mode operates independently of the 8255's primary I/O modes (0, 1, or 2), allowing concurrent use for fine-tuned control signals even when Ports A or B are in or bidirectional configurations. However, it exclusively targets Port C bits programmed as outputs via a prior mode set control word; attempts to set or reset input-configured bits in Port C have no effect, as those lines function in high-impedance read mode. Upon device reset, all Port C bits default to input, requiring an initial mode set to enable output capability before BSR usage. This separation enhances the 8255's versatility in embedded systems for efficient bit-level interfacing without full port reconfiguration.

Mode 0: Basic Input/Output

Mode 0, also known as the basic input/output mode, provides the fundamental functionality of the Intel 8255 Programmable Peripheral Interface (PPI) by enabling straightforward data transfer between the CPU and external devices without handshaking or interrupt support. In this mode, the 24 I/O lines are divided into two 8-bit ports (Port A and Port B) and one 8-bit Port C, which can be configured as two independent 4-bit ports (upper and lower halves). Each port or port group can be individually programmed as either an input or output, allowing for 16 possible I/O configurations across the device. To operate in Mode 0, the CPU must first initialize the 8255 by writing an 8-bit control word to the , which defines the mode and port directions. The control word format is as follows: bit D7 must be set to 1 to indicate a mode set operation; bits D6 and D5 select the mode for Group A (Port A and upper Port C), with 00 specifying Mode 0; bit D4 determines Port A direction (0 for input, 1 for output); bit D3 sets the upper Port C direction (0 for input, 1 for output); bit D2 selects the mode for Group B (Port B and lower Port C), with 0 specifying Mode 0; bit D1 sets Port B direction (0 for input, 1 for output); and bit D0 sets the lower Port C direction (0 for input, 1 for output). For full Mode 0 operation across both groups, bits D6, D5, and D2 are all 0. Once programmed, data output occurs by writing to the appropriate port register, where the data is latched and held on the output pins until the next write, ensuring stable signals to peripherals. Input data is read directly from the pins without latching, reflecting the instantaneous state of the connected device. The latching mechanism for outputs in Mode 0 prevents data corruption during CPU write cycles, as the output buffers hold the previous value until explicitly updated, which is particularly useful for with devices like displays or simple sensors that require steady signals. Inputs, being unlatched, allow real-time monitoring but may require software polling to capture transient data. Access times are specified at 150 ns for data availability after a write, with a minimum read/write cycle time of 1 µs, synchronized to the system clock. This mode supports no additional control signals from Port C for handshaking, distinguishing it from higher modes, and is ideal for basic peripheral in systems like the Intel 8080-based setups.
Control Word BitFunctionValue for Mode 0 (Group A/B)
D7Mode Set1
D6Group A Mode Select (MSB)0
D5Group A Mode Select (LSB)0
D4Port A I/O (0=input, 1=output)Programmable
D3Port C Upper I/O (0=input, 1=output)Programmable
D2Group B Mode Select0
D1Port B I/O (0=input, 1=output)Programmable
D0Port C Lower I/O (0=input, 1=output)Programmable
This table illustrates the bit assignments, enabling flexible configuration via a single byte write.

Mode 1: Strobed

Mode 1 of the 8255 Programmable Peripheral Interface operates as a strobed mode, enabling controlled data transfers between the device and external peripherals through signaling. This mode allows Port A and Port B to function independently as either inputs or outputs, with the upper four bits of Port C (PC7–PC4) dedicated to handshaking for Port A and the lower four bits (PC3–PC0) for Port B. It is particularly suited for applications requiring synchronized data exchange, such as interfacing with printers, displays, or other devices that use strobe and acknowledge signals to ensure reliable transmission without data loss or overrun. In input configuration for either Port A or Port B, data from the peripheral is latched into the 8255's input buffer upon receiving a low-going (Strobe) signal on the corresponding Port C pin (PC4 for Port A input). The IBF (Input Buffer Full) flag is then set high (on PC5 for Port A) to indicate that valid is available in the buffer, and an INTR () signal is generated on the appropriate Port C pin (PC6 for Port A) to notify the CPU, provided the interrupt enable bit is set in the control word. "A low on this input loads into the input ," as defined for the signal, ensuring the data is captured on the falling edge. The CPU reads the data from the port, which resets IBF low but does not affect INTR directly; INTR is reset when the peripheral asserts ACK (on PC7 for Port A input, though often PC7 is free in input). In practice, the handshake completes with peripheral monitoring IBF and asserting ACK if configured, but basic operation relies on CPU read resetting IBF. Timing requirements include a minimum of 100 ns and setup/hold times for relative to to prevent errors. For output configuration, the CPU writes data to the output register, which latches the data and immediately enables the three-state output buffers, placing the data on the lines. Simultaneously, OBF (Output Buffer Full) is set low (on PC7 for Port A output) to signal data availability, and INTR is pulsed high (on PC6) if enabled, notifying the CPU that the transfer can proceed to the next byte. The peripheral detects OBF low, reads the data from the , and asserts ACK low (on PC5 for Port A output) to acknowledge receipt. The falling edge of ACK resets OBF high and INTR low, indicating the buffer is empty and ready for the next output cycle. The ACK pulse must meet a minimum width of 100 ns, with defined delays for OBF reset and INTR clearing to synchronize with peripheral response times. The handshake protocol in Mode 1 ensures bidirectional compatibility, where Port A can be input while Port B is output (or vice versa), sharing the line if both groups generate INTR simultaneously. Note that the specific Port C pins used for handshaking differ slightly between input and output configurations: for Port A output, PC7 (OBF), PC6 (INTR), PC5 (ACK); for input, PC6 (INTR), PC5 (IBF), PC4 (), with the unused pin available for general I/O. This flexibility supports efficient peripheral control in systems like early microcomputers, where the 8255 interfaces with devices requiring precise timing, such as parallel printers using for data latching and ACK for readiness indication. Overall, Mode 1 enhances reliability over simpler modes by incorporating status flags and , reducing CPU polling overhead in I/O operations.

Mode 2: Bidirectional Mode

Mode 2, also known as the strobed bidirectional mode, configures Port A of the 8255 as an 8-bit bidirectional I/O port capable of data transfer in both directions under handshaking control. This mode is designed for applications requiring synchronized communication with peripherals that support bidirectional data flow, such as certain printers or memory-mapped devices, where data integrity is ensured through strobe and acknowledge signals. Unlike Mode 0 or Mode 1, Mode 2 is exclusive to Port A, while Port B operates independently in either Mode 0 (basic I/O) or Mode 1 (strobed I/O). Port C provides the necessary handshaking signals using its upper (PC7–PC4), with the lower (PC3–PC0) available for Port B control or general I/O if Port B is in Mode 0. The handshaking protocol in Mode 2 employs five key signals to manage input and output transfers: (strobe), IBF (input buffer full), OBF (output buffer full), ACK (acknowledge), and INTR (). These signals are mapped to Port C pins PC7–PC4 and facilitate a double-handshake mechanism for reliable data exchange. The protocol differs for input and output directions, with the 8255 automatically handling buffer and status flags upon CPU read or write operations to Port A. Interrupt generation on INTR can be enabled or disabled via bit set/reset operations on specific Port C pins (PC6 for Port A enable). Polarity of and ACK can be configured via the control word to match peripheral requirements. For input transfers (peripheral to 8255), the peripheral places on Port A lines and asserts STB low on PC4 to signal validity. The 8255 latches the into its input buffer on the falling edge of STB, sets IBF high on PC5 to indicate acceptance, asserts INTR high on PC6 if enabled to notify the CPU of available , and sets Port A to high-impedance state. The peripheral monitors IBF high, removes the from Port A, and asserts ACK low on PC7 to confirm transfer completion. Upon detecting the falling edge of ACK, the 8255 resets IBF low and INTR low. The CPU can read the latched from Port A at any time after INTR is asserted; the read operation retrieves the data from the input but does not affect the flags, which are reset by ACK. This ensures no data loss during high-speed transfers. For output transfers (8255 to peripheral), the CPU writes data to Port A, which loads the output , enables the output buffers to drive the data onto Port A, sets OBF low on PC7 to signal data ready, and asserts INTR high on PC6 if enabled. The peripheral detects OBF low, reads the data from Port A, and asserts low on PC4 to acknowledge acceptance. Upon detecting the falling edge of , the 8255 resets OBF high, deasserts INTR low, and sets Port A to high-impedance state, preparing for the next transfer. In this mode, PC5 (normally IBF) is not actively used for output handshaking but may be available depending on configuration. Timing parameters, such as pulse width (minimum 100 ns) and delay from to OBF reset (maximum 150 ns), ensure compatibility with various peripheral speeds.
SignalPort C PinFunction in Input TransferFunction in Output Transfer
STBPC4 (input)Peripheral asserts low to present valid data on Port APeripheral asserts low to acknowledge data read from Port A
IBFPC5 (output)8255 asserts high after latching data (signals acceptance to peripheral)Not used for primary handshaking (available for I/O in some setups)
INTRPC6 (output)8255 asserts high to request CPU interrupt (data available)8255 asserts high to request CPU interrupt (output cycle started)
ACKPC7 (input)Peripheral asserts low after seeing IBF high (confirms ready for next)Not used for primary handshaking
OBFPC7 (output)Not used for primary handshaking8255 asserts low to indicate output data ready on Port A
To enter Mode 2, the is programmed with bit D7 = 1 (select I/O mode), D6–D5 = 11 (select Mode 2 for Port A), and D4 don't care (bidirectional fixed). Additional control words set Port B mode (D2=0 or 1, D1 direction) and Port C lower configurations (D0), with separate bit set/reset for interrupt enables. Reading Port C provides status of IBF, INTR, and OBF for software polling if interrupts are disabled. This mode's flexibility makes it suitable for system designs requiring efficient bidirectional peripheral interfacing without dedicated hardware handshaking logic.

Applications

Peripheral Interfacing

The Programmable Peripheral Interface (PPI) facilitates direct communication between a and external peripherals by providing 24 programmable I/O lines organized into three 8-bit ports (A, B, and C), allowing flexible configuration for , or bidirectional operations. This design enables efficient parallel data transfer without burdening the CPU's address or data buses, making it ideal for integrating devices such as keyboards, displays, and analog-to-digital converters (ADCs) in early systems. The chip's allows dynamic mode selection and port direction, supporting seamless interfacing in resource-constrained environments. In basic peripheral interfacing, Mode 0 of the 8255 is employed for straightforward input/output tasks, where ports can be independently set as inputs or outputs with latched buffering to maintain signal stability. For example, Port B is often used as an output port to interface with LED or seven-segment displays, driving the segments directly while Port C handles control signals like enabling or scanning digits. Similarly, Port A can serve as an input for scanning a keyboard matrix, where key closures are detected by reading port status, preventing issues like key bounce through software debouncing routines. This mode's simplicity suits static peripherals requiring no handshaking, as seen in early calculator or terminal applications. For peripherals demanding synchronized data exchange, Mode 1 provides strobed with dedicated handshake lines from Port C (e.g., STB for strobe, IBF for input buffer full, and ACK for acknowledge), ensuring reliable transfer under varying peripheral speeds. A common application is keyboard input, where the keyboard controller sends a strobe signal to the 8255 upon key press, triggering an (INTR) to the CPU for data reading from Port A; this prevents data loss in high-speed environments. In ADC interfacing, Mode 1 captures converted digital values by waiting for the ADC's end-of-conversion signal on a Port C line, then latching the 8-bit output into Port A for CPU retrieval, commonly used in systems for sensors or . Printers also leverage this mode for controlled output, where the 8255 sends character data to the printer while monitoring busy and acknowledge signals. Mode 2 extends interfacing capabilities to bidirectional peripherals via Port A, using five Port C lines for advanced handshaking (e.g., OBFA for output buffer full and STBA for strobe A), enabling two-way data flow in a single port. This is particularly useful for devices like impact printers or shared bus peripherals, where the 8255 alternates between sending commands and receiving status or data, maintaining protocol compliance through timed signals. In display systems requiring feedback, such as those with status indicators, Mode 2 allows the to output display data while reading back verification from the peripheral. Overall, these modes make the 8255 a cornerstone for peripheral expansion in 8-bit systems, reducing wiring complexity and enhancing reliability through buffered I/O.

System Integration Examples

The Intel 8255 Programmable Peripheral Interface (PPI) was integral to the subsystem of the original IBM PC (model 5150), where it managed parallel I/O operations for several key peripherals. Configured in Mode 0 for basic , the chip's ports were initialized by the with a control word of 0b10011001, assigning Port A as input for keyboard scan codes or settings (e.g., floppy drive and display configuration), Port B as output for controlling the speaker, cassette motor, and RAM/I/O clocks, Port C upper bits for cassette data input, and Port C lower bits for receiving RAM size from . This setup enabled reliable interfacing with the keyboard (via Port A and PB7 for acknowledgment), cassette drive, speaker, and system configuration switches, demonstrating the 8255's role in bridging the 8088 CPU to legacy peripherals in early personal computing. In Intel's MCS-80 family systems, such as those based on the 8080 CPU, the 8255 facilitated diverse parallel I/O tasks through isolated or memory-mapped addressing schemes, supporting up to 24 configurable lines via the system's bi-directional data bus and control signals like RD, WR, and CS. For instance, in an automatic scale application, it interfaced input from weighing units and keyboards (using input ports) with outputs to displays and printers, leveraging Mode 0 for simple I/O or Mode 1 for strobed handshaking in printer hammer control. Other configurations included interfaces (Port A in Mode 1 for shift control, Port B in Mode 0 for status display) and CRT controllers (Port A for character generation, Port B for cursor positioning), highlighting its versatility in industrial and peripherals within the INTELLEC systems. Home computers like the SVI-328 (an early MSX-compatible system) employed the 8255 to handle user input and storage devices, with Port A (address 98H, input, Mode 0) reading cassette data, joystick triggers, and end-of-conversion signals; Port B (99H, input, Mode 0) scanning keyboard columns; and Port C (96H, output, Mode 0) controlling keyboard clicks, cassette motor/audio, and line selection. This integration supported seamless operation of the keyboard, joysticks, paddles, and system, controlled via a setup word at 97H (0b10010010), underscoring the chip's adoption in Z80-based for cost-effective peripheral expansion. In scientific instrumentation, the 8255 was integrated into microprocessor-based systems for automated , as seen in a respiration monitoring setup for sensory studies. Here, it served as the primary interface between an CPU and measurement peripherals, using its three 8-bit ports to handle 24 for input from sensors tracking patterns during chemical exposures. Operating in basic I/O mode, the chip enabled rapid data transfer and control, reducing manual processing time from hours to seconds per experiment and supporting real-time integrity checks, which was critical for toxicological .

Variants and Alternatives

Intel Variants

The Intel 8255 Programmable Peripheral Interface (PPI) was initially released in NMOS technology as the original 8255, providing 24 programmable I/O lines across three 8-bit ports (A, B, and C) configurable in basic input/output, strobed, or bidirectional modes. This variant was designed for early 8-bit microprocessors like the 8080 and , emphasizing compatibility with TTL logic levels but limited by higher power consumption and slower access times compared to later iterations. Subsequent improvements led to the 8255A, an enhanced NMOS version introduced as a for the original 8255, maintaining pin compatibility while improving electrical characteristics such as reduced power dissipation to 1 W maximum. The 8255A featured refined timing specifications, with data access times of 320 ns for reads and 320 ns for writes in Mode 0, making it suitable for higher-throughput peripheral connections like printers and keyboards in mid-1970s computing environments. It supported system clocks up to approximately 3 MHz. A further refinement, the 8255A-5, offered optimizations over the 8255A, primarily in signal timing requirements for faster system integration, with read access times reduced to 250 ns and write access times to 300 ns, while retaining the same 1 power profile; this variant supported system clocks up to 5 MHz and was targeted at applications demanding quicker response without shifting to technology. Similarly, the 8255B variant enhanced drive capability on output ports to support more capacitive loads, differing mainly in electrical specs like higher sink/source currents (up to 2.5 mA sink and 0.5 mA source on ports) but sharing the core functionality and speed profile of the 8255A-5. In response to demands for lower power and higher speeds, Intel developed the 82C55 and 82C55A as CMOS implementations, fully pin-compatible with the NMOS 8255A and 8255A-5, but achieving up to 8 MHz clock rates with "zero wait state" operation in systems like the 8086/88 and 80186/188 and typical power consumption of approximately 50 mW (10 mA at 5 V), a significant reduction from the 1 of NMOS variants. These CMOS versions preserved all operational modes and I/O configurations while improving efficiency for battery-powered or dense board designs, with extended temperature ranges (-40°C to 85°C) and supply voltages from 4 V to 7 V, marking a shift toward more versatile integration in embedded systems. The 82C55A remains available from manufacturers like Renesas for legacy and embedded applications as of 2025.

Comparable Devices

The Intel 8255 Programmable Peripheral Interface (PPI) was one of several similar devices developed by competing semiconductor manufacturers in the 1970s to provide flexible parallel I/O capabilities for microprocessors. These comparable chips typically featured multiple programmable ports, support for input/output modes, and compatibility with 8-bit systems, but varied in port count, operational modes, and integration with specific CPU families. Key examples include the Motorola MC6821 Peripheral Interface Adapter (PIA), the Signetics 2655 PPI, and the Zilog Z80 PIO, each designed to interface peripherals like keyboards, displays, and sensors to microprocessors such as the 6800, 2650, and Z80 series, respectively. The Motorola MC6821 PIA, introduced for the M6800 family, provides two 8-bit bidirectional ports (A and B) along with four dedicated control lines, enabling programmable I/O per data line and handshake logic for strobed transfers. It operates in a single mode with flexible input/output configuration and interrupt capabilities, packaged in a 40-pin DIP similar to the 8255, but lacks a third port and advanced bidirectional bus mode. This made it suitable for simpler peripheral expansions in Motorola-based systems, such as early industrial controllers. In contrast, the Signetics 2655 PPI, tailored for the 2650 , mirrors the 8255 more closely with three 8-bit ports (A, B, C) offering 24 I/O lines and five operational modes: static I/O, strobed I/O, bidirectional I/O, serial I/O, and serial/ I/O. It includes direct bit set/reset functions and supports both polled and interrupt-driven operations on a single +5V supply, with 300 ns access times, providing broader versatility including integration on Port B for event counting in embedded applications. The PIO (Z84C20), optimized for the Z80 CPU, features two 8-bit bidirectional ports with four modes—output, input, bidirectional (Port A only), and bit control—along with integrated lines and daisy-chain priority for up to four devices. Housed in a 40-pin DIP, it emphasizes efficient peripheral control in Z80 systems like early personal computers, but offers fewer ports than the 8255 while adding specialized for tasks such as driving transistors.
FeatureIntel 8255 PPIMotorola MC6821 PIASignetics 2655 PPIZilog Z80 PIO
Ports3 × 8-bit (24 I/O lines)2 × 8-bit (16 I/O lines)3 × 8-bit (24 I/O lines)2 × 8-bit (16 I/O lines)
Modes3 (basic, strobed, bidirectional)1 ()5 (static, strobed, bidirectional, serial, )4 (output, input, bidirectional, bit control)
Pin Package40-pin DIP40-pin DIP40-pin DIP40-pin DIP
Key IntegrationGeneral compatibleM6800 family 2650 family with daisy-chain
Supply/Access Time+5V, ~250 ns (8255A)+5V, ~1 µs+5V, 300 ns+5V, ~500 ns

References

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