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MOS Technology Agnus
MOS Technology Agnus
MOS Technology Agnus
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MOS 8367R0 – Agnus

The MOS Technology "Agnus", usually called Agnus, is an integrated circuit in the custom chipset of the Amiga computer. The Agnus, Denise and Paula chips collectively formed the OCS and ECS chipsets.

The Agnus is the Address Generator Chip. Its main function, in chip area, is the RAM Address Generator and Register Address Encoder which handles all DMA addresses. The 8361 Agnus is made up of approximately 21000 transistors and contains DMA Channel Controllers. The Blitter and Copper are also contained here. Originally Agnus was fabricated in 5 μm manufacturing process like all OCS chipset.

Agnus features:

  • Memory controller ("Chip" memory that can be accessed by the processor and the chipset)
  • The Blitter, a bitmap manipulator. The Blitter is capable of copying blocks of display data, or any arbitrary data in the chip memory, at high speed with various raster operations as well as drawing pixel perfect lines and filling outlined polygons, while freeing the CPU for concurrent tasks.
  • "Copper", a display synchronized co-processor
  • 25 Direct Memory Access (DMA) channels, allowing graphics, sound and I/O to be used with minimal CPU intervention
  • DRAM refresh controller
  • Generates the system clock from the 28 MHz oscillator
  • Video timing

Agnus was replaced by Alice in the Amiga 4000 and Amiga 1200 when the AGA chipset was introduced in 1992.

Chips by capability

[edit]
Agnus chip (MOS Technology 8370 R3)

* Somewhere 8372A Agnus mentioned as simply "8372".

Chips by package

[edit]
  • 48-lead DIP Agnus (aka thin Agnus): 8361; 8367
  • 84-contact PLCC Fat Agnus (named Fat Lady on most Amiga 2000 motherboards) 8370; 8371; 8372; 8372A; 8372AB; 8372B; 8375

Notes
Fat Agnus 1MB and Fat Agnus 2MB also known as Super Agnus; Super Fat Agnus; Fatter Agnus; Big Agnus; Big Fat Agnus.

DMA Channels

[edit]
Priority Name Count Cycles/Rasterline Chip Notes
MPU 1 varying CPU
A Blitter 4 varying Agnus (internal) yields 1/4 cycles to CPU when BLTPRI not active
B Bitplane 6 80 Denise impairs sprite channels on severe overscan
C Copper 1 varying Agnus (internal)
D Audio 4 4 Paula
E Sprites 8 16 Denise
F Disk 1 3 Paula
G Memory Refresh 1 4 -
Reference: Amiga 500 plus Service Manual

Pinout

[edit]

PLCC versions

[edit]

When replacing or upgrading chips, pinouts need to be taken care of. Types are just mentioned for reference; four-digit types and pinouts/usage are not consistent.[1]

Pin OCS/ECS ECS AGA (Alice) Description
A500/2000 A3000 A500+/600 A4000/1200
8370/1 8372 8375 8374
1 RD13 DRD13 DRD13 DRD13 Data Bus 16 bit, bit 13
2 RD12 DRD12 DRD12 DRD12 .
.
.
3 RD11 DRD11 DRD11 DRD11
4 RD10 DRD10 DRD10 DRD10
5 RD9 DRD9 DRD9 DRD9
6 RD8 DRD8 DRD8 DRD8
7 RD7 DRD7 DRD7 DRD7
8 RD6 DRD6 DRD6 DRD6
9 RD5 DRD5 DRD5 DRD5
10 RD4 DRD4 DRD4 DRD4
11 RD3 DRD3 DRD3 DRD3
12 RD2 DRD2 DRD2 DRD2
13 RD1 DRD1 DRD1 DRD1
14 RD0 DRD0 DRD0 DRD0 Data Bus 16 bit, bit 0
15 Vcc Vcc Vcc Vcc1 +5V ±5%
16 RST* _RESET _RESET /RESET Global RESETn, low active
17 INT3 _INTR _INTR /INTR
18 DMAL DMAL DMAL DMAL
19 BLS* _BLISS _BLISS /BLS
20 DBR* _BLIT _BLIT /DBR
21 RRW _WE _WE /WE
22 PRW R/W R/W R/W
23 RGEN* _REGEN _REGEN _REGEN
24 AS* _AS _AS NC2
25 RAMEN* _RAMEN _RAMEN /RAMEN
26 RGA8 RGA8 RGA8 RGA8
27 RGA7 RGA7 RGA7 RGA7
28 RGA6 RGA6 RGA6 RGA6
29 RGA5 RGA5 RGA5 RGA5
30 RGA4 RGA4 RGA4 RGA4
31 RGA3 RGA3 RGA3 RGA3
32 RGA2 RGA2 RGA2 RGA2
33 RGA1 RGA1 RGA1 RGA1
34 28 MHz 28 MHz 28 MHz SCLK
35 XCLK A20 A20 A20
36 XCLKEN* _XCLKEN _CDAC 14 MHz
37 CDAC* _CDAC 7 MHz /CDAC
38 7 MHz 7 MHz CCKQ 7 MHz
39 CCKQ CCKQ CCK CCKQ
40 CCK CCK 14M CCK
41 TEST TEST GND /NTSC
42 Vss Vss1 DRA0 GND2
43 MA0 DRA0 DRA1 DRA0 Memory address bus 9 bit, bit 0 (except 8375 which is bit 1)
44 MA1 DRA1 DRA2 DRA1 .
.
.
45 MA2 DRA2 DRA3 DRA2
46 MA3 DRA3 DRA4 DRA3
47 MA4 DRA4 DRA5 DRA4
48 MA5 DRA5 DRA6 DRA5
49 MA6 DRA6 DRA7 DRA6
50 MA7 DRA7 DRA8 DRA7
51 MA8 DRA8 _LDS DRA8 Memory address bus 9 bit, bit 8 (except 8375 which is bit _LDS)
52 LDS* _LDS _UDS Vcc2
53 UDS* _UDS _CASL NC1
54 CASL* _CASL _CASU /CAS
55 CASU* _CASU DRA9 Vbb
56 RAS1* DRA9 _RAS1 DRA9
57 RAS0* _RAS _RAS0 /RAS
58 Vss Vss2 GND GND3
59 A19 A19 A19 A19
60 A1 A1 A1 A1
61 A2 A2 A2 A2
62 A3 A3 A3 A3
63 A4 A4 A4 A4
64 A5 A5 A5 A5
65 A6 A6 A6 A6
66 A7 A7 A7 A7
67 A8 A8 A8 A8
68 A9 A9 A9 A9
69 A10 A10 A10 A10
70 A11 A11 A11 A11
71 A12 A12 A12 A12
72 A13 A13 A13 A13
73 A14 A14 A14 A14
74 A15 A15 A15 A15
75 A16 A16 A16 A16
76 A17 A17 A17 A17
77 A18 A18 A18 A18
78 LP* _LPEN _LPEN /LPEN
79 VSY* _VSYNC _VSYNC /VSYNC
80 CSY* _CSYNC _CSYNC /CSYNC
81 HSY* _HSYNC _HSYNC /HSYNC
82 Vss Vss3 GND GND1 Ground, common on whole board
83 RD15 DRD15 DRD15 DRD15 Data Bus 16 bit, bit 15
84 RD14 DRD14 DRD14 DRD14 Data Bus 16 bit, bit 14

References: A500 Service Training, A3000 Service Manual, A500+ Service Manual, A1200 schematics

See also

[edit]

References

[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

MOS Technology Agnus

View on Grokipedia
from Grokipedia
The MOS Technology Agnus is a custom large-scale integration (LSI) chip developed by , a subsidiary of , as a core component of the Original Chip Set (OCS) for the line of personal computers introduced in 1985. It functions primarily as the address generator, handling (DMA) operations, RAM address generation and encoding, system clock generation, and coordination of graphics, audio, and tasks across the chipset. In the Amiga architecture, Agnus integrates with the Denise chip for video rendering and the Paula chip for audio processing, interrupt control, and I/O operations, enabling the system's advanced multimedia capabilities such as hardware-accelerated blitting, sprite handling, and bitplane DMA. Over the Amiga's lifespan, it evolved through several variants to support increased memory and compatibility with later models, including the Enhanced Chip Set (ECS). These advancements solidified Agnus's role in defining the Amiga's pioneering hardware-accelerated graphics and sound, influencing retro computing and emulation communities to this day.

Overview

Role in Amiga Chipset

The MOS Technology Agnus serves as the Address Generator Chip in the 's Original Chip Set (OCS) and Enhanced Chip Set (ECS), forming a core part of the custom chipset alongside the Denise graphics processor and the Paula audio and controller. It acts as the central hub for memory addressing and timing coordination, enabling the Amiga's signature multimedia performance by synchronizing data transfers across hardware components. Agnus also integrates the for hardware-accelerated operations and the coprocessor for display list processing. Agnus's primary responsibilities include generating RAM addresses for video display operations, managing (DMA) for graphics rendering, audio playback, and peripheral interactions, as well as handling DRAM refresh cycles to maintain memory integrity. It also produces essential video beam timing signals that dictate the horizontal and vertical synchronization for screen output, ensuring precise control over display updates. Operating at a 28.63636 MHz , Agnus supports up to 25 DMA channels with prioritized time slots, allowing efficient allocation of bus cycles for tasks like bitplane fetching and sprite handling. Within systems, Agnus orchestrates data flow between the CPU, shared chip RAM, and custom hardware, facilitating seamless multitasking by granting DMA requests precedence over CPU access during critical periods such as video blanking intervals. This integration empowers the to deliver concurrent graphics, sound, and system operations without software intervention, a hallmark of the 's architecture. Introduced in July 1985 with the , Agnus was foundational to the platform's innovative multimedia features, including smooth hardware scrolling through coordinated bitplane DMA and independent sprite movement for dynamic visuals. In the ECS variant, debuting in 1990 with models like the , revised Agnus chips preserved these roles while accommodating expanded memory addressing up to 2 MB.

Key Technical Specifications

The MOS Technology Agnus chip was fabricated using an N-channel HMOS process. Agnus generates the system clock at 7.15909 MHz for configurations or 7.09379 MHz for PAL configurations from a 28.63636 MHz () or 28.37516 MHz (PAL) input oscillator, while supporting 15 kHz video beam synchronization through its beam counters and timing mechanisms. The chip features 23 address lines (A1-A23), allowing support for up to 8 MB of total RAM across the system, with 16-bit data bus access dedicated to chip RAM operations; individual DMA channels utilize 18-bit RAM address pointers for precise . As the core component of the Original Chip Set (OCS), Agnus provides baseline functionality for DMA, , and operations, with ECS revisions introducing enhancements such as expanded addressing for up to 2 MB chip RAM and additional video modes.

Development and Revisions

Origins and Design Team

The MOS Technology Agnus chip originated from the Lorraine project, a prototype multimedia computer initiated in 1982 by the Hi-Toro company, a startup founded by former Atari engineers including Dave Morse, Jay Miner, and Joe Decuir. Hi-Toro, later renamed Amiga Corporation in 1983 to appeal to investors, aimed to develop an affordable 16-bit computer expandable for gaming and professional use, with Miner—known for designing the Atari 2600's Television Interface Adaptor (TIA) chip—leading the hardware team that included designers Dale Luck and others. The project faced financial difficulties, leading to its acquisition by Commodore International on August 13, 1984, for $24 million, after which the custom chips, including Agnus, were finalized under Commodore's oversight. Agnus was designed primarily as a versatile direct memory access (DMA) engine to enable efficient processing in a cost-effective , drawing inspiration from arcade and hardware to integrate advanced capabilities directly into silicon. Key goals included supporting fast bit-block transfer () operations for acceleration and a lightweight () for managing display lists and video register changes without burdening the CPU, allowing the to deliver real-time video effects and animations rivaling dedicated arcade machines. This approach prioritized access among custom chips, the CPU, and peripherals to create a unified for affordable , with the design process spanning from 1982 to 1984 and involving three primary chip designers, including for Agnus. Initial fabrication occurred at , Commodore's semiconductor subsidiary, using a 5-micrometer NMOS process. The first silicon for Agnus was taped out in late 1984, following the Commodore acquisition, with prototypes demonstrated at the June 1984 Consumer Electronics Show (CES) using breadboard implementations to showcase basic DMA and blitter functionality, such as a demo. Significant design challenges included balancing DMA channel priorities to prevent CPU starvation, as the 68000 processor required exclusive access during even bus cycles for optimal performance, while custom chip DMA operations filled odd cycles to maximize bandwidth without halting instruction execution. Additionally, ensuring compatibility with the 68000's addressing scheme, which favored even-aligned word accesses but interfaced with interleaved chip RAM, demanded careful logic in Agnus to handle odd-address penalties and maintain system stability during high-contention scenarios.

Evolution Across Amiga Models

The MOS Technology Agnus debuted in 1985 as a core component of the Original Chip Set (OCS) in the , handling DMA operations, functions, and memory addressing for the system's initial 512 KB chip RAM configuration. This initial implementation, produced by , established Agnus as the central coordinator for shared RAM access and video timing in early hardware. By 1987, with the launch of the and , Agnus underwent revisions to the 8370 () and 8371 (PAL) variants, known as "Fat Agnus" due to their larger PLCC packaging that supported improved manufacturing efficiency and compatibility with the new models' base 512 KB chip RAM setups. These changes responded to hardware upgrades requiring more flexible integration, while mask-programmed updates between 1987 and 1989—such as the 8372 series—focused on cost reductions and corrections for PAL/ signal handling to ensure stable video output across regions. The evolution was driven by growing demands for expanded chip RAM, rising from 512 KB to 1 MB in later OCS configurations, enabling more sophisticated multitasking and graphics-intensive applications. In 1990, the introduction of the Enhanced Chip Set (ECS) with the prompted further adaptations, including the 8372A and 8372B variants, which extended chip RAM support to 2 MB and incorporated bug fixes for addressing issues in prior iterations. These ECS-compatible revisions, still manufactured under (later Commodore Semiconductor Group), enhanced video mode flexibility, such as additional display resolutions and interlaced modes, to meet evolving software requirements. By the early , the 8375 series refined these advancements for models like the Amiga 500+ and , using dedicated PAL and versions to eliminate jumper-based switching and reduce production costs through process optimizations. Agnus production ceased in 1992 with the shift to the Advanced Graphics Architecture (AGA) chipset in the and , where it was superseded by the Alice chip, ending further MOS-branded iterations and transitioning Amiga hardware to enhanced color and graphics capabilities.

Chip Variants

Variants by Memory Support

The MOS Technology Agnus chip was initially released in variants limited to 512 KB of chip RAM support, including the 8361 () and 8367 (PAL) models. These "thin" Agnus versions, designed for early Amiga systems such as the and , provided foundational DMA capabilities for graphics, audio, and I/O operations, along with support for up to seven bitplanes in display modes. The 8367 was a PAL-specific variant tailored for European markets, ensuring compatibility with regional video standards without altering core memory addressing. Subsequent iterations expanded memory capacity to 1 MB with the introduction of "Fat Agnus" variants, namely the 8370 and 8371. These chips, intended for upgrades in and systems, enabled the addressing of an additional 512 KB of chip RAM beyond the original limit, facilitating larger frame buffers and more complex graphics operations while preserving basic DMA and seven-bitplane support. The 8371 addressed specific bugs in the 8370 through mask ROM revisions, improving reliability in and display timing without introducing new features. Enhanced variants under the "Super Agnus" designation, including the 8372, 8372A, 8372AB, and 8372B, built upon the Fat Agnus foundation, with ECS compatibility for larger operations. Produced by UHA as later revisions, the A and B suffixes reflected yield improvements in fabrication processes. These chips supported up to 2 MB chip RAM addressing (e.g., 8372B) but extended DMA flexibility for ECS-equipped models. For ECS-based systems, the 8375 variant (and PAL equivalents like 8372B) supported up to 2 MB of chip RAM, targeting the and Amiga 3000T. The 8375, specifically optimized for NTSC standards, featured refined addressing logic to handle the expanded memory range seamlessly, enabling higher-resolution modes such as Super Hi-Res (1280 pixels horizontally) while retaining seven-bitplane graphics and basic DMA channels. All Agnus variants universally supported core OCS features like seven-bitplane displays and standard DMA operations, with later models incorporating ECS enhancements for advanced color modes and programmable scan rates.

Variants by Package Configuration

The MOS Technology Agnus chip was produced in two primary package configurations: the 48-pin (DIP) for early variants and the 84-pin Plastic Leaded Chip Carrier (PLCC) for later "Fat" and "Super" variants. These packaging choices directly influenced their integration into motherboards, balancing ease of assembly, upgradability, and space efficiency. The 48-pin DIP configuration, measuring approximately 62 mm in length by 15 mm in width with a 2.54 mm pin pitch, was used exclusively for the initial "thin" Agnus variants, including the 8361 () and 8367 (PAL). This through-hole package facilitated socketed installations in early models such as the and certain revisions, allowing for straightforward chip replacement and upgrades without specialized soldering equipment. The limited pin count supported basic 512 KB chip RAM addressing, making it suitable for the Original Chip Set (OCS) in compact, hobbyist-friendly designs. In contrast, the 84-pin PLCC configuration, with a square body size of about 36.5 mm per side and a finer 1.27 mm pin pitch, became the standard for enhanced Agnus variants starting with the 8370 series. This surface-mount-compatible package accommodated additional pins for expanded addressing and Enhanced Chip Set (ECS) signals, enabling support for up to 2 MB of chip RAM in models like the Amiga 500, 2000, 3000, 500+, 600, and CDTV. The PLCC design was typically socketed in consumer models like the Amiga 500 for serviceability but also supported direct soldering in higher-density boards such as the Amiga 3000 tower. These package differences had significant implications for board integration and . The DIP's taller profile (around 5-6 ) and wider made it ideal for prototyping and user upgrades via standard IC sockets, though it occupied more vertical space in chassis-constrained systems. Conversely, the PLCC's low-profile (under 5 height) and compact form enabled denser layouts in later expansions, but required precision surface-mount soldering techniques, increasing manufacturing complexity while improving overall system reliability through better thermal dissipation. Both packages used leaded construction typical of 1980s fabrication, with no documented 100-pin variants in production use.

Internal Components

DMA Controller and Channels

The DMA controller in the MOS Technology Agnus manages 25 (DMA) channels, enabling concurrent hardware tasks such as graphics, audio, and I/O operations with limited CPU overhead. These channels are multiplexed across 7 priority slots, designated A (highest priority) through G (lowest), where channels within the same slot share access via to promote equitable bus usage. The CPU yields the data bus during assigned DMA slots, ensuring prioritized hardware access to Chip RAM while the processor idles or executes from Fast RAM when possible. The channels are organized by function and priority as follows, with specific cycle demands tailored to their roles:
Channel TypeNumber of ChannelsPriority SlotCycle Allocation per Raster Line
Blitter4AVariable (depending on graphics operations like block moves or line fills)
Bitplane6B80 cycles total (for display data fetch, scaling with active planes)
Copper1CVariable (based on instruction list processing for display control)
Audio4D4 cycles total (1 cycle per active channel for sample playback)
Sprites8E16 cycles total (2 cycles per active sprite for position and data)
Disk1F3 cycles (fixed for floppy controller data transfer)
Memory Refresh1G4 cycles (fixed for DRAM row refresh)
These allocations reflect the hardware's design to balance real-time demands, with higher-priority slots (A–C) dominating during intensive graphics workloads. Each raster line provides 227 color clock cycles in total (NTSC timing), of which up to 80 are allocated for bitplane DMA, with additional fixed slots for other channels, leaving the balance for CPU access after accounting for video beam timing overhead. Slot allocation is determined by summing the cycle demands of all enabled channels; for example, a full-screen mode with all 6 bitplanes active consumes 80 cycles for bitplanes alone, leaving no room for lower-priority channels without adjustments. If bitplane demand exceeds its 80-cycle window, it results in display glitches like bitplane corruption; excessive total DMA can defer lower-priority channels like sprites or audio, causing dropout or stuttering, as unserved requests are deferred or dropped. The formula for required DMA cycles is simply the sum of individual channel demands: Total DMA cycles = Σ (cycles per channel × active status), where overflow occurs if total demand exceeds available line time (~227 cycles). Programmers mitigate this by disabling non-essential channels or using overscan to reclaim slots.

Blitter and Copper Processors

The is a dedicated hardware bit-block transfer engine integrated into the MOS Technology Agnus chip, enabling high-speed operations such as copying blocks of , area filling, line drawing, and masking without CPU involvement. It utilizes four DMA channels—three sources labeled A, B, and C for input (e.g., bitplanes or textures) and one destination channel D for output—allowing simultaneous of multiple streams in rectangular regions up to 1024 pixels wide by 1024 rows high. The engine's applies minterm logic to combine source bits via a programmable , supporting 256 possible boolean operations including AND, OR, and XOR for pixel-level blending and masking. In line-drawing mode, activated via the BLTCON1 register, the generates straight lines up to 1024 pixels long using an octant-based vector algorithm, with support for patterned textures, filling, and optional Z-minterm comparison (ZMC) to perform depth-like tests against a reference value, facilitating simple hidden surface removal in 3D graphics. Operating at the system's approximate 7 MHz , the Blitter achieves effective data throughput of around 1.4 MB/s for graphics tasks when sharing the bus with display DMA, though simple memory copies can reach up to 3.5 MB/s under ideal conditions with the CPU halted. The is a specialized within Agnus that manages real-time display control through a simple instruction set executed via DMA from chip RAM, allowing precise synchronization with the video beam for dynamic graphics updates. It supports three instruction types: MOVE, which transfers 16-bit data from to hardware registers (e.g., for palette or BPLPTR setup); WAIT, which pauses execution until the video beam reaches a specified horizontal/vertical position, masked by enable bits for flexibility; and SKIP, a conditional variant of WAIT that branches over the next instruction if the beam condition is met. Instructions are fetched in pairs into an internal buffer limited to chip RAM access, with the processor running in two-cycle steps and stealing bus cycles only on odd-numbered slots to minimize interference. This design enables the Copper to perform mid-frame modifications, such as changing color palette entries for fading effects, repositioning sprites for , or adjusting playfield parameters for genlocking to external video signals, all without interrupting the main processor. Copper lists are structured as sequential pairs of 16-bit words terminated by a zero command, supporting looped or one-shot execution for efficient display list management. The and interact through the shared DMA system, with the in the highest-priority slot (A) for graphics acceleration and the in slot C, allowing the to the if needed, though the 's odd-slot timing reduces conflicts. Bus conflicts cause the to halt temporarily for the , maintaining display integrity but constraining combined graphics throughput to approximately 1.4 MB/s under typical loads with active bitplane DMA. Brief references to underlying DMA channel allocation are covered in the DMA Controller and Channels section. Both processors lack floating-point capabilities and operate exclusively on fixed 16-bit words aligned to the chip RAM's data bus, limiting precision for advanced computations. Early Agnus revisions, such as the 8370, exhibited bugs including delayed busy flag assertion (requiring double-checking in software) and potential overflow in large line draws, which were addressed in later variants like the 8372.

Interfaces and Pinouts

DIP Package Details

The 48-pin (DIP) configuration of the MOS Technology Agnus chip, used in early models such as the and initial revisions of the , features a standard rectangular plastic package with two rows of 24 pins each, designed for through-hole mounting on a . This package type supports up to 512 KB of chip RAM addressing due to its limited pin count, which constrains the number of dedicated lines for higher-order address bits compared to later surface-mount variants. Pin 1 is typically marked with a dot or notch for orientation during installation. The pin assignments for the 48-pin DIP Agnus (variants 8361 for and 8362 for PAL) are optimized for memory interfacing, DMA operations, video timing, and control signals, with bidirectional data lines distributed across two sides of the package. Power and ground connections are provided at multiple points for stability, including VCC (+5 V) at pin 10 and VSS (ground) at pins 27 and 41. Key signals include lower data bus (D0-D8) on one side, upper data bus (D9-D15) on the other, DMA request lines, outputs, register address lines, DRAM row address outputs, clock inputs, and video outputs to drive the display controller. The clock input accepts a 28 MHz signal to generate internal timing for DMA cycles and video generation at rates compatible with 5 V TTL logic levels. In early Amiga systems, the 48-pin DIP Agnus was typically installed in a socket for field-replaceable upgrades, facilitating revisions from 256 KB to 512 KB chip RAM without . Electrical specifications include operation at 5 V DC with TTL-compatible I/O thresholds (high >2 V, low <0.8 V) and a maximum current draw of approximately 500 mA total for the chip under full load, though individual pins are rated for 50 mA to prevent damage during hot-swapping or testing. This package lacks pins for ECS (Enhanced Chip Set) extensions, restricting it to original OCS functionality in models produced before 1987.

PLCC Package Details

The PLCC (Plastic Leaded ) package variants of the MOS Technology Agnus chip represent an evolution toward , enabling compact integration in motherboards starting with the A2000 series. These 84-pin configurations, used in the 8370 (, 512 KB support), 8371 (PAL, 512 KB support), and 8372 (/PAL, up to 2 MB support) models, include pins for the register data bus (e.g., RD15-RD2 on pins 1-14), address bus (A1-A19 on pins 59-77), 16-bit data bus, and DRAM timing controls including /RAS and /CAS lines for chip RAM banking. This arrangement facilitates efficient DMA access to 512 KB or 1 MB of chip memory in early Fat Agnus implementations, with power supply pins (VCC and GND) positioned at the corners (e.g., pins 15, 42, 58, 82) for optimal thermal and electrical distribution in high-density boards. Video beam counter outputs, essential for display , occupy pins such as 79-81, providing horizontal (H) and vertical (V) position signals such as /HSYNC (pin 81), /VSYNC (pin 79), and /CSYNC (pin 80) to interface with Denise for raster timing in OCS/ECS modes. ECS ( Chip Set) signals are supported on dedicated pins, enabling extended video resolutions and color palette features when paired with compatible motherboards. These pins support with OCS while adding hooks for improved refresh rates and memory banking in models like the A2000 Rev 6 and A3000. The 8375 variant is an 84-pin PLCC package supporting up to 2 MB of chip RAM in ECS systems such as the 500+, with some revisions featuring minor pin function adjustments for compatibility with specific motherboards like the A3000. This package includes provisions for enhanced clock handling and I/O interfaces suited to later models. Across PLCC variants, critical control signals include direction controls, reset, and lines for prioritizing DMA events from the 68000 CPU. These features ensure seamless integration with the Amiga's custom . In practice, PLCC Agnus chips employ J-lead contacts for reliable surface-mount in A2000 and subsequent models like the A500+, operating reliably up to a maximum of 85°C under typical 5V/1A power conditions. The additional pins in ECS-compatible variants enable support for advanced video modes, such as 640×400 interlaced resolutions, without requiring hardware modifications in upgraded systems.

References

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  32. http://amigadev.elowar.com/read/ADCD_2.1/Includes_and_Autodocs_3._guide/node0339.html
  33. https://eab.abime.net/showthread.php?t=103651
  34. https://www.amigawiki.org/doku.php?id=de:parts:agnus_pinout
  35. https://www.amigawiki.org/dnl/schematics/A2000_R6.pdf
  36. https://www.amigawiki.org/lib/exe/fetch.php?media=de:parts:agnus-history.pdf
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