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WDC 65C02
The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502. It uses less power than the original 6502, fixes several problems, and adds new instructions and addressing modes. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in portable computer roles and industrial microcontroller systems. The 65C02 has also been used in some home computers, as well as in embedded applications, including implanted medical devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02 was officially released sometime shortly after. WDC licensed the design to Synertek, NCR, GTE Microcircuits, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
The 65C02 is a low cost, general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The register set is small, with a single 8-bit accumulator (A), two 8-bit index registers (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" ($0000 to $00FF), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The stack lies in the next 256 bytes, page one ($0100 to $01FF), and cannot be moved or extended. The stack grows downward with the stack pointer (S or SP) starting at $01FF and decrementing with each byte that is pushed. The 65C02 has a variable-length instruction set, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and may be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip (SoC) designs.
A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
The W65C02S6T is the production version as of 2025[update], and is available in PDIP-40, PLCC-44 and QFP-44 packages. The maximum officially supported Ø2 (primary) clock speed is 14 MHz when operated at 5 volts, indicated by a –14 part number suffix (hobbyists have developed 65C02 homebrew systems that run significantly faster than the official rating). The "S" designation indicates that the part has a fully static core, a feature that supports stopping the Ø2 clock in either phase with no loss of state. Typical microprocessors not implemented in CMOS have dynamic cores and will lose state (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
The "6T" designation indicates the process geometry (0.6µ) and that Taiwan Semiconductor Manufacturing Company (TSMC) is the foundry that produces WDC's wafers.
Hub AI
WDC 65C02 AI simulator
(@WDC 65C02_simulator)
WDC 65C02
The Western Design Center (WDC) 65C02 microprocessor is an enhanced CMOS version of the popular nMOS-based 8-bit MOS Technology 6502. It uses less power than the original 6502, fixes several problems, and adds new instructions and addressing modes. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in portable computer roles and industrial microcontroller systems. The 65C02 has also been used in some home computers, as well as in embedded applications, including implanted medical devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02 was officially released sometime shortly after. WDC licensed the design to Synertek, NCR, GTE Microcircuits, and Rockwell Semiconductor. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02. Sanyo later licensed the design as well, and Seiko Epson produced a further modified version as the HuC6280.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in PLCC and QFP packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
The 65C02 is a low cost, general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The register set is small, with a single 8-bit accumulator (A), two 8-bit index registers (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" ($0000 to $00FF), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The stack lies in the next 256 bytes, page one ($0100 to $01FF), and cannot be moved or extended. The stack grows downward with the stack pointer (S or SP) starting at $01FF and decrementing with each byte that is pushed. The 65C02 has a variable-length instruction set, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and may be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip (SoC) designs.
A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
The W65C02S6T is the production version as of 2025[update], and is available in PDIP-40, PLCC-44 and QFP-44 packages. The maximum officially supported Ø2 (primary) clock speed is 14 MHz when operated at 5 volts, indicated by a –14 part number suffix (hobbyists have developed 65C02 homebrew systems that run significantly faster than the official rating). The "S" designation indicates that the part has a fully static core, a feature that supports stopping the Ø2 clock in either phase with no loss of state. Typical microprocessors not implemented in CMOS have dynamic cores and will lose state (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
The "6T" designation indicates the process geometry (0.6µ) and that Taiwan Semiconductor Manufacturing Company (TSMC) is the foundry that produces WDC's wafers.