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Cyrix 6x86
Cyrix 6x86
Cyrix 6x86
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6x86/MII
A Cyrix 6x86-P166 processor
General information
Launched
  • 6x86 - Oct 1995
  • 6x86L - Jan 1997
  • 6x86MX - Jun 1997
  • MII - May 1998
Discontinued
  • 6x86 - Jun 1999
  • 6x86L - Jun 1999
  • 6x86MX - May 1998
  • MII - Early 2000s
Marketed by
Common manufacturers
Performance
Max. CPU clock rate80 MHz to 333 MHz
FSB speeds40 MHz to 100 MHz
Physical specifications
Transistors
  • 4.3M 500 nm
Cores
  • 1
Sockets
Cache
L1 cache
  • 16 KB (6x86/L)
  • 64 KB (6x86MX / MII)
Architecture and classification
ApplicationDesktop
Microarchitecture6x86
Instruction setx86-16, IA-32
Products, models, variants
Core names
  • M1
  • M1L (Low voltage)
  • M1R (3M to 5M)
  • MII (MMX)
Variant
  • 6x86, 6x86L, 6x86MX
History
PredecessorCyrix 5x86
SuccessorCyrix III

The Cyrix 6x86 is a line of fifth and sixth-generation, 32-bit x86 microprocessors designed and released by Cyrix in 1995. Cyrix, being a fabless company, had the chips manufactured by IBM and SGS-Thomson.[1][2] The 6x86 was made as a direct competitor to Intel's Pentium microprocessor line, and was pin compatible.

During the 6x86's development, the majority of applications (office software as well as games) performed almost entirely integer operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget.

This would later prove to be a strategic mistake, as the popularity of the P5 Pentium caused many software developers to hand-optimize code in assembly language, to take advantage of the P5 Pentium's tightly pipelined and lower latency FPU. For example, the highly anticipated first-person shooter Quake used highly optimized assembly code designed almost entirely around the P5 Pentium's FPU. As a result, the P5 Pentium significantly outperformed other CPUs in the game.[3][4][5][6]

After Cyrix was bought by National Semiconductor then later VIA, the 6x86 continued to be produced up until the early 2000s.

History

[edit]

The 6x86, previously under the codename "M1" was announced by Cyrix in October 1995.[2][7][8][9][10] On release only the 100 MHz (P120+) version was available, but a 120 MHz (P150+) version was planned for mid-1995 with a 133 MHz (P166+) model later. The 100 MHz (P120+) 6x86 was available to OEMs for a price of $450 per chip in bulk quantities.[11]

In mid February 1996 Cyrix announced the P166+, P150+, and P133+ to be added to the 6x86 model line.[12] IBM, who produced the chips, also announced they will be selling their own versions of the chips.[13]

The 6x86 P200+ was planned for the end of 1996,[12] and ended up being released in June.[14]

The M2 (6x86MX) was first announced to be in development in mid 1996. It would have MMX and 32-bit optimization. The M2 would also have some of the same features as the Intel Pentium Pro such as register renaming, out-of-order completion, and speculative execution. Additionally it would have 64 KB of cache over the original 6x86 and Pentium Pro's 16 KB.[15] In March 1997 when asked about when the M2 line of processors would begin shipping, Cyrix UK managing director Brendan Sherry stated, "I've read it's going to be May but we've said late Q2 all along and I'm pretty sure we'll make that."[16]

The 6x86L was first released in January 1997 to address the heat issues with the original 6x86 line.[17] The 6x86L had a lower V-core voltage and required a split power plane voltage regulator.

In April 1997 the first laptop to use the 6x86 processor was put on sale. They were sold by TigerDirect and had a 12.1in DSTN display, 16 MB of memory, 10x CD-ROM, 1.3 GB hard disk drive, and cost $1,899 for the base price.[18]

Later by the end of May 1997 on the 27th, Cyrix said they would announce details of the new chip line (6x86MX) the day before Computex in June 1997.[19] For the low end of the series, the PR166 6x86MX was available for $190 with higher end PR200 and PR233 versions available for $240 and $320.[20][21] IBM being the producer of Cyrix's chips, would also sell their own version. Cyrix hoped to ship tens of thousands within June 1997 with up to 1 million by the end of the year. Cyrix also expected to release a 266 MHz chip by the end of 1997 and a 300 MHz in the first quarter of 1998.[22] They had slightly better floating-point performance, which cut adding and multiply times by a third, but it was still slower than the Intel Pentium. The M2 also had full MMX instructions, 64 KB of cache over the original 16 KB, and had a lower core voltage of 2.5V over 3.3V of the original 6x86 line.[23][24]

National Semiconductor acquired Cyrix in July 1997.[25][26][27] National Semiconductor was not interested in high performance processors but rather system on a chip devices, and wanted to shift the focus of Cyrix to the MediaGX line.[28]

In January 1998 National Semiconductors produced a 6x86MX processor on a 0.25 micron process technology. This reduced the chip size from 150 square millimeters to 88.[29] National shifted their production of the MII and MediaGX to 0.25 by August.[30]

In September 1998 IBM's licensing partnership with Cyrix was said to be ended by National Semiconductors.[31][32] This was due to National wanting to increase production of Cyrix chips in their own facilities, and because having IBM produce Cyrix's chips was causing issues such as profit losses due to IBM frequently pricing their versions of Cyrix's chips lower.[33] National would be paying $50–55 million to IBM to end the partnership, which would end the following April. National would then be moving chip production to their own facility in South Portland, Maine.[34][35]

The Cyrix MII was released in May 1998. These chips were not exciting like people had hoped, as they were just a rebranding of the 6x86MX.[36] In December these chips cost $80 for a MII-333, $59 for a MII-300, $55 for a MII-266, and $48 for a MII-233.[37]

In May 1999 National Semiconductor decided to leave the PC chip market due to significant losses, and put the Cyrix CPU division up for sale.[38][25]

VIA bought the Cyrix line in June 1999, and ended the development of high performance processors. The MII-433GP would be the last processor produced by Cyrix.[39] Additionally after VIA's acquisition, the 6x86/L was discontinued, but the 6x86MX/MII line continued to be sold by VIA.[40][41]

VIA would continue to produce the MII throughout the early 2000s. It was expected to be discontinued when the VIA Cyrix MII was released.[42] However, the MII was still available for sale until mid/late 2003, being shown on VIA's website as a product until October, and it still saw use in devices such as network computers.[43][44]

Architecture

[edit]
A simplistic block diagram of the Cyrix 6x86 microarchitecture

The 6x86 is superscalar and superpipelined and performs register renaming, speculative execution, out-of-order execution, and data dependency removal.[45] However, it continued to use native x86 execution and ordinary microcode only, like Centaur's Winchip, unlike competitors Intel and AMD which introduced the method of dynamic translation to micro-operations with Pentium Pro and K5. The 6x86 is socket-compatible with the Intel P54C Pentium, and was offered in six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110 MHz, a PR 166+ ran at 133 MHz, etc.).[46]

With regard to internal caches, it has a 16-KB primary cache and a fully associative 256-byte instruction line cache is included alongside the primary cache, which functions as the primary instruction cache.[45]

The 6x86 and 6x86L were not completely compatible with the Intel P5 Pentium instruction set and are not multi-processor capable. For this reason, the chip identified itself as an 80486 and disabled the CPUID instruction by default. CPUID support could be enabled by first enabling extended CCR registers then setting bit 7 in CCR4. The lack of full P5 Pentium compatibility caused problems with some applications because programmers had begun to use P5 Pentium-specific instructions. Some companies released patches for their products to make them function on the 6x86.

Compatibility with the Pentium was improved in the 6x86MX, by adding a Time Stamp Counter to support the P5 Pentium's RDTSC instruction.[47] Support for the Pentium Pro's CMOVcc instructions were also added.[47]

Performance

[edit]

Similarly to AMD with their K5 and early K6 processors, Cyrix used a PR rating (Performance Rating) to relate their performance to the Intel P5 Pentium (pre-P55C), as the 6x86's higher per-clock performance relative to a P5 Pentium could be quantified against a higher-clocked Pentium part. For example, a 133 MHz 6x86 will match or outperform a P5 Pentium at 166 MHz, and as a result Cyrix could market the 133 MHz chip as being a P5 Pentium 166's equal. However, the PR rating was not an entirely truthful representation of the 6x86's performance.[48]

While the 6x86's integer performance was significantly higher than P5 Pentium's, its floating-point performance was more mediocre—between 2 and 4 times the performance of the 486 FPU per clock cycle (depending on the operation and precision). The FPU in the 6x86 was largely the same circuitry that was developed for Cyrix's earlier high performance 8087/80287/80387-compatible coprocessors, which was very fast for its time—the Cyrix FPU was much faster than the 80387, and even the 80486 FPU. However, it was still considerably slower than the new and completely redesigned P5 Pentium and P6 Pentium Pro-Pentium III FPUs. One of the main features of the P5/P6 FPUs is that they supported interleaving of FPU and integer instructions in their design, which Cyrix chips did not integrate. This caused very poor performance with Cyrix CPUs on games and software that took advantage of this.[49][50]

Therefore, despite being very fast clock by clock, the 6x86 and MII were forced to compete at the low-end of the market as AMD K6 and Intel P6 Pentium II were always ahead on clock speed. The 6x86's and MII's old generation "486 class" floating-point unit combined with an integer section that was at best on-par with the newer P6 and K6 chips meant that Cyrix could no longer compete in performance.

Models and variants

[edit]

6x86

[edit]

The 6x86 (codename M1) was released by Cyrix in 1996. The first generation of 6x86 had heat problems. This was primarily caused by their higher heat output than other x86 CPUs of the day and, as such, computer builders sometimes did not equip them with adequate cooling. The CPUs topped out at around 25 W heat output (like the AMD K6), whereas the P5 Pentium produced around 15 W of waste heat at its peak. However, both numbers would be a fraction of the heat generated by many high performance processors, some years later. Shortly after the original M1, the M1R was released. The M1R was a switch from SGS-Thomson 3M process to IBM 5M process, making the 6x86 chips 50% smaller.

  • Early Cyrix 6x86 (M1) die shot
    Early Cyrix 6x86 (M1) die shot

6x86L

[edit]

The 6x86L (codename M1L) was later released by Cyrix to address heat issues; the L standing for low-power. Improved manufacturing technologies permitted usage of a lower Vcore. Just like the Pentium MMX, the 6x86L required a split power plane voltage regulator with separate voltages for I/O and CPU core.

  • Cyrix 6x86L (M1L) die shot
    Cyrix 6x86L (M1L) die shot

6x86MX / MII

[edit]

Another release of the 6x86, the 6x86MX, added MMX compatibility along with the EMMI instruction set, improved compatibility with the Pentium and Pentium Pro by adding a Time Stamp Counter and CMOVcc instructions respectively, and quadrupled the primary cache size to 64 KB. The 256-byte instruction line cache can be turned into a scratchpad cache to provide support for multimedia operations.[47] Later revisions of this chip were renamed MII, to better compete with the Pentium II processor. 6x86MX / MII was late to market, and couldn't scale well in clock speed with the manufacturing processes used at the time.

  • Cyrix 6x86MX (M2) die shot
    Cyrix 6x86MX (M2) die shot

Model table

[edit]
Images Model Core name Process size
(μm) 		Die area
(mm2) 		Number of transistors
(millions) 		Socket(s) Package Core Voltage TDP (W) Clock speed Bus Speed L1 Cache Price (USD) Launch
PR90+ M1 0,65 394 3.0 Socket 7 CPGA 3.3 15.5 80 MHz 40 MHz 16 KB $84 Nov 1995
PR120+ M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 100 MHz 50 MHz 16 KB $450 Oct 1995
PR133+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3 19.1 110 MHz 55 MHz 16 KB $326 2-5-1996
PR150+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 20.1 120 MHz 60 MHz 16 KB $451 2-5-1996
PR166+ M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 21.8 133 MHz 66 MHz 16 KB $621 2-5-1996
PR200+ M1R 0,44 ? 3.0 Socket 7 CPGA 3.52 17.13 150 MHz 75 MHz 16 KB $499 6-6-1996
L-PR120+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 100 MHz 50 MHz 16 KB ? Jan-1997
L-PR133+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 110 MHz 55 MHz 16 KB ? Feb-1997
L-PR150+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 ? 120 MHz 60 MHz 16 KB ? Mar-1997
L-PR166+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 15.98 133 MHz 66 MHz 16 KB ? Apr-1997
L-PR200+ M1L 0,35 169 3.0 Socket 7 CPGA 2.8/3.3 17.13 150 MHz 75 MHz 16 KB ? Apr-1997
PR166-MMX MII 0,35 197 6.0 Socket 7 CPGA 2.9/3.3 ?

?

133 MHz

150 MHz

66 MHz

60 MHz

64 KB $190

?

5-30-97

Q2 1998

PR200-MMX MII 0,35 (IBM)

0,30 (NS)

197

156

6.0 Socket 7 CPGA 2.9/3.3 ?

?

150 MHz

166 MHz

75 MHz

66 MHz

64 KB $240

?

5-30-97

Q2 1998

PR233-MMX MII 0,35 (IBM)

0,30 (NS)

197

156

6.0 Socket 7 CPGA 2.9/3.3 ?

?

188 MHz

200 MHz

75 MHz

66 MHz

64 KB $320

?

5-30-97

Q2 1998

PR266-MMX MII 0,35 (IBM)

0,30 (NS)

197

156

6.0 Socket 7 CPGA 2.9/3.3 ? 208 MHz 83 MHz 64 KB $180

?

3-19-98

Q2 1998

MII-300-MMX (*m) MII 0,30

0,25

156

88

6.0 Super 7 CPGA 2.9/3.3

2.2 (*m)

?

?

233 MHz

225 MHz

66 MHz

75 MHz

64 KB $180

?

4-14-98

Q1 1999

MII-333-MMX (*m) MII 0,30

0,25

156

88

6.0 Super 7 CPGA 2.9/3.3

2.2 (*m)

?

?

250 MHz 100 MHz

83 MHz

64 KB $180

?

6-15-98

Mar-1999

MII-350-MMX MII 0,25 88 6.0 Super 7 CPGA 2.9/3.3 ? 270 MHz

250 MHz

90 MHz

83 MHz

64 KB ?

?

?

?

MII-366-MMX MII 0,25 88 6.0 Super 7 CPGA 2.9/3.3 ? 250 MHz 100 MHz 64 KB ? Mar-1999
MII-400-MMX (*m) MII 0,18 65 6.0 Super 7 CPGA 2.2/3.3 ? 285 MHz 95 MHz 64 KB ? Jun-1999
MII-433-MMX (*m) MII 0,18 65 6.0 Super 7 CPGA 2.2/3.3 ? 300 MHz 100 MHz 64 KB ? Jun-1999
SGS-Thomson 6x86 Models
ST6x86P90+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 17.39 80 MHz 40 MHz 16 KB ? ?
ST6x86P120+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 19.98 100 MHz 50 MHz 16 KB ? 2-5-1996
ST6x86P133+HS M1 0,65 394 3.0 Socket 7 CPGA 3.52 21.46 110 MHz 55 MHz 16 KB ? 2-5-1996
ST6x86P150+HS M1 0,65 225 3.0 Socket 7 CPGA 3.52 ? 120 MHz 60 MHz 16 KB ? 2-5-1996
ST6x86P166+HS M1 0,65 225 3.0 Socket 7 CPGA 3.52 ? 133 MHz 66 MHz 16 KB ? 2-5-1996
ST6x86P200+HS M1 0,44 ? 3.0 Socket 7 CPGA 3.52 ? 150 MHz 75 MHz 16 KB ? ?
IBM 6x86 Models
2V2100 GB M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 80 MHz 40 MHz 16 KB ? ?
2V2P120GC M1 0,65 394 3.0 Socket 7 CPGA 3.3 ? 100 MHz 50 MHz 16 KB ? ?
2V2120 GB M1R 0,65 394 3.0 Socket 7 CPGA 3.33 ? 100 MHz 50 MHz 16 KB ? ?
2V2P150GE M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 ? 120 MHz 60 MHz 16 KB ? 2-5-1996
2V2P166GE M1R 0,65 225 3.0 Socket 7 CPGA 3.3/3.52 21.8 133 MHz 66 MHz 16 KB ? 2-5-1996
2V7P200GE M1R 0,44 ? 3.0 Socket 7 CPGA 3.52 14 150 MHz 75 MHz 16 KB ? 2-5-1996
2VAP120 GB M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 100 MHz 50 MHz 16 KB ? ?
2VAP150 GB M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 120 MHz 60 MHz 16 KB ? ?
2VAP166 GB M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 133 MHz 66 MHz 16 KB ? ?
2VAP200 GB M1L 0,35 169 3.0 Socket 7 CPGA 2.8 ? 150 MHz 75 MHz 16 KB ? ?
AVAPR166 GB MII 0,35 197 6.0 Socket 7 CPGA 2.9/3.3 ? 133 MHz 66 MHz 64 KB $202 5-30-97
? MII 0,35 197 6.0 Socket 7 CPGA 2.9/3.3 ? 150 MHz 60 MHz 64 KB ? 5-30-97
BVAPR200 GB MII 0,35 ? 6.0 Socket 7 CPGA 2.9/3.3 ? 150 MHz 75 MHz 64 KB $369 5-30-97
AVAPR200GA MII 0,30 ? 6.0 Socket 7 CPGA 2.9/3.3 ? 166 MHz 66 MHz 64 KB ? Q2 1998
BVAPR233GC MII 0,35 ? 6.0 Socket 7 CPGA 2.9/3.3 ? 166 MHz 83 MHz 64 KB $477 5-30-97
AVAPR233 GB MII 0,30 ? 6.0 Socket 7 CPGA 2.9/3.3 ? 188 MHz 75 MHz 64 KB ? Q2 1998
BVAPR233GD MII 0,30 ? 6.0 Socket 7 CPGA 2.9/3.3 ? 200 MHz 66 MHz 64 KB ? Q2 1998
BVAPR266GE MII 0,35

0,30

? 6.0 Socket 7 CPGA 2.9/3.3 ? 208 MHz 83 MHz 64 KB ? 3-19-98

Q2 1998

CVAPR300GF (*m) MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3 ? 225 MHz 75 MHz 64 KB $217 3-19-98
DVAPR300GF (*m) MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3 ? 233 MHz 66 MHz 64 KB ? ?
CVAPR333GF (*m) MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3

2.2 (*m)

? 250 MHz 83 MHz 64 KB $299 3-19-98
? MII 0,25 119 6.0 Super 7 CPGA 2.9/3.3 ? 263 MHz 75 MHz 64 KB ? ?
? - Missing information

*m -Available in mobile version for laptops

Information From:

Timeline

[edit]
Timeline of Cyrix Products
Cyrix 6x86Cyrix 6x86Cyrix 6x86Cyrix 5x86MediaGXCyrix Cx486Cyrix Cx486SLCCyrix Cx486Cyrix Cx486SLCCyrix Cx486SLC82S8783S8783D87
See also: Cyrix

See also

[edit]

Competitors

[edit]

References

[edit]

Further reading

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Cyrix 6x86

View on Grokipedia
from Grokipedia
The 6x86 is a family of 32-bit x86-compatible superscalar microprocessors developed by the fabless company Corporation and introduced in 1996 as a direct competitor to Intel's processors. Featuring a 64-bit internal data path, an integrated 80-bit (FPU), and 16 KB of unified L1 write-back cache, the 6x86 supported Socket 5 and Super Socket 7 interfaces with clock speeds ranging from 80 MHz to 333 MHz. It employed advanced features such as branch prediction and to enhance performance, while using a "Pentium Rating" (PR) marketing system to equate its capabilities to Intel's offerings, such as the PR166+ model operating at 133 MHz. Cyrix announced the 6x86, codenamed M1, in October 1995, with the first production models like the PR120+ at 100 MHz shipping in early 1996; the chips were fabricated on a 0.65 μm process by partners including and SGS-Thomson Microelectronics. Designed from scratch rather than reverse-engineered from 's architecture, the 6x86 combined RISC and CISC elements for efficient x86 instruction handling, excelling in workloads but underperforming in floating-point tasks due to its FPU limitations, which notably impacted early 3D gaming like Quake. The family expanded to include the low-voltage 6x86L variant for power-sensitive applications and the 6x86MX (codenamed ) and its enhanced MII versions, released in 1997, which added Intel MMX multimedia extensions, quadrupled the L1 cache to 64 KB (including a 256-byte instruction line cache), and supported higher clocks up to 233 MHz on later 0.25 μm shrinks. Despite its budget appeal and strong value in non-floating-point applications, the 6x86 faced challenges from incomplete Pentium instruction set compatibility, high heat output, and compatibility issues with some motherboards, contributing to Cyrix's acquisition by in 1997 and eventual rebranding under . The processors played a key role in the 1990s x86 market by providing affordable upgrades for 486-era systems, helping to democratize before Cyrix shifted focus to embedded and mobile designs.

Development and History

Origins and Announcement

Cyrix Corporation was established in 1988 as a fabless company by engineers Jerry Rogers and Tom Brightman, initially specializing in high-performance x87 math coprocessors compatible with Intel's 286 and 386 processors to provide cost-effective alternatives in the x86 ecosystem. The company aimed to challenge Intel's market dominance by developing x86-compatible chips that offered competitive performance without requiring full-scale fabrication facilities of their own. The 6x86 processor line stemmed from Cyrix's goal to deliver Pentium-level performance at a lower , emphasizing compatibility with existing Socket 5 motherboards to enable straightforward upgrades from 486-based systems. This design approach focused on superscalar execution to boost processing efficiency, allowing the chip to run standard PC software while targeting budget-conscious OEMs and consumers seeking enhanced capabilities without new hardware investments. Cyrix formally announced the 6x86 on October 6, 1995, introducing the initial model as the PR120+ variant clocked at 100 MHz and priced at $450 in quantities of 1,000 units. The processor was positioned as outperforming Intel's 100 MHz in integer tasks, with claims of up to 2.5 times the performance of a 486 in Windows environments, marking 's first full-fledged entry into the sixth-generation x86 market. As a fabless designer, partnered with Microelectronics and SGS-Thomson Microelectronics for initial fabrication of the 6x86 using a 0.65 μm process, under a five-year agreement established in September 1993 that also covered prior 486 and 5x86 chips. This collaboration enabled rapid production scaling while leveraging their manufacturing expertise to meet demand for the Socket 5-compatible CPU.

Company Acquisitions and Discontinuation

In July 1997, announced its acquisition of Corporation in a stock-swap deal valued at approximately $550 million, with the merger completed later that year on November 17. This move integrated Cyrix's CPU division into National's operations, aiming to combine Cyrix's x86 processor expertise—particularly the 6x86 line—with National's strengths in analog and mixed-signal technologies to develop system-on-a-chip solutions for low-cost PCs and appliances. However, National's primary interest lay in embedded and mobile applications rather than high-performance desktop processors, leading to a strategic pivot away from aggressive competition in the mainstream x86 market. By mid-1999, National decided to divest its struggling unit amid ongoing losses from price wars and compatibility challenges in the desktop segment. On June 30, 1999, signed a to acquire 's assets for $167 million, with the deal finalized on September 10, 1999. Under VIA, the focus shifted further toward embedded systems, mobile processors, and integration with VIA's chipset portfolio, including merging designs with those from to create low-power C3-series chips. This transition marked the end of independent development for high-end 6x86 variants, as VIA prioritized cost-effective solutions over desktop performance. Production of the 6x86 family, including its MX and MII enhancements, wound down between 2001 and 2003 as VIA phased out the line in favor of newer architectures. Key factors included the industry's rapid shift to Socket 370 platforms and superior competitors like AMD's and Intel's , which outpaced Cyrix in performance and ecosystem support. Manufacturing scalability issues at foundries like further hampered yields and cost competitiveness. Overall, Cyrix produced an estimated 5-6 million 6x86 units across licensees, capturing a peak of around 7% before declining due to intensified rivalry and ongoing fixes for compatibility problems.

Technical Architecture

Core Design Features

The Cyrix 6x86 processor features a superscalar with dual pipelines, known as the X and Y pipelines, enabling the execution of up to two instructions per clock cycle in parallel. This design incorporates superpipelining across seven stages per pipeline—Instruction Fetch (IF), Decode 1 (ID1), Decode 2 (ID2), Calculation 1 (AC1), Calculation 2 (AC2), Execute (EX), and Write-Back (WB)—to reduce execution stalls and facilitate higher clock speeds. The core supports the full x86 instruction set, encompassing both 16-bit (x86-16) and 32-bit () modes, along with an integrated 80-bit (FPU) compatible with the instruction set and IEEE-754 standard. It provides partial compatibility with Intel's architecture, including support for Pentium bus cycles and signals on the Socket 5 interface, while ensuring seamless operation with x86 operating systems and software such as , DOS, and UNIX variants. However, early implementations of the 6x86 lack MMX instruction support, which was incorporated in subsequent enhancements like the 6x86MX. To enhance efficiency in mixed code environments, the processor includes a branch prediction unit with a 256-entry, 4-way set-associative Branch Target Buffer (BTB) and an 8-entry return stack, enabling and minimizing branch-related penalties in both 16-bit and 32-bit applications. Dynamic instruction scheduling is achieved through out-of-order completion after the EX stage, supported by , data forwarding, and bypassing mechanisms, which allow faster instructions to retire without disrupting overall program flow. Additionally, the core utilizes internal clock multipliers of 2x or 3x relative to the external bus clock, configurable via the CLKMUL pin, to achieve performance gains on Socket 5 motherboards while maintaining compatibility with existing systems.

Cache System and Pipelining

The Cyrix 6x86 processor features a 16 KB unified Level 1 (L1) cache that serves both instructions and , organized as a 4-way set-associative with 32-byte cache lines and a dual-ported design to enable simultaneous code fetches and operations across its integer pipelines or . This unified structure, employing a replacement , supports write-back policies for modified lines and write-through for shared lines, with cache flushes triggered by the FLUSH# signal to write back dirty before invalidation. Complementing the main cache is a 256-byte fully associative instruction line cache acting as a prefetch buffer, which holds eight 32-byte lines filled from the unified cache to accelerate sequential instruction fetches and bypass the larger cache on hits. The processor lacks an on-chip Level 2 (L2) cache, relying instead on external motherboard-based secondary caching for additional , while its 64-bit external data bus facilitates efficient data transfers, including burst modes such as the compatible "one-plus-four" sequence or linear burst for cache line fills involving four 64-bit transfers. is handled by a (TLB) comprising a direct-mapped 128-entry main TLB for 4 KB page translations, augmented by a four-entry fully associative Directory Table Entry (DTE) cache and additional segment-level caches to minimize walks and support x86 virtual addressing without excessive thrashing. In later variants like the 6x86MX and , the cache subsystem was enhanced to a 64 KB split L1 configuration, with separate instruction and caches for improved hit rates and bandwidth. The pipelining architecture employs dual independent 7-stage integer pipelines (X and Y), each comprising instruction fetch (IF), two decode stages (ID1 and ID2), two address calculation stages (AC1 and AC2), execution (EX), and write-back (), enabling superscalar execution of up to two while processing in-order through the EX stage and allowing out-of-order completion thereafter. This superpipelined design, with seven stages per pipeline versus the Pentium's five, reduces per-stage clock constraints to support higher core frequencies up to 150 MHz, incorporating , forwarding, and a 256-entry Branch Target Buffer for to mitigate branch penalties. These optimizations contribute to efficient integer throughput by overlapping fetch, decode, and execution phases across the dual units.

Models and Variants

Original 6x86 (M1)

The original Cyrix 6x86, codenamed M1, was released in early 1996, with the initial model operating at a core clock speed of 100 MHz and a PR rating of 120+. Subsequent variants reached up to 133 MHz core speed with a PR166+ rating, using a 2x clock multiplier on bus speeds from 50 MHz to 66 MHz. Manufactured on a 0.65 μm process by and SGS-Thomson, the processor contained approximately 3 million transistors. The chip utilized a 296-pin staggered (SPGA) package compatible with Socket 5 motherboards, operating at a 3.3 V core voltage with 5 V I/O tolerance. Full compatibility often required updates on Socket 5 or 7 systems, as the processor initially identified itself as a 486-class CPU, potentially limiting recognition of its Pentium-level capabilities without adjustments. It featured a baseline superscalar, superpipelined architecture with dual integer pipelines, an 80-bit , and a 16 KB unified L1 write-back cache, serving as the foundation for later 6x86 variants. Lacking support for Intel's MMX instruction set, the 6x86 was optimized for integer-heavy workloads prevalent in office productivity software and general 16/32-bit applications of the era, such as Windows 95 and DOS-based programs. Its dense design contributed to significant heat dissipation challenges, with reports of potential system instability from overheating under load; Cyrix recommended active cooling solutions like heatsinks with fans to mitigate thermal issues.

Low-Power 6x86L

The 6x86L, introduced in January 1997, represented a power-optimized iteration of the original 6x86 , specifically engineered to mitigate thermal challenges associated with earlier models. Available initially at clock speeds of 100 MHz (PR120+ rating), it scaled up to 150 MHz (PR200+ rating) in subsequent releases through April 1997, utilizing a 296-pin staggered (SPGA) package compatible with motherboards. Manufactured on a 0.35 μm five-metal-layer process with approximately 3 million transistors and a die size of 169 mm², the 6x86L employed a split voltage scheme—2.8 V for the core and 3.3 V for I/O pins—to facilitate efficient power delivery via dual-plane regulators. This variant maintained the core superscalar architecture of the 6x86, including its 16 KB unified L1 cache and execution strengths, while incorporating modifications for reduced energy use, such as clock throttling to dynamically adjust based on workload demands. Enhanced features, including low-power suspend mode, stop-clock capability, and support for (SMM), further enabled idle states with minimal dissipation, making it well-suited for emerging mobile and low-heat desktop applications like battery-powered laptops. Compared to the standard 6x86, the 6x86L achieved a 25% or greater reduction in power draw through these optimizations and the lower core voltage, without altering the fundamental instruction set or structure. Despite its innovations, the 6x86L saw a brief production lifecycle, primarily as an interim solution for power-constrained systems before the transition to the multimedia-enhanced 6x86MX in mid-1997. Early adopters included configurations, with the first systems featuring the processor appearing in April 1997, underscoring its role in bridging Cyrix's Pentium-era offerings toward more integrated platforms. also produced licensed versions under the same branding, leveraging shared fabrication to ensure availability during this period.

Enhanced 6x86MX and MII

The Cyrix 6x86MX, introduced in late May 1997 and available by early June, represented a significant upgrade to the original 6x86 lineup, targeting multimedia applications with enhanced features for Socket 7 systems. Operating at core clock speeds of 133 MHz to over 200 MHz, it carried PR ratings from PR200+ to PR300+, positioning it as competitive with Intel's Pentium MMX processors in integer and multimedia workloads. A key addition was full support for Intel's MMX instruction set, enabling optimized performance in video decoding and graphics tasks, while the on-chip L1 cache was expanded to 64 KB of unified write-back memory (quadrupling the original 16 KB), improving data throughput and reducing latency. Building on the MX foundation, the MII (based on the M2 core), debuted in April 1998, with initial shipments following in May, and pushed clock speeds higher to a maximum of around 285 MHz while adopting a more refined 0.25 μm manufacturing process for better efficiency and heat management. This variant integrated an L2 cache controller to interface with external secondary cache up to 1 MB, allowing configurable synchronous or asynchronous operation to boost overall system performance in memory-intensive scenarios. Like its predecessor, the MII retained the 64 KB L1 cache and MMX support, but incorporated architectural tweaks such as an enhanced 384-entry L2 TLB for faster handling. Both the 6x86MX and MII maintained full compatibility with the interface, supporting speeds up to 100 MHz in Super Socket 7 configurations, which enabled higher effective bandwidth compared to standard 66 MHz setups. PR ratings extended up to PR333+ for certain 200 MHz core variants and higher for later models, reflecting Cyrix's emphasis on perceived performance equivalence to chips despite actual clock differences. To address early 6x86 compatibility issues, such as incomplete Pentium instruction support, the MX and MII added features like a (TSC) for the RDTSC instruction and refined CPUID reporting, ensuring smoother operation with /NT and other x86 software. However, scaling beyond 285 MHz proved challenging due to the limitations of Cyrix's 0.25 μm process and fab partnerships, which lagged behind competitors' transitions to 0.18 μm, constraining yield and power efficiency at higher frequencies.

Performance Characteristics

Integer and Benchmark Results

The Cyrix 6x86 exhibited strong performance relative to its contemporaries, particularly in workloads involving office productivity and system-level tasks. In Ziff-Davis Norton System (SI) benchmarks, which emphasize CPU throughput, the 150 MHz 6x86 (PR200+) scored 1020.4, outperforming the 200 MHz Pentium's 632.0 by approximately 61%, highlighting the 6x86's architectural advantages in execution such as dual pipelines and branch prediction. Similarly, the 133 MHz 6x86 (PR166+) achieved 907.0 in Norton SI, surpassing the 166 MHz Pentium's 525.8 by about 72%. These results underscore the 6x86's efficiency in -heavy operations like data compression and basic database processing. Cyrix's PR rating system provided a standardized measure of this integer dominance, derived from Ziff-Davis Winstone 96 benchmarks across 13 Windows applications in categories including business graphics, database, , and word processing. Conducted by MicroDesign Resources on identically configured systems, the compared 6x86 scores to equivalents; for instance, the 100 MHz 6x86 scored 71.7 in Winstone 96, closely matching the 120 MHz 's 70.9 and demonstrating per-MHz superiority in mixed tasks. The 150 MHz 6x86 (PR200+) earned a Winstone 96 score of 91.6, edging out the 200 MHz 's 89.0 and equating its office application performance to that speed grade. In comparisons with rivals, the 6x86 generally led in benchmarks against the , which trailed the by about 7% in integer performance per clock while matching or slightly exceeding it in some database operations. Against the NexGen Nx586, the 6x86 showed advantages in tasks like compression, benefiting from its more mature superscalar design that allowed higher throughput in 16/32-bit code mixes, though both outperformed the clock-for-clock in non-floating-point workloads. Overclocking extended the 6x86's integer capabilities, with the 100 MHz model often reaching 150 MHz on compatible motherboards using the 3x multiplier and 50 MHz bus, yielding performance gains of 15-20% in benchmarks like Norton SI due to improved thermal management in later steppings. Success rates improved with 2.7V or 3.7V cores, though stability required enhanced cooling.

Floating-Point and Compatibility Challenges

The 6x86's represented a significant weakness compared to contemporary processors, as it was essentially a modified version of the older 80387 design integrated on-chip. While this FPU offered 2-4 times the performance of the 80486's external , it lacked the advanced pipelining and parallel execution capabilities of the 's dedicated FPU, resulting in high latency and inefficiency for floating-point operations. This architectural simplicity made the 6x86 particularly unsuited for workloads involving intensive floating-point calculations, such as scientific simulations or graphics rendering. Early 6x86 models suffered from notable software compatibility issues, often being misdetected by operating systems and applications as an Intel 80486-class processor due to incomplete support for the 's instruction set extensions and CPUID reporting. This led to crashes in applications utilizing for graphics acceleration, as the software assumed a more capable FPU for floating-point transformations. In gaming, these limitations were starkly evident; for instance, the 6x86 struggled with id Software's Quake, achieving maximum frame rates of around 15 FPS at standard resolutions, which was 30-40% lower than comparable systems running the same software-accelerated title. Subsequent revisions and the enhanced 6x86MX variant addressed some of these shortcomings through improved FPU emulation software and Cyrix-specific drivers that better aligned the processor with -compatible code paths, reducing crash frequency in DirectX-dependent applications. However, full compatibility often still required these proprietary patches, and the underlying FPU hardware remained a bottleneck. Additionally, the 6x86's 0.65 μm contributed to higher power draw and heat generation than Intel's more refined 0.35 μm , leading to throttling during prolonged floating-point workloads that stressed the inefficient unit. Cyrix recommended enhanced cooling solutions to mitigate these issues, but overheating persisted as a common complaint in FP-heavy scenarios.

Market and Legacy

Competition and Reception

The Cyrix 6x86 captured a modest but notable portion of the x86 CPU market in the late , estimated at around 3% by revenue in and aiming for up to 10% through partnerships with manufacturers like . It gained traction in the budget PC segment, where it was integrated into affordable systems targeting home and small business users, often pricing complete Cyrix-based PCs 20-30% lower than equivalent configurations—for instance, a 6x86MX PR233 system sold for approximately $400 less than a comparable setup. This value proposition helped Cyrix challenge 's dominance in entry-level markets, though its overall share remained limited compared to 's 88% and AMD's 5%. Reception of the 6x86 was mixed, with praise for its cost-effectiveness in business applications like and NT workloads, where it often outperformed Intel's MMX in integer-heavy tasks such as office productivity suites. However, it faced significant criticism in gaming due to (FPU) weaknesses, particularly evident in titles like Quake, where it underperformed compared to the Pentium MMX. Reviewers noted that while the chip excelled in business benchmarks like Winstone 97 (outperforming a Pentium MMX-166 by 8–13%), its gaming shortcomings alienated enthusiasts and highlighted architectural limitations. The 6x86 engaged in fierce rivalry with the and , positioning itself as a alternative with performance ratings (PR) that controversially claimed equivalence to higher-clocked chips, such as labeling a 133 MHz model as PR166+ to suggest Pentium-level speed. These PR ratings ignited marketing disputes, as competitors like and accused of misleading consumers by overemphasizing integer gains while downplaying FPU deficits, fueling a broader "CPU wars" in industry publications. Despite edges in some business metrics, the K6's balanced performance and the Pentium MMX's superior support ultimately overshadowed the 6x86 in direct comparisons. In retro computing communities as of the , the 6x86 enjoys renewed interest among enthusiasts for overclocking projects, with vintage builds leveraging its affordability and upgrade potential from 486-era systems, often praised for enabling high-performance retro gaming rigs without modern hardware costs. Throughout the , pursued multiple lawsuits against , primarily targeting its x86-compatible processors as unauthorized clones of 's designs. A prominent case began in 1992 when sued in federal court, alleging infringement of patents related to the 486 architecture. This dispute was settled in 1994 through mutual dismissal of claims, with dropping its concurrent antitrust allegations against , though no broad cross-licensing agreement was immediately established. Additional litigation followed, including 's 1993 suit over U.S. No. 4,914,588 ('338 patent) concerning pipelining, which courts partially invalidated in 's favor by 1994, limiting 's enforcement scope. In response, Cyrix filed a significant countersuit against on May 13, 1997, in collaboration with (DEC), which lodged a parallel action on the same day. Cyrix accused of infringing its patents, focusing on technologies for bus interfaces and cache used in the and processors. DEC's suit targeted similar products for infringing 10 of its own patents on related bus and caching innovations, dating from 1988 to 1996. These actions stemmed from 's alleged unauthorized use of licensed technologies originally developed by Cyrix and DEC. The 1997 lawsuits culminated in settlements that favored cross-licensing arrangements. and resolved their dispute in February 1998, dismissing all claims without disclosed financial terms, but extending National Semiconductor's existing broad patent cross-license with to cover following its July 1997 acquisition by National for $550 million in stock. Similarly, and DEC settled in October 1997 for $700 million, including Intel's purchase of DEC's semiconductor assets and a 10-year cross-license. While achieved partial victories, such as court rulings narrowing 's patent assertions, the protracted legal battles imposed substantial costs, contributing to 's merger with National to leverage its patent protections and stabilize operations. These disputes profoundly shaped the by normalizing cross-licensing as a mechanism for resolving conflicts among competitors. The settlements reinforced second-sourcing practices, allowing firms like and to produce compatible processors under licensed terms, but they also exposed the formidable legal barriers erected by Intel's aggressive enforcement, which deterred smaller challengers and consolidated market power among licensees like that held earlier agreements dating to the 1980s.

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