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CSG 65CE02
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CSG 65CE02
The CSG 65CE02 is an 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family, developed from the CMOS WDC 65C02 released by the Western Design Center in 1983.
Like the 65C02, the 65CE02 was built on a 2 µm CMOS process instead of the original 6502's 8 µm NMOS technology, making the chip smaller (and thus less expensive) as well as using much less power. In addition to changes made in the 65C02, the 65CE02 also included improvements to the processor pipeline to allow one-byte instructions to complete in 1 cycle, rather than the 6502's (and most variants) minimum of 2 cycles. It also removed 1 cycle delays when crossing page boundaries. These changes improved performance as much as 25% at the same clock speed.
Other changes included the addition of a third index register, Z, along with the addition and modification of a number of instructions to use this register. The zero-page, the first 256 bytes of memory that were used as pseudo-registers, could now be moved to any page in main memory using the B(ase page) register. The stack register was widened from 8 to 16-bits using a similar page register, SPH (stack pointer high), allowing the stack to be moved out of page one and to grow to larger sizes.
The 65CE02 was the basis for the system on a chip CSG 4510 that was developed for the unreleased Commodore 65. The 65CE02 was later used for the A2232 serial port card for the Amiga computer. It appears to have seen no other use.
The original 6502 was designed in the era before microcomputers existed, when microprocessors were used as the basis for simpler systems like smart terminals, desktop calculators and many different industrial controller systems. This was also an era when memory devices were generally based on static RAM, which was very expensive and had low memory density. For both of these reasons, the ability to handle large amounts of memory (for the era) was not required, and many processors had operating modes that worked with small portions of a larger address space in order to offer higher performance. Such was the case in the 6502, which used the first memory page, or "zero page", to provide faster access, and the second page, "page one", to hold a 256-byte stack.
By the late 1970s, the original MOS Technology team that designed the 6502 had broken up. Bill Mensch had moved to Arizona and set up the Western Design Center (WDC) to provide 6502-based design services. Around 1981, the main licensees of the 6502 design, Rockwell Semiconductor, GTE and Signetics, began a redesign effort with Mensch that led to the WDC 65C02. This was mainly a CMOS implementation of the original NMOS 6502 that used 10 to 20 times less power, but it also included a number of new instructions to help improve the code density in certain applications. New instructions included INA/DEA to increment and decrement the accumulator, STZ to write a zero to a memory location, and BRA which was a jump with a branch-style 1-byte relative address. The 65C02 also fixed a number of minor flaws (and at least one outright bug) in the original 6502 design.
By the time the 65C02 was introduced, the original design assumptions were no longer valid; many machines based on these processors now shipped with the maximum 64 kB that the 6502 could address, using the far less expensive and denser dynamic RAM. The speed advantages of the zero page addressing mode remained, but now existing within a memory space that was dramatically larger. Likewise, the single-page call stack was now a pittance within the overall memory, and high-level languages that made prodigious use of stack space could not easily run on the 6502. The 65C02, largely intended to be a low-power 6502, retained these disadvantages.
The 65CE02 is a further improved version of the 65C02 which expands the memory model to make it more suitable for a system with large amounts of main memory. To do this, it adds the following new features:
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CSG 65CE02 AI simulator
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CSG 65CE02
The CSG 65CE02 is an 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family, developed from the CMOS WDC 65C02 released by the Western Design Center in 1983.
Like the 65C02, the 65CE02 was built on a 2 µm CMOS process instead of the original 6502's 8 µm NMOS technology, making the chip smaller (and thus less expensive) as well as using much less power. In addition to changes made in the 65C02, the 65CE02 also included improvements to the processor pipeline to allow one-byte instructions to complete in 1 cycle, rather than the 6502's (and most variants) minimum of 2 cycles. It also removed 1 cycle delays when crossing page boundaries. These changes improved performance as much as 25% at the same clock speed.
Other changes included the addition of a third index register, Z, along with the addition and modification of a number of instructions to use this register. The zero-page, the first 256 bytes of memory that were used as pseudo-registers, could now be moved to any page in main memory using the B(ase page) register. The stack register was widened from 8 to 16-bits using a similar page register, SPH (stack pointer high), allowing the stack to be moved out of page one and to grow to larger sizes.
The 65CE02 was the basis for the system on a chip CSG 4510 that was developed for the unreleased Commodore 65. The 65CE02 was later used for the A2232 serial port card for the Amiga computer. It appears to have seen no other use.
The original 6502 was designed in the era before microcomputers existed, when microprocessors were used as the basis for simpler systems like smart terminals, desktop calculators and many different industrial controller systems. This was also an era when memory devices were generally based on static RAM, which was very expensive and had low memory density. For both of these reasons, the ability to handle large amounts of memory (for the era) was not required, and many processors had operating modes that worked with small portions of a larger address space in order to offer higher performance. Such was the case in the 6502, which used the first memory page, or "zero page", to provide faster access, and the second page, "page one", to hold a 256-byte stack.
By the late 1970s, the original MOS Technology team that designed the 6502 had broken up. Bill Mensch had moved to Arizona and set up the Western Design Center (WDC) to provide 6502-based design services. Around 1981, the main licensees of the 6502 design, Rockwell Semiconductor, GTE and Signetics, began a redesign effort with Mensch that led to the WDC 65C02. This was mainly a CMOS implementation of the original NMOS 6502 that used 10 to 20 times less power, but it also included a number of new instructions to help improve the code density in certain applications. New instructions included INA/DEA to increment and decrement the accumulator, STZ to write a zero to a memory location, and BRA which was a jump with a branch-style 1-byte relative address. The 65C02 also fixed a number of minor flaws (and at least one outright bug) in the original 6502 design.
By the time the 65C02 was introduced, the original design assumptions were no longer valid; many machines based on these processors now shipped with the maximum 64 kB that the 6502 could address, using the far less expensive and denser dynamic RAM. The speed advantages of the zero page addressing mode remained, but now existing within a memory space that was dramatically larger. Likewise, the single-page call stack was now a pittance within the overall memory, and high-level languages that made prodigious use of stack space could not easily run on the 6502. The 65C02, largely intended to be a low-power 6502, retained these disadvantages.
The 65CE02 is a further improved version of the 65C02 which expands the memory model to make it more suitable for a system with large amounts of main memory. To do this, it adds the following new features: