Clipper architecture

The Clipper architecture is a 32-bit reduced instruction set computer (RISC)-like central processing unit (CPU) instruction set architecture designed by Fairchild Semiconductor. The architecture had little market success: the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.

The Clipper architecture used a simplified instruction set compared to earlier complex instruction set computer (CISC) architectures, but it did incorporate some more complex instructions than were present in other contemporary RISC processors. These instructions were implemented in a so-called Macro Instruction read-only memory (ROM) within the Clipper CPU. This scheme allowed the Clipper to have somewhat higher code density than other RISC CPUs.

The initial Clipper microprocessor produced by Fairchild was the C100, which became available in 1986. This was followed by the faster C300 from Intergraph in 1988. The final model of the Clipper was the C400, released in 1990, which was extensively redesigned to be faster and added more floating-point arithmetic registers. The C400 processor combined two key architectural techniques to achieve a new level of performance: superscalar instruction dispatch and superpipelined operation.

While many processors of the time used either superscalar instruction dispatch or superpipelined operation, the Clipper C400 was the first processor to use both.

Intergraph started work on a subsequent Clipper processor design known as the C5, but this was never completed or released. Nonetheless, some advanced processor design techniques were devised for the C5, and Intergraph was granted patents on these. These patents, along with the original Clipper patents, have been the basis of patent-infringement lawsuits by Intergraph against Intel and other companies.

Unlike many other microprocessors, the Clipper processors were actually sets of several distinct chips. The C100 and C300 consist of three chips: one central processing unit containing both an integer unit and a floating point unit, and two cache and memory management units (CAMMUs), one responsible for data and one for instructions. The CAMMUs contained caches, translation lookaside buffers, and support for memory protection and virtual memory. The C400 consists of four basic units: an integer CPU, an FPU, an MMU, and a cache unit. The initial version used one chip each for the CPU and FPU and discrete elements for the MMU and cache unit, but in later versions the MMU and cache unit were combined into one CAMMU chip.

The Clipper has 16 integer registers (R15 is used as the stack pointer), 16 floating-point registers (limited to 8 in early implementations), plus a program counter (PC), a processor status word (PSW) containing ALU and FPU status flags and trap enables, and a system status word (SSW) containing external interrupt enable, user/supervisor mode, and address translation control bits.

User and supervisor modes has separate banks of integer registers. Interrupt handling consisted of saving the PC, PSW, and SSW on the stack, clearing the PSW, and loading the PC and SSW from a memory trap vector.