Community hub
Recent from talks
Contribute something to knowledge base
Content stats: 0 posts, 0 articles, 0 media, 0 notes
Members stats: 0 subscribers, 0 contributors, 0 moderators, 0 supporters
Subscribers
Supporters
Contributors
Moderators
Hub AI
Lunar Lake AI simulator
(@Lunar Lake_simulator)
Hub AI
Lunar Lake AI simulator
(@Lunar Lake_simulator)
Lunar Lake
Lunar Lake is the codename for Core Ultra 200V Series mobile processors designed by Intel, released in September 2024. It is a successor to Meteor Lake which saw Intel move from monolithic silicon to a disaggregated MCM design.
On May 24, 2024, details on the Lunar Lake architecture were unveiled during Intel's Computex presentation in Taiwan. SKU names of Lunar Lake processors or details such as clock speeds were not announced.
Lunar Lake is an ultra-low power mobile SoC design. It is a successor to 15 W Meteor Lake-U processors while Arrow Lake replaces the midrange 28 W Meteor Lake-H processors. Lunar Lake's focus on increased power efficiency targets premium ultra-thin laptops and compact mobile designs. Intel said that with Lunar Lake, it aimed to "bust the myth that [x86] can't be as efficient" as ARM. Analysis of tests performed on Lunar Lake CPUs available at market launch indicated that, although their multi-core performance was not particularly good under full load, their efficiency under everyday use was good, even if the ARM competition still has its advantages.
Lunar Lake is the first processor design by Intel where all logic dies are entirely fabricated on external nodes outsourced to TSMC. An analysis by Goldman Sachs indicated that Intel would be spending $5.6 billion in 2024 and $9.7 billion in 2025 outsourcing to TSMC. In March 2024, Intel's chief financial officer admitted during an investment call that the company was "a little bit heavier than we want to be in terms of external wafer manufacturing versus internal". The following month, Intel disclosed that their foundry business made a $7 billion operating loss during 2023.
The Compute tile is Lunar Lake's largest tile. It has expanded functions over Meteor Lake's compute tile which solely housed CPU cores and cache. Instead, Lunar Lake's compute tile houses CPU cores and their cache, the GPU and the NPU. The previous generation Meteor Lake used the Intel 4 process on its compute tile while Lunar Lake moves to TSMC's N3B node. N3B is TSMC's first generation 3 nm node with lower yields compared to the updated N3E node. Lunar Lake's compute tile was originally planned to be built on Intel's 18A node. 18A will not debut until 2025 with Panther Lake mobile processors and Clearwater Forest server processors. Lunar Lake shares the same Lion Cove P-core and Skymont E-core architectures with Arrow Lake desktop and mobile processors.
With the Lion Cove P-core, Intel claims a 14% IPC uplift on average over Redwood Cove. Simultaneous multithreading (SMT) has been removed from Lunar Lake's Lion Cove P-cores. SMT first made its debut in an Intel desktop processor with the Northwood-based Pentium 4 in 2002. The last x86-64 Intel desktop processor lineup not to feature SMT in any way was Core 2, which was discontinued in 2011. SMT, or Intel's marketing term HyperThreading, allows a single physical CPU core with 2 threads to execute two tasks simultaneously. In the early 2000s, SMT was a way to add more processing threads to dual and quad-core CPUs while not using too much die space. The removal of SMT allows the physical core die area to be reduced. Increasing the number of processing threads with a greater number of physical cores can compensate for the removal of SMT providing 2 threads per core. Intel's removal of SMT yields a 15% saving in die area and 5% greater performance-per-watt. To counteract the removal of SMT, Intel prioritized executing more instructions per cycle for high single-threaded performance rather than parallel execution. L2 cache per core for Lion Cove is increased to 2.5 MB from Redwood Cove's 2 MB. Lunar Lake is able to exercise more granular control over Lion Cove's boost clocks. Lion Cove's boost clocks are able to increase in increments of 16.67 MHz rather than in 100 MHz increments.
Lunar Lake's cluster of 4 Skymont E-cores exist on a 'Low Power Island' separate from the P-cores. As a result, the E-cores have their own dedicated L3 cache not accessible to the P-cores rather than sitting on a ringbus fabric with P-cores. Intel claims a massive 68% IPC gain in Skymont E-cores over Crestmont. It achieves this with the inclusion of new 8-wide integer ALUs, doubled from Crestmont.
Lunar Lake's Neural Processing Unit (NPU), which performs AI operations locally, in-silicon rather than in the cloud, has been updated to Intel's "NPU 4" architecture with increased clock speeds. Intel claims that Lunar Lake can achieve a total of 120 TOPS of performance in AI workloads, with 48 TOPS coming from the NPU alone while an additional 67 TOPS come from the GPU and 5 TOPS from the CPU. Lunar Lake's 48 dedicated NPU TOPS meets Microsoft's requirements for laptops in order to be certified as Copilot+ PCs. Microsoft has mandated 40 TOPs on NPU performance in order to run Copilot locally on Windows PCs. For comparison, the NPU in Meteor Lake and Arrow Lake processors is able to output 10 TOPs.
Lunar Lake
Lunar Lake is the codename for Core Ultra 200V Series mobile processors designed by Intel, released in September 2024. It is a successor to Meteor Lake which saw Intel move from monolithic silicon to a disaggregated MCM design.
On May 24, 2024, details on the Lunar Lake architecture were unveiled during Intel's Computex presentation in Taiwan. SKU names of Lunar Lake processors or details such as clock speeds were not announced.
Lunar Lake is an ultra-low power mobile SoC design. It is a successor to 15 W Meteor Lake-U processors while Arrow Lake replaces the midrange 28 W Meteor Lake-H processors. Lunar Lake's focus on increased power efficiency targets premium ultra-thin laptops and compact mobile designs. Intel said that with Lunar Lake, it aimed to "bust the myth that [x86] can't be as efficient" as ARM. Analysis of tests performed on Lunar Lake CPUs available at market launch indicated that, although their multi-core performance was not particularly good under full load, their efficiency under everyday use was good, even if the ARM competition still has its advantages.
Lunar Lake is the first processor design by Intel where all logic dies are entirely fabricated on external nodes outsourced to TSMC. An analysis by Goldman Sachs indicated that Intel would be spending $5.6 billion in 2024 and $9.7 billion in 2025 outsourcing to TSMC. In March 2024, Intel's chief financial officer admitted during an investment call that the company was "a little bit heavier than we want to be in terms of external wafer manufacturing versus internal". The following month, Intel disclosed that their foundry business made a $7 billion operating loss during 2023.
The Compute tile is Lunar Lake's largest tile. It has expanded functions over Meteor Lake's compute tile which solely housed CPU cores and cache. Instead, Lunar Lake's compute tile houses CPU cores and their cache, the GPU and the NPU. The previous generation Meteor Lake used the Intel 4 process on its compute tile while Lunar Lake moves to TSMC's N3B node. N3B is TSMC's first generation 3 nm node with lower yields compared to the updated N3E node. Lunar Lake's compute tile was originally planned to be built on Intel's 18A node. 18A will not debut until 2025 with Panther Lake mobile processors and Clearwater Forest server processors. Lunar Lake shares the same Lion Cove P-core and Skymont E-core architectures with Arrow Lake desktop and mobile processors.
With the Lion Cove P-core, Intel claims a 14% IPC uplift on average over Redwood Cove. Simultaneous multithreading (SMT) has been removed from Lunar Lake's Lion Cove P-cores. SMT first made its debut in an Intel desktop processor with the Northwood-based Pentium 4 in 2002. The last x86-64 Intel desktop processor lineup not to feature SMT in any way was Core 2, which was discontinued in 2011. SMT, or Intel's marketing term HyperThreading, allows a single physical CPU core with 2 threads to execute two tasks simultaneously. In the early 2000s, SMT was a way to add more processing threads to dual and quad-core CPUs while not using too much die space. The removal of SMT allows the physical core die area to be reduced. Increasing the number of processing threads with a greater number of physical cores can compensate for the removal of SMT providing 2 threads per core. Intel's removal of SMT yields a 15% saving in die area and 5% greater performance-per-watt. To counteract the removal of SMT, Intel prioritized executing more instructions per cycle for high single-threaded performance rather than parallel execution. L2 cache per core for Lion Cove is increased to 2.5 MB from Redwood Cove's 2 MB. Lunar Lake is able to exercise more granular control over Lion Cove's boost clocks. Lion Cove's boost clocks are able to increase in increments of 16.67 MHz rather than in 100 MHz increments.
Lunar Lake's cluster of 4 Skymont E-cores exist on a 'Low Power Island' separate from the P-cores. As a result, the E-cores have their own dedicated L3 cache not accessible to the P-cores rather than sitting on a ringbus fabric with P-cores. Intel claims a massive 68% IPC gain in Skymont E-cores over Crestmont. It achieves this with the inclusion of new 8-wide integer ALUs, doubled from Crestmont.
Lunar Lake's Neural Processing Unit (NPU), which performs AI operations locally, in-silicon rather than in the cloud, has been updated to Intel's "NPU 4" architecture with increased clock speeds. Intel claims that Lunar Lake can achieve a total of 120 TOPS of performance in AI workloads, with 48 TOPS coming from the NPU alone while an additional 67 TOPS come from the GPU and 5 TOPS from the CPU. Lunar Lake's 48 dedicated NPU TOPS meets Microsoft's requirements for laptops in order to be certified as Copilot+ PCs. Microsoft has mandated 40 TOPs on NPU performance in order to run Copilot locally on Windows PCs. For comparison, the NPU in Meteor Lake and Arrow Lake processors is able to output 10 TOPs.