A numerically controlled oscillator (NCO) is a digital signal generator which creates a synchronous (i.e., clocked), discrete-time, discrete-valued representation of a waveform, usually sinusoidal. NCOs are often used in conjunction with a digital-to-analog converter (DAC) at the output to create a direct digital synthesizer (DDS).

Numerically controlled oscillators offer several advantages over other types of oscillators in terms of agility, accuracy, stability and reliability. NCOs are used in many communications systems including digital up/down converters used in 3G wireless and software radio systems, digital phase-locked loops, radar systems, drivers for optical or acoustic transmissions, and multilevel FSK/PSK modulators/demodulators.

An NCO generally consists of two parts:

When clocked, the phase accumulator (PA) creates a modulo-2^N sawtooth waveform which is then converted by the phase-to-amplitude converter (PAC) to a sampled sinusoid, where N is the number of bits carried in the phase accumulator. N sets the NCO frequency resolution and is normally much larger than the number of bits defining the memory space of the PAC look-up table. If the PAC capacity is 2^M, the PA output word must be truncated to M bits as shown in Figure 1. However, the truncated bits can be used for interpolation. The truncation of the phase output word does not affect the frequency accuracy but produces a time-varying periodic phase error which is a primary source of spurious products. Another spurious product generation mechanism is finite word length effects of the PAC output (amplitude) word.

The frequency accuracy relative to the clock frequency is limited only by the precision of the arithmetic used to compute the phase. NCOs are phase- and frequency-agile, and can be trivially modified to produce a phase-modulated or frequency-modulated output by summation at the appropriate node, or provide quadrature outputs as shown in the figure.

A binary phase accumulator consists of an N-bit binary adder and a register configured as shown in Figure 1. Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size ${\displaystyle \Delta F}$, the integer value of the FCW. In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle latency but allows the adder to operate at a higher clock rate.

The adder is designed to overflow when the sum of the absolute value of its operands exceeds its capacity (2^N−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder ${\displaystyle \phi _{n}}$, called the residual, is stored in the register and the cycle repeats, starting this time from ${\displaystyle \phi _{n}}$ (see figure 2). Since a phase accumulator is a finite-state machine, eventually the residual at some sample K must return to the initial value ${\displaystyle \phi _{0}}$. The interval K is referred to as the grand repetition rate (GRR) given by

where GCD is the greatest common divisor function. The GRR represents the true periodicity for a given ${\displaystyle \Delta F}$ which for a high resolution NCO can be very long. Usually we are more interested in the operating frequency determined by the average overflow rate, given by