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Program status word
Program status word
Program status word
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The program status word[a] (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360[1] and its successors,[2][3][4][5][6] and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24[b] bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

Format

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S/360

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On all but 360/20,[c] the PSW has the following formats. S/360 Extended PSW format only applies to the 360/67 with bit 8 of control register 6 set.

IBM S/360 PSW formats
S/360 Standard PSW[11]

System Mask Key A M W P Interruption Code[12]
0 7 8 11 12 13 14 15 16 31

ILC CC Program
Mask 		Instruction Address
32 33 34 35 36 39 40 63
S/360 Standard PSW abbreviations
Bits Field Meaning
0-7 SM
System Mask
Bit Meaning
0 Channel 0 mask
1 Channel 1 mask
2 Channel 2 mask
3 Channel 3 mask
4 Channel 4 mask
5 Channel 5 mask
6 Channel 6 mask
7 External Mask
8-11 Key PSW key
12 A ASCII
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-31 IC Interruption Code[13]
32-33 ILC Instruction-Length Code[14]
34-35 CC Condition Code
36-39 PM
Program Mask
Bit Meaning
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
40-63 IA Instruction Address
S/360 Extended PSW[15]

spare 24/32
Bit
Mode 		Tran
Ctrl 		I/O
Mask 		Ext.
Mask 		Key A M W P ILC CC Program
Mask 		spare
0 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

Instruction Address
32 63
S/360 Extended PSW abbreviations
Bits Field Meaning
0-3 Spare (must be 0)
4 24/32-bit Address mode
5 Translation Control
6 IO I/O Mask (Summary)
7 EX External Mask (Summary)
8-11 Key Protection Key
12 A ASCII
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 ILC Instruction-Length Code[16]
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
24-31 Spare
32-63 IA Instruction Address

S/370

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IBM S/370 PSW formats
S/370 Basic Control mode PSW[17]

Chan.
Mask 		I
O 		E
X 		Key 0 M W P Interruption Code
0 1 2 4 5 6 7 8 11 12 13 14 15 16 31

ILC CC Program
Mask 		Instruction Address
32 33 34 35 36 39 40 63
S/370 BC mode PSW abbreviations
Bits Field Meaning
0-5 Channel Masks for channels 0-5
6 IO I/O Mask for channels > 5
7 EX External Mask
8-11 Key PSW key
12 E=0 Basic Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-31 IC Interruption Code[18]
32-33 ILC Instruction-Length Code[19]
34-35 CC Condition Code
36-39 PM
Program Mask
Bit Meaning
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
40-63 IA Instruction Address
S/370 Extended Control mode PSW[20]

0 R 0 0 0 T I
O 		E
X 		Key 1 M W P S 0 CC Program
Mask 		0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

0 0 0 0 0 0 0 0 Instruction Address
32 39 40 63
S/370 EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16 S Address-Space Control
0=primary-space mode
1=Secondary-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
40-63 IA Instruction Address

S/370 Extended Architecture (S/370-XA)

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IBM Extended Architecture (XA) PSW format
Extended Architecture Extended Control mode PSW[21]

0 R 0 0 0 T I
O 		E
X 		Key 1 M W P S 0 CC Program
Mask 		0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

A Instruction Address
32 33 63
S/370-XA EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16 S Address-Space Control
0=primary-space mode
1=Secondary-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
32 A Addressing mode
0=24 bit; 1=31 bit
33-63 IA Instruction Address

Enterprise Systems Architecture (ESA)

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IBM Enterprise Systems Architecture (ESA) PSW format
Enterprise Systems Architecture Extended Control mode PSW[22][23]

0 R 0 0 0 T I
O 		E
X 		Key 1 M W P AS CC Program
Mask 		0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

A Instruction Address
32 33 63
ESA EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow[d]
23 Significance[e]
32 A Addressing mode
0=24 bit; 1=31 bit
33-63 IA Instruction Address

z/Architecture

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IBM z/Architecture PSW formats
z/Architecture long PSW[24]

0 R 0 0 0 T I
O 		E
X 		Key 0 M W P AS CC Program
Mask 		R
I 		0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 30 31

B
A 		0
32 33 63

Instruction Address
64 95

Instruction Address (Continued)
96 127
Long PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=0 Must be zero for LPSWE
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
64-127 IA Instruction Address
z/Architecture short PSW[25]

0 R 0 0 0 T I
O 		E
X 		Key 1 M W P AS CC Program
Mask 		R
I 		0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 25 30 31

B
A 		Instruction Address
32 33 63
Short PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=1 Must be one for LPSW
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
33-63 IA Instruction Address

Notes

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References

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Revisions and contributorsEdit on WikipediaRead on Wikipedia

Program status word

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The program status word (PSW) is a in CPU designs, starting from System/360, that combines the function of a and . It contains status information reflecting the current execution state of a program, including condition codes indicating outcomes such as lesser than zero, zero or equal, or greater than zero from arithmetic or logical operations. The PSW serves to encapsulate key processor conditions that influence , , and privilege modes, enabling the operating system to manage interrupts, context switches, and diagnostic information efficiently. Common components include condition code bits that indicate the outcome of the most recent instruction, interruption masks to control asynchronous events, and addressing mode indicators for or architecture-specific behaviors. The PSW incorporates the address of the next instruction to be executed, facilitating precise resumption after interruptions. Notable examples appear in architectures: in systems, the PSW is a 16-byte structure that denotes the system's general status (e.g., wait state or processing mode), interrupt capabilities, and the instruction address, with variants like restart, external, or program PSWs providing diagnostics for events such as machine checks. These implementations highlight the PSW's role in maintaining processor state in mainframe computing environments.

Overview

Definition and Purpose

The Program Status Word (PSW) is a in architectures that combines the functions of a and a , defining the state of the (CPU) for the currently active program. It holds the address of the next instruction to be executed, ensuring continuity in program flow, while also tracking essential execution details such as operational outcomes and system conditions. This dual role allows the PSW to serve as a central control mechanism, preserving the CPU's operational during task execution. The primary purposes of the PSW include maintaining seamless program execution by directing instruction sequencing, signaling conditions that may trigger branching or interrupts, and enforcing storage protection to safeguard . For instance, it facilitates handling by storing the current CPU state and loading a new PSW to transfer control to an appropriate handler, thereby supporting efficient multitasking and error recovery. Additionally, through embedded protection mechanisms, the PSW prevents unauthorized access to by comparing access keys against storage protections, a critical feature for secure multi-programmed environments. In general composition, the PSW typically encompasses an instruction address field for the next executable command, a condition code of 2-4 bits that indicates results such as , overflow, or negative outcomes from prior operations, a program mask to enable or disable specific program exceptions such as fixed-point overflow or overflow, and a system mask to control interrupts such as I/O or external events, along with a protection key to regulate access permissions. Over time, the PSW has evolved from a 64-bit structure in early systems to a 128-bit format in modern implementations, accommodating expanded addressing and enhanced control capabilities without altering its core conceptual framework.

Role in Program Execution

The Program Status Word (PSW) plays a central role in sequencing instructions during program execution by specifying the address of the next instruction to be fetched from main storage. After an instruction is fetched, the instruction address field within the PSW is automatically incremented by the length of that instruction, as indicated by the instruction length code (ILC) field, to point to the subsequent instruction in a linear execution flow. Branching instructions can modify this address based on specified conditions, enabling non-sequential execution such as jumps or calls to subroutines. In exceptional situations like interrupts or mode switches, the PSW ensures continuity by preserving the current execution state. When an interruption occurs, the existing PSW—capturing the precise instruction address, condition code, and control bits—is stored as the "old PSW" in a designated in main storage, allowing the program to resume exactly from the interruption point upon completion of the handling routine. A "new PSW" is then loaded from another predefined storage to initiate the interrupt service, updating the CPU state for the required processing. This mechanism supports seamless transitions between normal program flow and without loss of . The PSW also governs access to and interaction with other CPU components, such as general registers and floating-point status, through its state and fields. For instance, the problem state bit in the PSW determines whether the CPU operates in or problem mode, restricting privileged access to certain registers and operations in user mode to maintain system integrity. Similarly, the program field controls for arithmetic operations involving general registers or floating-point units, influencing how results propagate to the overall execution state. A practical example of the PSW's dynamic role occurs in conditional looping constructs, where arithmetic instructions update the condition code field based on results from general register operations, such as comparisons or additions. The Branch on Condition (BC) instruction then examines this condition code to decide whether to alter the instruction address, for instance, repeating a loop if a counter in a general register remains nonzero after decrementing. This integration allows efficient data-dependent without manual address management.

Historical Development

Origins in System/360

The Program Status Word (PSW) was introduced with the family of computers, announced on April 7, 1964, as a key element in unifying IBM's disparate pre-existing computer lines—such as the scientific 701 series and business-oriented 1401—into a single, compatible architecture spanning low- to high-end models. This design effort, guided by the 1961 SPREAD Task Group recommendations, aimed to create a "New Product Line" that eliminated the fragmentation of hardware, software, and peripherals, enabling seamless data and application portability across the range. The PSW served as the central repository for CPU state information, facilitating this unified approach by standardizing program control and interruption handling in a 64-bit doubleword format. The primary motivations for the PSW's design centered on the need for a compact mechanism to manage program execution status and the instruction counter, essential for supporting multitasking environments and ensuring binary compatibility across System/360 models from the entry-level Model 30 to the high-performance Model 91. In an era of growing complexity, the PSW addressed the challenges of asynchronous events like I/O interruptions and program exceptions by storing all necessary control information—such as the next instruction address and interruption masks—in one accessible unit, allowing efficient state preservation and restoration during context switches. This compactness was crucial for real-time operations and task queuing, as seen in applications like NASA's , while promoting upward and downward compatibility without requiring program rewrites. Key innovations in the PSW included embedding a 24-bit instruction address within the 64-bit structure to support up to 16 megabytes of main storage addressing, balancing immediate hardware capabilities with future scalability across the model lineup. Additionally, the incorporation of a 4-bit protection key provided early memory access control, comparing the PSW key against 2,048-byte storage blocks to prevent unauthorized stores and trigger protection exceptions, enhancing system security in multi-programmed setups. These features centralized status switching and exception handling, marking a departure from prior IBM designs and laying the groundwork for robust, interrupt-driven processing. An early deviation occurred with the System/360 Model 20, a cost-reduced variant introduced to bridge smaller installations, which employed a non-standard 4-byte (32-bit) PSW format due to hardware limitations in its 16-bit register set and simplified . This shorter PSW, consisting of two halfwords for instruction address, condition codes, and limited status bits like channel masks, maintained basic compatibility but omitted full 64-bit features such as extended interruption codes, reflecting the Model 20's role as a transitional subset rather than a full implementation.

Evolution Through System/370 and Successors

The , introduced in 1970, marked a significant in the Program Status Word (PSW) by incorporating an Extended Control (EC) mode alongside the Basic Control (BC) mode for compatibility with the System/360. In EC mode, the PSW expanded to support 31-bit logical addressing, enabling dynamic address translation for virtual storage and addressing up to 16 MB of real memory, a step beyond the 24-bit limit of prior architectures. This addition included new fields such as the translation-control bit (bit 5) to enable or disable address translation and the Program-Event-Recording (PER) mask (bit 1) for , while relocating interruption-related fields like channel masks to main storage or control registers to streamline the 64-bit PSW structure. In the , the System/370 Extended Architecture (S/370-XA), announced in 1981, further refined the PSW to address growing memory demands, mandating EC mode and introducing full 31-bit addressing via the addressing-mode bit (bit 32), which allowed programs to operate in either 24-bit or 31-bit modes for bimodal compatibility. A key enhancement was the address-space-control bit (bit 16), enabling primary- and secondary-space modes to support multiple virtual address spaces of up to 2 GB each, facilitated by control registers for segment-table designations and instructions like SET ADDRESS SPACE CONTROL. These changes supported larger memory configurations and environments, with the PSW retaining its 64-bit format but gaining fields for enhanced interruption validity and space-switching. The 1990s brought the Enterprise Systems Architecture/390 (ESA/390) in 1990, which enhanced the PSW for enterprise-scale operations, including logical partitioning (LPAR) through expanded address-space-control bits (16-17) that defined four modes: primary, secondary, access-register, and home-space. This allowed up to 65,536 address spaces per partition, with bit fields integrating access-list entries (ALETs) and space-switching instructions like PROGRAM CALL to manage partitioned environments on a single system. The PSW remained 64 bits but incorporated additional validity indicators and control-register interactions (e.g., CR13 for home-space designation), improving and resource isolation without altering core compatibility. By the 2000s, , introduced in 2000 with the zSeries 900, shifted the PSW to a 128-bit format to natively support 64-bit addressing, using bits 31 (extended-addressing mode) and 32 (basic-addressing mode) to enable 24-, 31-, or 64-bit operations, addressing up to 16 exabytes of . This evolution included an expanded instruction-address field (bits 64-127) and enhanced dynamic address translation with region tables, while maintaining compatibility modes for ESA/390 via a short 64-bit PSW option in instructions like LOAD PSW. As of 2025, mainframes fully leverage this 128-bit PSW in for , with ongoing support for legacy modes ensuring seamless migration. Overall, the PSW's development from System/370 onward reflects a progression from compatibility-driven expansions—focusing on virtual storage and addressing limits—to comprehensive 64-bit native capabilities, enabling modern IBM Z systems to handle massive-scale workloads while preserving backward compatibility across decades of mainframe evolution.

Access and Manipulation

Instructions for PSW Handling

The Load Program Status Word (LPSW) instruction in IBM System/360 architecture loads a new 8-byte PSW from a doubleword location in main storage, specified by the operand address in the instruction format LPSW D2(B2) with operation code 82 hexadecimal. This privileged instruction, executable only in supervisor state, replaces the current PSW, immediately altering the CPU's execution state, including the instruction address (PSW bits 40-63), condition code (bits 34-35), protection key (bits 8-11), and interruption masks. If executed in problem state, it triggers a privileged-operation exception; additionally, invalid operand addresses (e.g., not on a doubleword boundary) or nonzero protection keys without the protection feature cause specification exceptions. In , the Load PSW Extended (LPSWE) instruction extends this capability for the 16-byte PSW format, using the syntax LPSWE D2(B2) with operation B2B2 , and supports loading in 64-bit while handling transitions between long (64-bit) and short (31-bit or 24-bit) PSW formats. Like LPSW, LPSWE is privileged and causes serialization and checkpoint synchronization upon execution, updating fields such as the (PSW bits 31-32), DAT mode (bit 5), and instruction (bits 64-127 in long format). Loading an invalid PSW via LPSWE—such as one with unassigned bits set or bit 12 zero in certain models—results in a specification exception after loading, with the instruction (ILC) set to zero and potential entry into a program interruption loop unless interrupted by reset. For storing or examining PSW contents without full replacement, the Extract PSW (EPSW) instruction provides a non-privileged mechanism to copy the current PSW into a general register or storage, using formats such as EPSW R1 (operation code B98D hexadecimal in RRE format) for diagnostic purposes in user programs. This read-only operation places PSW bits 0-11 and 13-31 into specified register bits (e.g., 32-43 and 45-63 of GR R1), with bit 44 indicating the PSW format (0 for z/Architecture long PSW), and does not alter the execution state. Complementing this, the Set PSW Key from Address (SPKA) instruction, privileged and formatted as SPKA R1,D2(X2,B2) (operation code E1C0 hexadecimal), stores the current PSW key (bits 8-11) into bits 56-59 of a target register while setting the PSW key from the low-order bits of an address operand, facilitating selective updates to storage protection without full PSW replacement. Earlier systems, such as System/360 and System/370, relied solely on the 8-byte LPSW for PSW loading, treating it as a 64-bit entity with implicit short-format handling. Modern implementations maintain backward compatibility by automatically converting 8-byte PSWs loaded via LPSW to 16-byte format (e.g., inverting bit 12), but LPSWE enables direct manipulation of extended fields, including selective updates to masks and addresses in 64-bit mode without requiring full privileged reloads in some contexts.

Privileged and Compatibility Modes

The Program Status Word (PSW) enforces privilege levels in architectures by distinguishing between supervisor state, which allows kernel-level operations with full access to privileged instructions and system resources, and problem state, which confines user programs to non-privileged instructions to prevent unauthorized system interference. In supervisor state, the processor can execute all instructions, including those for I/O control and storage manipulation, whereas problem state restricts access to sensitive operations, such as modifying control registers or issuing interrupts, to maintain system security. This mode is determined by a designated bit in the PSW, for example, bit 15 set to 0 for supervisor state and 1 for problem state in System/360. Problem state further limits access to certain PSW fields, such as protection keys, to avoid tampering with system controls. In System/360, initial privilege enforcement combined the supervisor bit with key-based protection, where the PSW's 4-bit protection key (bits 8-11) is matched against storage keys for 2,048-byte blocks to block invalid accesses, triggering a protection exception on mismatch. Subsequent architectures retained this foundation but added layers like PSW-key masks in control registers to authorize specific keys only in problem state. These mechanisms collectively restrict problem-state programs from altering critical PSW elements, such as interruption masks or addressing controls. Compatibility modes in the PSW bridge architectural generations by emulating legacy formats and addressing schemes. The short PSW, an 8-byte format in , supports 24-bit and 31-bit legacy addressing on 64-bit processors, enabling older applications to run without modification during initial program load or mode transitions. In System/370, Extended Control (EC) mode activates virtual addressing by setting PSW bit 12 to 1, allowing dynamic address translation via segment and page tables for up to 16 megabytes of space, while Basic Control mode (bit 12 = 0) preserves System/360 compatibility without translation. Mode switching between privileged and compatibility states is managed through the Load PSW (LPSW) instruction, a privileged operation that replaces the current PSW with values from a specified operand address, but only validly from supervisor state to avoid security risks. The processor validates transitions, such as prohibiting a direct switch to supervisor state from problem state without an intervening interruption like a supervisor call, which would otherwise cause a specification exception if PSW bits are invalid. Interruptions automatically store the old PSW and load a new one from fixed locations, facilitating controlled mode changes. Attempts to violate privilege rules, such as executing a restricted instruction in problem state, invoke or operation exceptions that halt execution and transfer control to a handler via PSW update. In contemporary environments, PSW modes underpin by isolating guest OS privileges through address-space controls and mode enforcement. The evolution of PSW modes reflects a progression from System/360's rudimentary key-based and supervisor bit to more sophisticated features in later systems. System/370 introduced EC mode for virtual addressing alongside AMODE and SMODE indicators to support 24-bit and 31-bit compatibility. further extended this with 64-bit addressing via PSW bits 31-32, ensuring legacy code portability while enhancing capabilities.

Formats by Architecture

System/360 Format

The Program Status Word (PSW) in the IBM System/360 architecture is a 64-bit doubleword that encapsulates essential control information for program execution, including interruption masks, status indicators, and the address of the next instruction to be fetched. It is always treated as residing at a location with an even address and is loaded as a complete unit, with the operand address for the Load PSW (LPSW) instruction required to be on a doubleword boundary (low-order bits 0-2 zero); otherwise, a specification exception occurs. The PSW's bit layout is as follows, with bits numbered 0 (most significant) to 63 (least significant):
BitsFieldDescription
0-7System MaskEight bits controlling interruption classes: bits 0-6 mask I/O channels 0-6, bit 7 masks external interruptions (e.g., timer or external signals); a 1 enables interruptions in that class, while 0 disables them but allows pending conditions to accumulate.
8-11Protection KeyFour-bit field (values 0-15) that specifies the storage protection key for the current program; it is compared against the key of each 2,048-byte (2K) block of storage accessed—if they match or the PSW key is 0, access is permitted; if the protection feature is not installed, this field must be zeros, or a specification exception results.
12Compatibility Flag (A-bit)Selects the sign code for decimal results: 0 for EBCDIC (zone 1111), 1 for USASCII-8 (zone 0101); this bit is unused in non-decimal operations.
13Machine-Check Mask (M-bit)Controls machine-check interruptions: 1 enables them, 0 disables but allows pending checks.
14Wait State (W-bit)Indicates processor state: 1 places the CPU in a wait state (no instruction execution, responsive to interruptions), 0 indicates running state.
15Problem State (P-bit)Defines execution mode: 1 for problem state (user mode, restricting privileged instructions), 0 for supervisor state (full access).
16-31ReservedZeros in the current PSW; during interruption processing, these bits store the 16-bit interruption code identifying the cause (e.g., 0x0004 for supervisor call).
32-33Instruction Length Code (ILC)Two bits indicating the length of the interrupted or last-executed instruction in halfwords: 00 (2 bytes), 01 (4 bytes), 10 (6 bytes); value 11 is reserved.
34-35Condition Code (CC)Two bits summarizing the result of the previous instruction: 0 indicates equal/zero, 1 low/less than zero, 2 high/greater than zero, 3 overflow or special condition (e.g., unnormalized result or test under mask failure).
36-39Program MaskFour bits masking program exceptions: bit 36 for fixed-point overflow, bit 37 for decimal overflow, bit 38 for exponent underflow, bit 39 for significance (loss in floating-point); 1 enables interruption on occurrence, 0 suppresses it but sets the condition code.
40-63Instruction AddressRight-justified 24-bit address of the next instruction byte to execute; bit 63 is always 0, providing addressing up to 16 megabytes of storage.
In the System/360 Model 67, an extended PSW variant supports 32-bit addressing for virtual memory, activated by setting bit 4 of the PSW to 1 (indicating extended addressing mode) and bit 5 to 1 (enabling relocation); in this mode, the instruction address field expands to use bits 32-63 (with bits 32-39 zero in 24-bit mode otherwise), allowing access to up to 4 gigabytes via segment and page translation, while bits 0-3 must be zero to avoid a specification exception. The condition code in the PSW reflects outcomes like equality or overflow from prior operations to guide branching decisions.

System/370 Format

The Program Status Word (PSW) in the IBM System/370 architecture maintains backward compatibility with the System/360 through its Basic Control (BC) mode while introducing enhancements in Extended Control (EC) mode to support expanded addressing and additional control features. In BC mode, the 64-bit PSW format is identical to that of the System/360, ensuring seamless execution of legacy programs in non-virtual environments without modifications. This mode limits addressing to 24 bits, positioning the instruction address in bits 40-63, with bits 0-39 dedicated to interruption masks, condition code, program mask, and reserved fields set to zero for compatibility. In contrast, EC mode employs a full 64-bit PSW that incorporates System/370-specific extensions, including a protection key, timing facility bit, and support for 31-bit addressing, enabling up to 2 gigabytes of addressable storage. This mode is the default for System/370 operations and is used when saving the PSW during interruptions, where the old PSW is stored at real locations 0-63 and the new PSW loaded from 64-127. The EC PSW structure allocates bits 0-4 for the I/O interruption mask, which selectively enables interruptions from up to five I/O channels; bit 5 for DAT mode (1 enables dynamic address translation); bit 6 for the external interruption mask (enabling signals from external devices); and bit 7 for the problem state bit (1 denotes restricted user-mode privileges, 0 indicates supervisor mode). Bits 8-11 hold the PSW key, a 4-bit value that governs access to main storage blocks during real addressing. Bit 12 is the machine-check mask; bit 13 is the wait state (1 indicates the CPU is paused and not fetching instructions). Bits 14-17 are reserved and must be zero. Bits 18-19 form the condition code, a 2-bit value reflecting the outcome of the last instruction (e.g., 0 for equal/comparable, 1 for low/greater, 2 for high/less, 3 for overflow or special conditions). Bits 20-23 form the program mask, controlling whether certain program exceptions (such as fixed-point overflow in bit 20 or decimal overflow in bit 21) cause interruptions. Bit 24 as the T-bit for the timing facility, which when set to 1 enables CPU timer interrupts for performance monitoring; and bits 25-31 as reserved (must be zero). Bit 32 serves as the addressing-mode bit (AM bit), with 0 specifying 24-bit addressing (for compatibility, placing the 24-bit instruction address in bits 40-63 and requiring bits 33-39 to be zero) and 1 enabling 31-bit addressing (using bits 33-63 directly for the full 31-bit instruction address). In DAT-off mode (dynamic address translation disabled), the AM bit acts as the extension bit to toggle between these addressing modes without invoking virtual storage mechanisms. Bits 33-63 then contain the instruction address for the next sequential execution, either 24 bits (right-justified when AM=0) or 31 bits (fully utilized when AM=1). This design supports the transition to larger memory configurations while preserving the ability to run System/360 code in BC mode.
Bit PositionsFieldDescription
0-4I/O MaskEnables I/O interruptions for channels 0-4 (1=enabled).
5DAT Mode1=DAT on (virtual addressing enabled); 0=real addressing.
6External Mask1=enables external interruptions; 0=masked.
7Problem State1=problem (user) state; 0= state.
8-11PSW Key4-bit storage key for real-mode access checks.
12Machine-Check Mask1=enables machine-check interruptions.
13Wait State1=CPU in wait state (no instruction fetch); 0=executing.
14-17Must be 0.
18-19Condition Code (CC)2-bit status: 0=equal/normal, 1=low/greater, 2=high/less, 3=overflow/special.
20-23Program MaskControls exceptions (e.g., bit 20=fixed-point overflow, bit 21= overflow).
24T-Bit (Timing)1=enables CPU for timing facility interruptions.
25-31Must be 0.
32 (AM)0=24-bit addressing; 1=31-bit addressing (extension bit in DAT-off).
33-63Instruction AddressNext instruction location: 24-bit (bits 40-63, bits 33-39=0 when AM=0) or 31-bit (full range when AM=1).

S/370 Extended Architecture Format

The Program Status Word (PSW) in System/370 Extended Architecture (S/370-XA) operates exclusively in extended control (EC) mode, extending the 64-bit format from the prior System/370 architecture to support 31-bit addressing and advanced virtual storage management. Bits 0-15 retain the same structure as the System/370 EC mode PSW, encompassing the condition code (bits 0-1), program mask (bits 2-5), I/O mask (bit 6), external mask (bit 7), PSW key (bits 8-11), machine-check mask (bit 12), wait state (bit 13), problem state (bit 14), and address-space control (ASC) bit (bit 15, where 0 indicates primary space and 1 indicates secondary space). This continuity ensures basic compatibility for legacy code execution within the enhanced framework. Key enhancements appear in the upper bits, introducing fields for address-space management and extended addressing. Bit 16 specifies the addressing mode (AMODE), determining whether 24-bit or 31-bit addressing is active. Bit 17 indicates supervisor key validity, affecting storage protection enforcement. Bits 18-23 hold the primary ASN key, while bits 24-31 contain the secondary ASN, collectively forming the address-space control elements that identify and validate the current virtual address space. These ASN fields enable the association of processes with specific address spaces, supporting up to 65,536 distinct 2 GB address spaces through dynamic address translation (DAT). Bit 32 through bit 63 comprise the 31-bit instruction address, with bit 32 serving as the addressing mode bit (always set to 1 for 31-bit mode in full XA operation) and bits 33-63 providing the effective 31-bit pointer to the next instruction, aligned such that bit 0 of the address is implicitly zero. The new address-space control fields (bits 16-31) represent a fundamental shift toward , allowing multiple independent address spaces without relying solely on s for ASN assignment. DAT mode, which enables virtual-to-real address , is controlled by PSW bit 5 (set to 1 for on) in conjunction with control register 0 bit 5; when active, it leverages two-level page and segment tables to map the 31-bit virtual addresses. This setup permits real and virtual storage up to 2 GB (2^{31} bytes), a significant expansion from the 16 MB limit of 24-bit addressing in System/370. Programs operating in 31-bit mode can access the full range, but transitions between modes require explicit instructions to avoid addressing exceptions. Adopting S/370-XA necessitates updated linkage conventions, such as the PROGRAM CALL and PROGRAM RETURN instructions, to properly stack and restore the extended PSW fields during subroutine calls or context switches. Legacy System/370 PSW formats, lacking the new bits 16-31 and the extended instruction address, trigger access exceptions or specification exceptions when loaded in XA mode, enforcing a clean migration path for operating systems and applications. This design prioritizes for 24-bit programs running under DAT-on while mandating 31-bit awareness for new virtual storage features.

Enterprise Systems Architecture Format

The Program Status Word (PSW) in the Enterprise Systems Architecture (ESA) format, particularly for ESA/390 in extended control (EC) mode, is a 64-bit structure that extends the System/370 Extended Architecture (XA) design with refinements tailored to enterprise-scale computing environments. Introduced with the S/390 processors in , this format supports 31-bit addressing while maintaining with prior architectures, enabling seamless operation in logically partitioned systems. The PSW governs critical aspects of program execution, including handling, selection, and floating-point operations, with specific bits dedicated to masking exceptions and specifying operational modes. Building on XA, the ESA PSW incorporates bit 22 as the hexadecimal floating-point (HFP) exponent underflow mask, which was renamed and refined from earlier implementations to control underflow handling—setting the result to when the bit is zero or normalizing the when it is one. Bits 24-31 handle space-switch events, which facilitate controlled transitions between primary, secondary, access-register, and home spaces during operations such as program calls or transfers. Bits 32-63 store the 31-bit instruction , allowing programs to operate within a 2 GB virtual space per region. These elements ensure robust support for multi-tasking and in enterprise settings. ESA enhancements emphasize integration with advanced services, including the EXCP macro for low-level I/O control, where PSW bits enable direct channel command word (CCW) chaining without operating system intervention. The PSW also includes provisions for access register specification through its address space control (ASC) field, permitting up to 16 access registers (0-15) to designate dataspaces and regions via access-list-entry tokens (ALETs). This supports efficient private space operations beyond traditional primary/secondary spaces. Compatibility is preserved by retaining XA PSW formats and adding a dedicated mode for System/370 emulation, allowing legacy applications to run unaltered on S/390 hardware. As part of the shift to scalable enterprise , ESA's PSW design facilitated the consolidation of mainframe workloads in partitioned environments. Key field specifics include bit 16, which designates the addressing mode (AMODE) as part of the ASC configuration, and bit 14, which indicates problem state (zero for supervisor, one for problem state). ASN (access space number) fields, inherited from XA and managed via control registers 3 and 4, integrate with the PSW's ASC bits to enable multi-space operations, where each space is limited to 2 GB under 31-bit addressing. The following table summarizes the primary PSW fields relevant to ESA/390 EC mode:
Bit PositionField NameDescription
22HFP Exponent Underflow MaskControls underflow response: 0 sets result to zero; 1 normalizes fraction.
24-31Space-Switch EventManages events for address space transitions (e.g., via PROGRAM CALL).
32-63Instruction Address31-bit address of the next instruction to execute (bits 33-63 effective).
16AMODE (in ASC)Specifies addressing mode within address space control (00/01/10/11 codes).
14Problem State0 for supervisor (privileged); 1 for problem (user) state.
ASC (15-17)Address Space ControlSelects mode: primary (00), access-register (01), secondary (10), home (11); integrates ASN for multi-space access up to 2 GB per space.

z/Architecture Format

The format defines the Program Status Word (PSW) for mainframes, emphasizing 64-bit addressing capabilities introduced to handle vast memory spaces in enterprise computing. This 128-bit long PSW supersedes prior 64-bit formats by incorporating extended fields for management and protection, enabling operations on systems supporting up to 16 exabytes of . It builds briefly on the Enterprise Systems Architecture (ESA) foundation but introduces incompatible changes for full 64-bit support, aligning with the architectural shift toward larger-scale processing as seen in successors to System/370. The long PSW structure spans 128 bits, with specific fields allocated as follows:
BitsFieldDescription
0–55Format and ControlIncludes interruption masks (e.g., I/O mask bits 0-4 at 0-4, external at 6), wait state (13), problem state (14), address-space control (17-19), machine-check mask (12), and other control bits such as DAT mode (5) and PSW key (8–11). These govern execution state, privilege levels, and interruption handling.
56–57Condition Code (CC)A 2-bit code (values 0–3) indicating the outcome of the most recent instruction, used for branching decisions and status checks.
58–61Program MaskControls responses to exceptions like fixed-point overflow (58), overflow (59), HFP overflow (60), significance (61).
62–63Other MasksAdditional masks for exponent overflow/underflow.
64–127Instruction Address64-bit address of the next instruction to execute.
Bit 0 acts as the long/short PSW indicator (1 for long format). Access registers and ASNs are managed via separate control registers, not embedded in the PSW. The instruction address supports 64-bit signed values, with low-address preventing branching to addresses below 512 bytes in certain modes. For , a short PSW format uses 64 bits, replicating the ESA layout with a 31-bit instruction address confined to bits 33–63 and control fields in bits 0–32. This allows legacy code execution without modification but limits addressing to 2 GB. As of 2025, the long PSW is integral to operating systems like z/OS and z/VM on IBM Z platforms, where the Load PSW Extended (LPSWE) instruction restores the full 128 bits from storage, including the 64-bit address when the addressing-mode bit (AMODE=2 or 3) indicates 64-bit operation. This facilitates seamless handling of large-scale workloads in virtualized environments.

Usage and Applications

Interrupt and Exception Processing

In IBM mainframe architectures, interruption processing begins when an event such as I/O completion or an external signal triggers the CPU to save the current program status word (PSW) to a designated fixed location in low real storage, preserving the interrupted program's state including the instruction address and control bits. For external interrupts, the old PSW is stored at real addresses 24-31, while for I/O interrupts it is saved at 56-63; a new PSW is then loaded from the corresponding vector location, such as 88-95 for external or 120-127 for I/O, to initiate the handler routine. Exception handling, classified as program interruptions, operates similarly for conditions like protection violations, addressing errors, or invalid PSW formats, where the old PSW is saved to real addresses 40-47 and a supervisor-mode PSW is loaded from 104-111 to transfer control to the operating system. The cause of the exception is indicated by an interruption code stored at locations 142-143 or a condition code reflected in the saved PSW, enabling the handler to diagnose and respond appropriately. Interrupts are categorized as maskable or non-maskable based on PSW control bits: maskable types, such as external interrupts (controlled by PSW bit 7) and I/O interrupts (PSW bit 6), can be suppressed to allow uninterrupted program execution, whereas non-maskable ones like exigent machine-check conditions or restart interruptions always take precedence. The supervisor call (SVC) instruction exemplifies a synchronous program interruption, saving the old PSW at 32-39 and loading a new one from 96-103, with the SVC number placed at 138-139 to invoke specific system services without reliance on mask bits. Upon completion of the interrupt or exception handler, restoration occurs via the Load PSW (LPSW) instruction or equivalent mechanisms like PROGRAM RETURN, which reloads the saved PSW to resume the original program at the point of interruption, thereby ensuring atomic execution and state preservation critical for multitasking environments. In modern implementations, the extended (long) PSW is additionally saved to an interruption buffer or extended save areas (e.g., real addresses 128-255 for machine-check) to support advanced diagnostics and recovery, enhancing system reliability without altering the core saving mechanism.

Operating System Integration

In z/OS, the operating system manages task execution by saving the current Program Status Word (PSW) into the Task Control Block (TCB) during the dispatch process, preserving the processor state for resumption after interruption or context switch. The TCB serves as the primary dispatchable unit, holding the PSW along with registers and priority information to enable the dispatcher to restore execution context efficiently. This mechanism supports multitasking by allowing z/OS to alternate between units of work without losing state. For cross-memory services, z/OS leverages the PSW's Address Space Control (ASC) mode bits to facilitate communication between programs in different address spaces, enabling secure data access across boundaries like primary, secondary, or home spaces. In , the PSW plays a central role in by defining execution modes for guest operating systems, allowing virtual machines to run as if on dedicated hardware. The intercepts PSW load instructions, such as those during interpretive execution via the Start Interpretive Execution (SIE) facility, to enforce isolation and simulate privileged operations without compromising host . This interception ensures that guest PSW modifications do not affect the host environment, supporting concurrent execution of multiple guests on shared hardware. For security, integrates PSW protection keys with the (RACF) to enforce granular over memory regions and resources. The PSW's key bits (positions 8-11) determine the storage key under which a program executes, allowing RACF to validate access requests against user profiles and prevent unauthorized modifications in supervisor or problem states. Programs in PSW key 0-7 gain elevated privileges for resources, but RACF audits these based on the executing key to maintain integrity. The evolution from early systems to modern illustrates PSW enhancements in managing , particularly through the introduction of Address Space Control (ASC) bits in the PSW starting with MVS/XA, alongside the Access Space Number (ASN) concept that assigns unique 12-bit identifiers to (enabling up to 4,096 per system, later expanded in ). These mechanisms allow to handle large-scale by tagging and translating virtual across distinct spaces without conflicts. This capability evolved further in , allowing dual-address-space operations that underpin today's multi-tenant environments.

Variations and Notes

Architectural Compatibility

The maintains with earlier architectures, such as System/360, through the use of a short PSW format that exactly emulates the 8-byte structure defined in the original System/360 Principles of Operation. In ESA/390 , the processor operates with this short PSW, ensuring that problem-state programs written for System/360 or System/370 execute without modification, as the PSW bits for instruction address, condition code, and program mask are preserved identically. Additionally, (AMODE) bits in the PSW—specifically bits 31 and 32—enable seamless mixing of 24-bit, 31-bit, and 64-bit code within the same environment, allowing legacy applications to coexist with modern 64-bit programs without requiring architectural changes. Forward migration from earlier architectures like to and beyond involves updates to linkage conventions, such as stack management for mode transitions, to accommodate expanded addressing and formats. However, PSW designs incorporate reserved bits that must remain zero, providing future-proofing by allowing to assign new functions without disrupting existing software. One notable challenge arose with the , which deviated from the standard 8-byte PSW by using a specialized 4-byte format tailored to its 16-bit register subset and limited instruction set, necessitating software emulators on later systems to run Model 20-specific code. Similarly, bit renamings, such as ESA/390's reassignment of PSW bit 22 from its System/370 role to indicate hexadecimal floating-point (HFP) exponent underflow, preserved functional equivalence while enabling enhancements. The Principles of Operation manuals across generations mandate PSW format invariance, ensuring that software can be recompiled and executed on newer hardware without PSW-related alterations, as long as unassigned bits are zeroed. This standardization has enabled , as of 2025, to support all addressing modes and run unmodified code from the 1960s /360 era through compatibility facilities like the ESA/390-Compatibility-Mode, maintaining operational continuity for decades-old applications in production environments.

Deviations and Nomenclature Changes

The Model 20 implemented a simplified 32-bit Program Status Word (PSW), deviating from the standard 64-bit format used in other System/360 models, primarily due to cost constraints in its low-end design targeted at small-scale applications. This reduced PSW omitted several fields present in the full , such as the key and extended interruption , while emphasizing I/O control fields like the device address (bits 8-11) and function specification (bits 12-15), with the instruction address limited to 16 bits (bits 16-31). The channel mask bit (bit 7) and condition (bits 2-3) were retained but adapted for the model's limited handling, ensuring basic compatibility for simple operations without floating-point or full binary arithmetic support. In the System/370 architecture, nomenclature shifts occurred in the PSW program mask. This change aligned with the shift to Extended Control (EC) mode, where PSW bit 12 (previously the USASCII mode bit in System/360) was repurposed to indicate EC mode operation, enabling dynamic address translation while maintaining with Basic Control (BC) mode. Additionally, the System/370 Model 145 provided partial EC mode support in its PSW, interpreting bit 12 as the EC indicator but lacking full virtual storage capabilities until later upgrades, which restricted its use in advanced multitasking environments despite standard PSW loading via instructions like Load PSW (LPSW). Further nomenclature changes appeared in the Enterprise Systems Architecture/390 (ESA/390), where PSW bit 22 was renamed the HFP (hexadecimal floating-point) exponent underflow mask and bit 23 the HFP significance mask, reflecting enhanced floating-point exception handling to distinguish from the new binary floating-point facilities; the underflow handling sets the result to true zero when the bit is zero or normalizes the fraction when one. These renamings ensured compatibility with legacy software by preserving bit positions while updating functional semantics, as detailed in IBM's architectural manuals for programmers transitioning between modes. Early System/360 prototypes, such as those developed before full production, occasionally omitted protection key handling in the PSW to streamline hardware testing, though this was resolved in released models without affecting standard software portability. IBM documentation, including Principles of Operation manuals for each architecture, explicitly notes these model-specific deviations and nomenclature shifts to guide assembly-language programmers and system integrators, emphasizing that they do not disrupt compatibility for standard operating systems like OS/360 or OS/370, which rely on the core PSW structure. No significant PSW updates related to AI mask bits have been introduced in z/Architecture as of 2025, maintaining the established 128-bit format with extensions focused on vector processing rather than new PSW fields.

References

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