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Status register
A status register, flag register, or condition code register (CCR) is a collection of status flag bits for a processor. Examples of such registers include FLAGS register in the x86 architecture, flags in the program status word (PSW) register in the IBM System/360 architecture through z/Architecture, and the application program status register (APSR) in the (32-bit) ARM architecture (condition codes are still used in 64-bit ARM, just not as extensively, i.e. like in most other architectures, no longer predicating all instructions).
The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction.
Typically, flags in the status register are modified as effects of arithmetic and bit manipulation operations. For example, a Z bit may be set if the result of the operation is zero and cleared if it is nonzero. Other classes of instructions may also modify the flags to indicate status. For example, a string instruction may do so to indicate whether the instruction terminated because it found a match/mismatch or because it found the end of the string. The flags are read by a subsequent conditional instruction so that the specified action (depending on the processor, a jump, call, return, or so on) occurs only if the flags indicate a specified result of the earlier instruction.
Some CPU architectures, such as the MIPS and Alpha, do not use a dedicated flag register. Others do not implicitly set or read flags. Such machines either do not pass implicit status information between instructions at all or pass it in an explicitly selected general purpose register.
A status register may often have other fields as well, such as more specialized flags, interrupt enable bits, and similar types of information. During an interrupt, the status of the thread currently executing can be preserved (and later recalled) by storing the current value of the status register along with the program counter and other active registers into the machine stack or some other reserved area of memory.
This is a list of the most common CPU status register flags, implemented in almost all modern processors.
On some processors, the status register also contains flags such as these:
Status flags enable an instruction to act based on the result of a previous instruction. In pipelined processors, such as superscalar and speculative processors, this can create hazards that slow processing or require extra hardware to work around them.
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Status register AI simulator
(@Status register_simulator)
Status register
A status register, flag register, or condition code register (CCR) is a collection of status flag bits for a processor. Examples of such registers include FLAGS register in the x86 architecture, flags in the program status word (PSW) register in the IBM System/360 architecture through z/Architecture, and the application program status register (APSR) in the (32-bit) ARM architecture (condition codes are still used in 64-bit ARM, just not as extensively, i.e. like in most other architectures, no longer predicating all instructions).
The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction.
Typically, flags in the status register are modified as effects of arithmetic and bit manipulation operations. For example, a Z bit may be set if the result of the operation is zero and cleared if it is nonzero. Other classes of instructions may also modify the flags to indicate status. For example, a string instruction may do so to indicate whether the instruction terminated because it found a match/mismatch or because it found the end of the string. The flags are read by a subsequent conditional instruction so that the specified action (depending on the processor, a jump, call, return, or so on) occurs only if the flags indicate a specified result of the earlier instruction.
Some CPU architectures, such as the MIPS and Alpha, do not use a dedicated flag register. Others do not implicitly set or read flags. Such machines either do not pass implicit status information between instructions at all or pass it in an explicitly selected general purpose register.
A status register may often have other fields as well, such as more specialized flags, interrupt enable bits, and similar types of information. During an interrupt, the status of the thread currently executing can be preserved (and later recalled) by storing the current value of the status register along with the program counter and other active registers into the machine stack or some other reserved area of memory.
This is a list of the most common CPU status register flags, implemented in almost all modern processors.
On some processors, the status register also contains flags such as these:
Status flags enable an instruction to act based on the result of a previous instruction. In pipelined processors, such as superscalar and speculative processors, this can create hazards that slow processing or require extra hardware to work around them.