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28 nm process
28 nm process
28 nm process
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The "28 nm" lithography process is a half-node semiconductor manufacturing process based on a die shrink of the "32 nm" lithography process.[1] It appeared in production in 2010.[2]

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no direct relation to the dimensions on the integrated circuit;[3] neither gate length, metal pitch or gate pitch on a "28 nm" device is twenty-eight nanometers.[4][5][6][7]

Taiwan Semiconductor Manufacturing Company has offered "28 nm" production using high-K metal gate process technology.[8]

GlobalFoundries offers a "28 nm" foundry process called the "28SLPe" ("28 nm Super Low Power") foundry process, which uses high-K metal gate technology.[9]

According to a 2016 presentation by Sophie Wilson, 28 nm has the lowest cost per logic gate. Cost per gate had decreased as processes shrunk until reaching 28 nm, and has slowly risen since then.[10]

Design

[edit]

"28 nm" requires twice the number of design rules for ensuring reliability in manufacturing as "80 nm".[11]

Shipped devices

[edit]

AMD's Radeon HD 7970 uses a graphics processing unit manufactured using a "28 nm" process.[12]

Some models of the PS3 use an RSX 'Reality Synthesizer' chip manufactured using a "28 nm" process.[13]

FPGAs produced with "28 nm" process technology include models of the Xilinx Artix 7 FPGAs and Altera Cyclone V FPGAs.[14]

References

[edit]
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28 nm process

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from Grokipedia
The 28 nm process is a semiconductor manufacturing technology node that employs 28-nanometer lithography to fabricate advanced integrated circuits, representing a significant scaling from prior 32 nm and 40 nm nodes by enabling denser transistor integration and improved performance-per-watt metrics. Introduced into production by Taiwan Semiconductor Manufacturing Company (TSMC) in 2010, it marked a pivotal advancement in CMOS technology, with TSMC becoming the first foundry to offer a general-purpose 28 nm process in 2011. This node introduced key innovations, including high-k metal gate (HKMG) transistors in high-performance variants, which replaced traditional silicon dioxide gates to reduce leakage and boost drive currents, achieving up to 45% speed improvements over TSMC's 40 nm process at equivalent power levels. TSMC offered four primary variants to address diverse applications: High Performance (HP) for speed-optimized designs like graphics processors; High Performance Mobile (HPM) for battery-efficient mobile devices supporting mixed transistor types; High Performance Low Leakage (HPL) balancing speed and power for FPGAs; and Low Power (LP) as a cost-effective shrink of the 40 nm LP process, ideal for low-standby applications such as cellular basebands. These variants featured a minimum contacted gate pitch of 120 nm and supported dense SRAM cells, with the HP variant achieving 0.16 µm² cell sizes—over five times smaller than those in 90 nm processes. Adoption of the 28 nm process accelerated rapidly due to surging demand from mobile and consumer electronics, with TSMC ramping to over 130,000 wafers per month by late 2011 and capturing more than 20% of its sales in that period. Major chipmakers like AMD, Qualcomm, Xilinx, and Altera utilized it for products including the Radeon HD 7970 GPU, Snapdragon S4 SoC, and Stratix V FPGA. Samsung followed with mass production in 2012, emphasizing a 28 nm RF process to enhance connectivity in wireless applications through advanced radio frequency functions and design kits. Despite later shifts to FinFET-based nodes below 20 nm, the 28 nm process remains relevant for cost-sensitive, mature-node applications, underscoring its role as a bridge in scaling Moore's Law.

Overview

Definition and Scale

The 28 nm process node refers to a semiconductor manufacturing technology characterized by a nominal feature size of 28 nanometers, primarily denoting the half-pitch of metal interconnect layers or the approximate drawn gate length, rather than a uniform physical scale across all device elements. This designation serves as a marketing and industry standard term for process generation, allowing for variations in actual dimensions among foundries while indicating overall scaling progress. Key dimensions in the 28 nm process include a minimum metal pitch of approximately 105 nm for lower interconnect layers (metal 1 to 4), a drawn gate length of 30 nm, and an effective gate length ranging from 26 nm in high-speed variants to 30 nm in low-leakage configurations. Production 28 nm processes employed planar transistors with high-k metal gate (HKMG) architecture. The contacted gate pitch scaled to 120 nm, enabling tighter packing compared to prior nodes. Implementations varied slightly by foundry, with TSMC, Samsung, and GlobalFoundries offering HKMG-based processes, while some used poly-SiGe gates. Introduced into production around 2010–2011 by leading foundries like TSMC, the 28 nm node marked a transitional shrink from the 40 nm process for TSMC (which bypassed 32 nm for logic), achieving approximately 1.8 times higher logic density through linear scaling factors of about 0.7x based on gate pitch reduction, amid emerging challenges to classical Dennard scaling where power density no longer decreased proportionally with transistor size. While generally positioned as a half-node between 32 nm and 22 nm, this shift highlighted the limitations of planar scaling, paving the way for non-planar transistor adoption in subsequent nodes below 22 nm to sustain performance gains.

Historical Context and Significance

The transition to the 28 nm process node was driven by escalating challenges encountered at the preceding 45 nm and 32 nm nodes, particularly in managing leakage currents and power density. At these earlier nodes, aggressive scaling of transistor dimensions led to exponentially increasing leakage power due to thinner gate oxides, which allowed greater electron tunneling and off-state currents, while higher clock speeds and functional integration exacerbated power density issues, straining thermal management and reliability. These problems were compounded by process variations and the limitations of traditional SiO2/poly-Si gate stacks, necessitating innovations to sustain performance gains without prohibitive power penalties. Positioned in the International Technology Roadmap for Semiconductors (ITRS) as a "half-node" intermediary between the 32 nm and 22 nm full nodes, the 28 nm process represented an incremental scaling step with a modest ~12-14% linear dimension reduction from 32 nm, enabling continued adherence to Moore's Law through equivalent scaling techniques rather than pure geometrical shrinks. This positioning allowed for a balanced advancement in density and performance, with transistor densities reaching up to approximately 29 million per mm² in high-performance variants, a significant leap that supported the proliferation of power-efficient chips for emerging applications like smartphones and data center servers. Moreover, 28 nm marked the widespread adoption of high-k metal gate (HKMG) technology as a standard, transitioning from experimental use at prior nodes to core implementation with hafnium-based dielectrics and metal work functions, which reduced gate leakage by orders of magnitude while maintaining drive currents. Economically, the 28 nm node marked the point where cost per transistor scaling stalled, with no significant reduction compared to prior generations like 40 nm, though improved densities and yield optimizations helped maintain economic viability; this came at the expense of sharply rising upfront costs for masks (approaching $1 million per set) and specialized tools like immersion lithography systems. This trade-off highlighted the node's role in bridging mature bulk CMOS scaling with more complex paradigms, ensuring economic viability amid slowing classical shrinks while fueling a surge in SoC adoption for consumer electronics.

Development History

Key Milestones and Research

The development of the 28 nm process was built on foundational research in the 2000s, including ongoing advancements in extreme ultraviolet (EUV) lithography prototypes—though EUV was not used in production at this node—and high-k metal gate (HKMG) materials. The 28 nm process primarily utilized 193 nm immersion lithography with double patterning techniques to achieve dense features. In the late 1990s and early 2000s, IBM contributed to EUV lithography through its participation in EUV LLC, a consortium that invested in resolving key challenges such as optics, masks, and light sources, leading to the delivery of the first prototype EUV engineering test stand by 2004. Concurrently, IBM led innovations in HKMG stacks throughout the 2000s, addressing issues like electron mobility reduction and thermal instabilities to enable their integration into CMOS devices for nodes at 45 nm and beyond, with significant progress demonstrated by 2007. These efforts involved collaborations with academic institutions, including work at Lawrence Berkeley National Laboratory on EUV imaging systems and tool integration during the same period. Key milestones in the late 2000s included prototype demonstrations by major players. TSMC achieved a breakthrough in 2009 by yielding functional 64 Mb SRAM cells across its three 28 nm process variants (high-performance, low-power, and ultra-low-power), validating the technology's viability for dense memory integration. Intel advanced parallel research, focusing on HKMG integration and tri-gate structures to mitigate scaling limits for sub-30 nm nodes, enhancing performance while controlling leakage. By 2011, the first tape-outs for 28 nm designs were completed, enabling early validation of customer circuits and marking a transition from lab prototypes to pre-production testing. Consortia like IMEC played a pivotal role in overcoming specific challenges, such as enhancing carrier mobility through strain engineering techniques, including selective epitaxial growth of stressors in source/drain regions to boost electron and hole transport in 28 nm MOSFETs. Research also addressed variability issues like random dopant fluctuation (RDF), a major hurdle at this scale due to discrete dopant atom distributions causing threshold voltage shifts; mitigation strategies, including optimized doping profiles and HKMG adoption, reduced RDF-induced variability by improving gate control and minimizing statistical fluctuations in device parameters. These advancements were critical for achieving reliable performance in sub-30 nm regimes. Notable dates include TSMC's 2010 announcement of piloting the 28 nm process, which confirmed readiness for risk production following successful prototyping, and Samsung's initiation of 28 nm low-power risk production in 2011, incorporating HKMG for mobile applications.

Introduction by Foundries

The 28 nm process node marked a pivotal advancement in semiconductor manufacturing, with Taiwan Semiconductor Manufacturing Company (TSMC) leading the commercial rollout as the first foundry to achieve high-volume production in 2011, initially targeting mobile system-on-chips (SoCs) using bulk complementary metal-oxide-semiconductor (CMOS) technology. This milestone enabled the fabrication of power-efficient, high-performance chips for consumer electronics, with TSMC's 28 nm high-performance (28HP) variant entering volume production ahead of competitors, surpassing prior nodes in ramp speed and yield maturity at equivalent stages. GlobalFoundries followed with its 28 nm production starting in 2012, focusing on planar transistor architectures to support low-power applications in mobile and Internet of Things (IoT) devices, exemplified by the 28 nm super low-power (28SLP) platform. Samsung, meanwhile, initiated 28 nm high-k metal gate (HKMG) process development in 2011, conducting early experiments that laid groundwork for subsequent non-planar innovations, though initial commercial emphasis remained on planar implementations for foundry services. These efforts by major foundries facilitated broader adoption, with initial yields for TSMC's 28 nm processes hovering around 70-80% in late 2011 amid yield challenges, ramping to over 80% by mid-2012 and approaching 90% by 2013 through process optimizations. Foundries adopted licensing models for intellectual property (IP) blocks to accelerate design integration, with companies like ARM and Synopsys providing optimized processor cores, memory compilers, and interface IP tailored to 28 nm nodes across TSMC, GlobalFoundries, and Samsung platforms. This ecosystem approach supported rapid market entry, highlighted by 2012 supply chain integrations such as Nvidia's Kepler GPU architecture on TSMC's 28 nm process, which boosted graphics performance in gaming and computing applications.

Technical Specifications

Lithography and Patterning Techniques

The 28 nm semiconductor process relies on 193 nm argon fluoride (ArF) immersion lithography as the foundational optical technique to define fine features, extended through multiple patterning to overcome resolution limits of single-exposure methods. This approach, often termed 193i, uses a water-immersion lens to increase numerical aperture to 1.35, enabling critical dimensions below the classical diffraction limit while maintaining compatibility with existing infrastructure. Multiple patterning, including double and triple schemes, is essential for layers such as metals and contacts, where pitch splitting divides patterns into multiple exposures to achieve effective resolutions not possible with immersion alone. For instance, self-aligned double patterning (SADP) is applied to contact layers, using sidewall spacers to self-align features and reduce variability in dense arrays. In poly gate patterning, double patterning with 193i lithography forms long continuous lines followed by line-end cut (LEC) processes to segment them into transistor gates, addressing limitations of optical proximity correction (OPC) at this scale, such as line-end rounding and tip-to-tip spacing errors. Resolution enhancement techniques, including off-axis illumination and sub-resolution assist features (SRAFs), optimize the illumination source shape and insert non-printing structures to improve image contrast and process windows for features around 28 nm. These methods enable metal layer pitches of approximately 90 nm (half-pitches of ~45 nm) via pitch doubling, supporting dense interconnects without requiring immediate transition to extreme ultraviolet (EUV) tools. Key challenges in these techniques include overlay errors between multiple exposures, which must be controlled to below 4 nm to prevent misalignment in multi-layer stacks, achieved through advanced metrology and scanner stabilization on immersion systems. While EUV lithography was under development for future nodes, the 28 nm process predominantly used 193i with multiple patterning for cost efficiency, as EUV infrastructure was not yet mature or economical at the time. SADP for contacts further mitigates overlay sensitivity by leveraging self-alignment, though it introduces additional etching steps that impact throughput. Overall, these patterning strategies balanced resolution gains with manufacturing viability, enabling high-volume production at foundries like TSMC and GlobalFoundries.

Transistor Architecture and Materials

The 28 nm process primarily employs planar bulk complementary metal-oxide-semiconductor (CMOS) transistors, marking a significant adoption of high-k metal gate (HKMG) technology across major foundries like TSMC and Samsung to enable continued scaling beyond the 32 nm node. GlobalFoundries employed a gate-first HKMG approach in their 28HP process variant. This architecture uses a gate-last process at TSMC, where initial polysilicon gates are replaced post-source/drain formation with dual metal gates tailored for n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), improving gate control and reducing leakage compared to prior poly-SiON stacks. While FinFET structures were explored in research for enhanced electrostatic control at sub-28 nm scales, production 28 nm nodes remained planar, with FinFETs not entering high-volume manufacturing until the 14-16 nm generations. Central to the HKMG implementation are hafnium oxide (HfO₂)-based high-k dielectrics, which offer a dielectric constant (k) of approximately 20-25, allowing for physical thicknesses that maintain capacitance while minimizing quantum tunneling leakage. These are paired with a thin silicon dioxide (SiO₂) interfacial layer, typically 1.2-2.0 nm thick, to passivate the silicon channel interface, achieving an equivalent oxide thickness (EOT) as low as 0.9 nm for superior gate coupling. Metal gates consist of titanium nitride (TiN) for pMOSFETs and titanium aluminum nitride (TiAlN) or similar for nMOSFETs, often capped with tungsten (W) for fill and work function tuning, enabling dual-threshold voltage options critical for balancing performance and power. Performance enhancements in 28 nm transistors incorporate strain engineering, particularly embedded silicon-germanium (SiGe) in pMOSFET source/drain regions to induce compressive strain, boosting hole mobility by up to 30% without altering the planar architecture. This SiGe integration, combined with channel orientation adjustments (e.g., <100> for high-performance low-leakage variants), addresses short-channel effects prevalent at this scale. To mitigate interconnect capacitance, which becomes pronounced at 28 nm densities, local interconnects utilize ultra-low-k dielectrics such as porous carbon-doped oxides (k ≤ 2.55), integrated via damascene processes with copper metallization and thin tantalum-based barriers for reliable gap-fill and electromigration resistance. These materials reduce RC delays, supporting the high-speed signaling required in logic and memory applications.

Design Considerations

Circuit Design Challenges

At the 28 nm process node, circuit designers faced heightened process variations compared to prior generations, primarily due to the adoption of high-k metal gate (HKMG) transistors and aggressive scaling, which amplified statistical fluctuations in key parameters such as threshold voltage (V_TH). Global V_TH variation was typically contained within 70 mV, a significant improvement over coarser nodes like 65 nm (up to 300 mV), but local mismatches still posed challenges for analog and mixed-signal circuits, necessitating robust statistical modeling in design flows. Interconnect scaling introduced substantial RC delay issues, as wires became thinner and longer, increasing resistance through enhanced electron scattering at sidewalls and grain boundaries while capacitance rose from denser routing. This shift elevated RC effects from a secondary concern to a primary limiter of performance, particularly in global interconnects, where delays could dominate over gate delays and contribute to signal integrity degradation, electromigration risks, and elevated power dissipation. To address these, designers relied on enhanced standard cell libraries incorporating HKMG-specific variability models, such as the Liberty Variation Format (LVF), which captured statistical sigma values for timing arcs, slews, and loads derived from Monte Carlo-like simulations. These libraries enabled variation-aware static timing analysis (STA), reducing over- or under-pessimism in signoff compared to earlier on-chip variation (OCV) methods. Design rule checks (DRC) were adapted for compatibility with advanced patterning techniques, including checks for decomposition-friendly layouts to support immersion lithography limits at 28 nm, where single patterning was predominant but required precise spacing to avoid defects in metal and contact layers. Timing models evolved to incorporate HKMG-induced variations, shifting from nominal characterizations to statistical approaches that accounted for process-voltage-temperature (PVT) corners, with later enhancements including skewness for non-Gaussian distributions to better predict tail-end behaviors in low-voltage regimes. Variability mitigation often involved adaptive voltage scaling techniques, where on-chip sensors monitored voltage droops and process corners in real-time, allowing dynamic adjustments to supply levels for balancing performance and reliability without excessive guard-banding. Foundries like TSMC provided 28 nm process design kits (PDKs) with updated electronic design automation (EDA) integrations from vendors such as Synopsys and Cadence, supporting LVF-based flows, advanced DRC decks, and variation-aware place-and-route to streamline implementation while minimizing yield impacts from variability.

Power and Performance Optimization

At the 28 nm process node, power and performance optimization became critical due to the scaling challenges that increased leakage currents and power density, necessitating advanced techniques to achieve efficient trade-offs between speed, power consumption, and area. Multi-threshold voltage (multi-Vt) transistors emerged as a cornerstone strategy, allowing designers to mix low-Vt devices for high-performance logic paths with high-Vt devices for low-power blocks like memory and always-on circuits, thereby reducing overall standby power by up to 30% without sacrificing critical path speeds. This approach leveraged the high-k metal gate (HKMG) stack, which enabled finer control over threshold voltages compared to planar bulk transistors at prior nodes. Dynamic voltage and frequency scaling (DVFS) was widely adopted to dynamically adjust supply voltage and clock frequency based on workload demands, enabling up to 40% power savings in mobile and server applications while maintaining performance under bursty loads. Complementary techniques included power gating, which shuts off power to inactive circuit blocks using sleep transistors to minimize leakage, and adaptive body biasing, which modulates transistor body voltage to fine-tune performance and suppress subthreshold leakage—achieving reductions of over 50% in static power relative to the 32 nm node through HKMG improvements. Clock tree synthesis optimizations further contributed by minimizing skew and jitter, allowing for 20-30% higher clock frequencies at iso-power compared to 32 nm designs. Performance metrics underscored these gains: NMOS drive currents reached up to 1.2 mA/μm at 0.9 V supply, supporting GHz-range operation, while HKMG integration reduced gate leakage by approximately 50% versus 32 nm poly-SiON processes, balancing the power-performance envelope for diverse applications from smartphones to high-performance computing. These optimizations collectively enabled 20-30% performance uplifts or 40% power reductions over preceding nodes, paving the way for energy-efficient scaling at 28 nm.

Manufacturing Process

Fabrication Steps

The fabrication of integrated circuits using the 28 nm process entails a highly intricate sequence of approximately 800–1000 individual steps, spanning roughly 40 days from initial wafer processing. Wafer preparation initiates the process, employing bulk silicon substrates. Following shallow trench isolation (STI) formation and well implantation, front-end-of-line (FEOL) processing centers on gate-last high-k metal gate (HKMG) integration to mitigate short-channel effects and enable scaling. Dummy polysilicon gates are first patterned to define active regions, allowing subsequent source/drain engineering before replacement with the final metal gate stack, which includes a hafnium-based high-k dielectric (such as HfSiON) over an interfacial silicon dioxide layer (1.2–2.0 nm thick) and work-function-tuned metals like TiN for PMOS and TiAlN for NMOS. Source and drain regions are recessed and filled via selective epitaxial growth, with embedded SiGe employed in PMOS transistors for certain high-performance variants (e.g., HP) to induce compressive strain and boost hole mobility by up to 25%. Dopants are then activated using rapid thermal annealing (RTA) to achieve ultra-shallow junctions while minimizing diffusion, often combined with laser annealing for optimized activation levels exceeding 80% in 28 nm nodes. Silicide contacts, typically NiPt alloys with 10% Pt additive, are formed on source, drain, and gate regions to reduce contact resistance, involving deposition, annealing at 500–600°C, and selective etching to suppress defects and improve leakage by 3–5%. Middle-of-line (MOL) processing follows, incorporating damascene techniques for tungsten-filled contacts and local copper interconnects to bridge FEOL devices, with chemical mechanical polishing (CMP) iterations ensuring planarity after each deposition and fill. Backend-of-line (BEOL) integration completes the structure with 10–12 layers of copper metallization embedded in extreme low-k (ELK) dielectrics (k < 2.5), fabricated via dual damascene patterning, electroplating, and multiple CMP steps for surface leveling; top layers often include thicker aluminum redistribution for packaging compatibility.

Yield and Cost Factors

The 28 nm process faced significant yield challenges during its initial ramp-up phase around 2011–2012, primarily due to high defect densities associated with multiple patterning techniques and the introduction of high-k metal gate (HKMG) structures. Target defect densities for mature production were aimed at 0.1–0.2 defects per cm² to achieve viable yields, but early efforts encountered systematic defects such as line-edge roughness and overlay errors from 193 nm immersion lithography. These issues were compounded by process-limited factors like particulate contamination and design-limited interactions, including parametric variations in transistor performance. Foundries like TSMC and GlobalFoundries reported initial yield struggles, with some designs failing to meet specifications, though progress was ahead of the 40/45 nm node's timeline at equivalent stages. Yield improvements were driven by advanced inline metrology tools for precise overlay control and defect monitoring, enabling faster identification and correction of systematic issues. Learning curves accelerated through iterative process tweaks and design-for-manufacturability (DFM) strategies, with TSMC achieving stable high-volume yields—exemplified by "fabulous" results for Nvidia's graphics chips—by mid-2012. By the mid-2010s, yield rates for 28 nm had matured significantly in optimized lines, supported by enhanced critical area analysis and parametric monitoring on test structures. These advancements reduced random defect impacts and improved overall process stability, particularly in poly-SiON and HKMG variants. Cost factors for 28 nm manufacturing were dominated by the high capital intensity of fabrication facilities, with individual fabs costing $4–5 billion for 45,000 wafer starts per month (wspm) capacity, often exceeding $10 billion when including expansions and R&D amortization. Wafer costs ranged from approximately $3,500 at 80% utilization to $5,000–7,000 in fully loaded scenarios, reflecting the added complexity of multiple patterning and HKMG over prior nodes, though scaling benefits partially offset these through higher die density. Economic viability required break-even volumes of 10,000–20,000 wafers per month to amortize fixed costs, with regional variations influencing profitability—TSMC's Taiwan operations benefited from lower labor and energy expenses compared to GlobalFoundries' U.S. facilities. Despite initial yield hurdles increasing per-wafer expenses, mature 28 nm production offered a cost-performance sweet spot, sustaining long-term adoption in high-volume applications.

Adoption and Applications

Major Foundries and Licensing

The 28 nm process node was predominantly manufactured by a handful of leading semiconductor foundries, with Taiwan Semiconductor Manufacturing Company (TSMC) emerging as the dominant player. TSMC offered multiple variants, including bulk silicon processes for cost-sensitive applications and high-k metal gate (HKMG) variants for enhanced performance and power efficiency. By 2015, TSMC held over 80% of the global 28 nm production capacity, underscoring its pivotal role in scaling this technology for widespread adoption. GlobalFoundries also played a significant role as a major foundry for 28 nm production, specializing in planar transistor architectures compatible with the node's standard requirements. Their 28 nm process supported a range of applications, leveraging established bulk CMOS technology to deliver reliable yields for customers transitioning from larger nodes. United Microelectronics Corporation (UMC) contributed to 28 nm production with bulk CMOS processes tailored for cost-sensitive, mature-node applications. Samsung Electronics, meanwhile, introduced a 28 nm planar HKMG process in mass production in 2012, emphasizing a 28 nm RF process to enhance connectivity in wireless applications through advanced radio frequency functions and design kits. Licensing for 28 nm processes involved extensive intellectual property (IP) ecosystems, with foundries providing process design kits (PDKs) through partnerships like those with Synopsys and ARM. TSMC's 28HPC variant targeted high-performance computing with optimized HKMG integration, while the 28LP focused on low-power mobile applications, both accessible via licensed PDKs that enabled foundry-agnostic design flows. Cross-licensing agreements, particularly for HKMG patents, facilitated collaboration among foundries and IP providers, mitigating legal hurdles and accelerating ecosystem development. These licensing models supported diverse implementations, including application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), fostering interoperability across the industry.

Commercial Devices and Products

The 28 nm process enabled a range of high-volume commercial devices, particularly in mobile computing and graphics. Apple's A7 system-on-chip (SoC), introduced in 2013 for the iPhone 5s, was fabricated using Samsung's 28 nm high-k metal gate (HKMG) process, marking Apple's shift to 64-bit ARM architecture while delivering improved power efficiency for smartphones. Similarly, Qualcomm's Snapdragon 800 series processors, launched in 2013, utilized TSMC's 28HPM (high-performance mobile) process to power premium Android smartphones and tablets with quad-core Krait CPUs clocked up to 2.3 GHz. Nvidia's Tegra 4 SoC, released in 2013, employed TSMC's 28 nm HPL (high-performance low-power) process for mobile devices, featuring a 72-core GPU and integrated LTE support to enhance graphics and connectivity in tablets and portable systems. In graphics and embedded applications, the node saw early adoption for discrete GPUs and programmable logic. AMD's Radeon HD 7970, unveiled in late 2011 and available in 2012, was the world's first consumer GPU built on a 28 nm process by TSMC, offering significant performance gains over prior generations through its Tahiti architecture. Xilinx's 7 series field-programmable gate arrays (FPGAs), introduced starting in 2010 with volume production ramping in 2012, leveraged 28 nm HKMG technology for embedded systems, enabling scalable designs in communications, industrial automation, and defense applications with unified architecture across families. Beyond consumer electronics, 28 nm found use in automotive and other sectors. Renesas Electronics developed 28 nm embedded flash MCUs in 2014 for automotive engine control units (ECUs), achieving higher on-chip memory capacities and supporting advanced driver assistance systems through low-power process variants. Production of 28 nm devices peaked between 2013 and 2016, driven by mobile demand, before major foundries transitioned volume manufacturing to 16 nm and 14 nm nodes by 2017 to pursue further scaling.

Comparisons and Legacy

Comparison to Adjacent Nodes

The 28 nm process node marked a transitional advancement over the preceding 32 nm node, achieving a transistor density of approximately 29 million transistors per square millimeter compared to 23 million at 32 nm, which enabled a 25-35% reduction in die area for equivalent functionality. Despite this scaling, power consumption remained similar to 32 nm levels primarily due to the adoption of high-k metal gate (HKMG) transistors, which mitigated leakage issues but limited aggressive voltage reductions. Additionally, lithography techniques shifted from single patterning at 32 nm to double patterning at 28 nm to maintain resolution amid the challenges of extreme ultraviolet (EUV) delays, improving pattern fidelity but increasing process complexity. In contrast to the subsequent 22 nm and 20 nm nodes, the 28 nm process offered economic advantages for low-power applications, with production costs roughly 50% lower than 22 nm due to its planar transistor architecture and established manufacturing infrastructure. However, 22 nm introduced FinFET (fin field-effect transistor) structures, delivering about a 20% performance boost at iso-power or equivalent power savings compared to 28 nm's planar HKMG devices, particularly in high-performance mobile and server chips. Power efficiency at 28 nm saw incremental improvements over 32 nm through optimized HKMG stacks, but it lagged behind 22 nm's 3D channel design, which reduced short-channel effects and enabled better electrostatic control. Overall, the 28 nm node served as a critical bridge technology, bridging the gap between planar bulk CMOS at larger nodes and the full adoption of 3D transistor architectures at 22 nm and beyond, allowing foundries to refine high-volume production while preparing for FinFET transitions.

Impact on Industry Evolution

The introduction of the 28 nm process in the early 2010s played a pivotal role in solidifying the dominance of the pure-play foundry model, particularly through Taiwan Semiconductor Manufacturing Company (TSMC), which increased its global foundry market share from 45.5% in 2010 to 55% by 2015. This node marked TSMC's ascension to process leadership, as it became the first foundry to achieve volume production of 28 nm wafers in 2011, outpacing integrated device manufacturers like Intel and Samsung in deployment speed. The success at 28 nm accelerated the shift toward specialized manufacturing services, enabling fabless companies to focus on design while foundries handled production, a business model that now commands over 90% of advanced logic capacity. The 28 nm process significantly fueled the mobile computing boom by enabling high-density, low-power system-on-chips (SoCs) essential for smartphones and tablets. Collaborations such as Qualcomm's with TSMC in 2010 targeted 28 nm for next-generation mobile processors, delivering up to twice the density of prior nodes and supporting the proliferation of dual-core and quad-core devices that drove smartphone shipments from 300 million units in 2010 to over 1.4 billion by 2015. This era's emphasis on power efficiency at 28 nm also laid groundwork for Internet of Things (IoT) precursors, with processes like GlobalFoundries' 28 nm-SLP optimized for connected sensors and wearables requiring extended battery life. Industry-wide, the 28 nm ramp-up influenced substantial fab investments, with global semiconductor equipment spending totaling approximately $206 billion from 2011 to 2015 to support capacity expansions amid tight supply. However, it also highlighted the end of straightforward Dennard scaling, as transistor cost reductions stalled at this node—rising thereafter due to challenges in lithography and materials—prompting a pivot toward heterogeneous integration for future performance gains. Legacy 28 nm libraries continue to influence designs at advanced nodes like 7 nm through scaled IP blocks, ensuring cost-effective reuse in mixed-signal and analog components.

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