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A dual-gate MOSFET and schematic symbol
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A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor (MIGFET). The most widely used multi-gate devices are the FinFET (fin field-effect transistor) and the GAAFET (gate-all-around field-effect transistor), which are non-planar transistors, or 3D transistors.

Multi-gate transistors are one of the several strategies being developed by MOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's law (in its narrow, specific version concerning density scaling, exclusive of its careless historical conflation with Dennard scaling).[1] Development efforts into multigate transistors have been reported by the Electrotechnical Laboratory, Toshiba, Grenoble INP, Hitachi, IBM, TSMC, UC Berkeley, Infineon Technologies, Intel, AMD, Samsung Electronics, KAIST, Freescale Semiconductor, and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies.[2] The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-κ/metal gate materials.

Dual-gate MOSFETs are commonly used in very high frequency (VHF) mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such as Motorola, NXP Semiconductors, and Hitachi.[3][4][5]

Types

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Several multigate models

Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and the number of channels/gates (2, 3, or 4).

Planar double-gate MOSFET (DGMOS)

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A planar double-gate MOSFET (DGMOS) employs conventional planar (layer-by-layer) manufacturing processes to create double-gate MOSFET (metal–oxide–semiconductor field-effect transistor) devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the drain–source channel is sandwiched between two independently fabricated gate/gate-oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.[6]

FlexFET

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FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa.[7] FlexFET was developed and is manufactured by American Semiconductor, Inc.

FinFET

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Main article: FinFET
A double-gate FinFET device
An SOI FinFET MOSFET
The NVIDIA GTX 1070 from 2016, which uses a 16 nm FinFET-based Pascal chip manufactured by TSMC

FinFET (fin field-effect transistor) is a type of non-planar transistor, or "3D" transistor (not to be confused with 3D microchips).[8] The FinFET is a variation on traditional MOSFETs distinguished by the presence of a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to make two points of contact: the left and right sides of the fin. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects.

The first FinFET transistor type was called a depleted lean-channel transistor or "DELTA" transistor, which was first fabricated by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[9][10][11] In the late 1990s, Digh Hisamoto began collaborating with an international team of researchers on further developing DELTA technology, including TSMC's Chenming Hu and a UC Berkeley research team including Tsu-Jae King Liu, Jeffrey Bokor, Xuejue Huang, Leland Chang, Nick Lindert, S. Ahmed, Cyrus Tabery, Yang-Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998, the team developed the first N-channel FinFETs and successfully fabricated devices down to a 17 nm process. The following year, they developed the first P-channel FinFETs.[12] They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper.[13]

In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET[14] development, whereas Intel avoids using the term when describing their closely related tri-gate architecture.[15] In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance.[16] The gate may also cover the entirety of the fin(s).

A 25 nm transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC (Taiwan Semiconductor Manufacturing Company). The "Omega FinFET" design is named after the similarity between the Greek letter omega (Ω) and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004, Samsung Electronics demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90 nm Bulk FinFET process.[12] In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on FinFET technology.[17][18] In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[19]

In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET has an unusual shape of a triangle rather than rectangle, and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area-to-volume ratio than a rectangular prism, thus increasing switching performance.[20]

In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014.[21] The next month, the rival company TSMC announced start early or "risk" production of 16 nm FinFETs in November 2013.[22]

In March 2014, TSMC announced that it is nearing implementation of several 16 nm FinFETs die-on wafers manufacturing processes:[23]

  • 16 nm FinFET (Q4 2014),
  • 16 nm FinFET+ (cca[clarify] Q4 2014),
  • 16 nm FinFET "Turbo" (estimated in 2015–2016).

AMD released GPUs using their Polaris chip architecture and made on 14 nm FinFET in June 2016.[24] The company has tried to produce a design to provide a "generational jump in power efficiency" while also offering stable frame rates for graphics, gaming, virtual reality, and multimedia applications.[25]

In March 2017, Samsung and eSilicon announced the tapeout for production of a 14 nm FinFET ASIC in a 2.5D package.[26][27]

Tri-gate transistor

[edit]

A tri-gate transistor, also known as a triple-gate transistor, is a type of MOSFET with a gate on three of its sides.[28] A triple-gate transistor was first demonstrated in 1987, by a Toshiba research team including K. Hieda, Fumio Horiguchi and H. Watanabe. They realized that the fully depleted (FD) body of a narrow bulk Si-based transistor helped improve switching due to a reduced body-bias effect.[29][30] In 1992, a triple-gate MOSFET was demonstrated by IBM researcher Hon-Sum Wong.[31]

Intel announced this technology in September 2002.[32] Intel announced "triple-gate transistors" which maximize "transistor switching performance and decreases power-wasting leakage". A year later, in September 2003, AMD announced that it was working on similar technology at the International Conference on Solid State Devices and Materials.[33][34] No further announcements of this technology were made until Intel's announcement in May 2011, although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009.[35]

On April 23, 2012, Intel released a new line of CPUs, termed Ivy Bridge, which feature tri-gate transistors.[36][37] Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass-production issues. The new style of transistor was described on May 4, 2011, in San Francisco.[38] It was announced that Intel's factories were expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs.[39] It was announced that the new transistors would also be used in Intel's Atom chips for low-powered devices.[38]

Tri-gate fabrication was used by Intel for the non-planar transistor architecture used in Ivy Bridge, Haswell and Skylake processors. These transistors employ a single gate stacked on top of two vertical gates (a single gate wrapped over three sides of the channel), allowing essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than previous transistors. This allows up to 37% higher speed or a power consumption at under 50% of the previous type of transistors used by Intel.[40][41]

Intel explains: "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)."[42] Intel has stated that all products after Sandy Bridge will be based upon this design.

The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels.[43]

Gate-all-around FET (GAAFET)

[edit]

Gate-all-around FETs (GAAFETs) are the successor to FinFETs, as they can work at sizes below 7 nm. They were used by IBM to demonstrate 5 nm process technology.

GAAFET, also known as a surrounding-gate transistor (SGT),[44][45] is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally.[46][47] They have also been successfully etched onto nanowires of InGaAs, which have a higher electron mobility than silicon.[48]

A gate-all-around (GAA) MOSFET was first demonstrated in 1988, by a Toshiba research team including Fujio Masuoka, Hiroshi Takato, and Kazumasa Sunouchi, who demonstrated a vertical nanowire GAAFET which they called a "surrounding gate transistor" (SGT).[49][50][45] Masuoka, best known as the inventor of flash memory, later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with Tohoku University.[51] In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology.[52][18] GAAFET transistors may make use of high-k/metal gate materials. GAAFETs with up to 7 nanosheets have been demonstrated which allow for improved performance and/or reduced device footprint. The widths of the nanosheets in GAAFETs is controllable which more easily allows for the adjustment of device characteristics.[53]

As of 2020, Samsung and Intel have announced plans to mass produce GAAFET transistors (specifically MBCFET transistors) while TSMC has announced that they will continue to use FinFETs in their 3 nm node,[54] despite TSMC developing GAAFET transistors.[55]

Multi-bridge channel (MBC) FET

[edit]

A multi-bridge channel FET (MBCFET) is similar to a GAAFET except for the use of nanosheets instead of nanowires.[56] MBCFET is a word mark (trademark) registered in the U.S. to Samsung Electronics.[57] Samsung plans on mass producing MBCFET transistors at the 3 nm node for its foundry customers.[58] Intel is also developing RibbonFET, a variation of MBCFET "nanoribbon" transistors.[59][60] Unlike FinFETs, both the width and the number of the sheets can be varied to adjust drive strength or the amount of current the transistor can drive at a given voltage. The sheets often vary from 8 to 50 nanometers in width. The width of the nanosheets is known as Weff, or effective width.[61][62]

Industry need

[edit]

Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from the undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device.[63]

In a multigate device, the channel is surrounded by several gates on multiple surfaces. Thus it provides better electrical control over the channel, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. Multigate transistors also provide a better analog performance due to a higher intrinsic gain and lower channel length modulation.[64] These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics.

Integration challenges

[edit]

The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include:

  • Fabrication of a thin silicon "fin" tens of nanometers wide
  • Fabrication of matched gates on multiple sides of the fin

Compact modeling

[edit]
Different FinFET structures, which can be modeled by BSIM-CMG

BSIMCMG106.0.0,[65] officially released on March 1, 2012 by UC Berkeley BSIM Group, is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A. Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with the 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD = 1).

All of the important multi-gate (MG) transistor behavior is captured by this model. Volume inversion is included in the solution of Poisson's equation, hence the subsequent I–V formulation automatically captures the volume-inversion effect. Analysis of electrostatic potential in the body of MG MOSFETs provided a model equation for short-channel effects (SCE). The extra electrostatic control from the end gates (top/bottom gates) (triple or quadruple-gate) is also captured in the short-channel model.

See also

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References

[edit]
[edit]
Revisions and contributorsEdit on WikipediaRead on Wikipedia

Multigate device

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from Grokipedia
A multigate device, also referred to as a multi-gate or multi-gate (MuGFET), is a architecture that integrates multiple gates around the channel to enhance electrostatic control in metal–oxide–semiconductor (). This design departs from traditional single-gate planar by surrounding the channel from multiple sides, typically two or more, to mitigate short-channel effects such as drain-induced barrier lowering and subthreshold leakage as device dimensions scale below 20 nm. Multigate devices emerged in the early as a solution to the limitations of planar transistors, enabling continued adherence to through improved scalability and performance in (CMOS) technology. Key variants include the (fin ), which features a three-dimensional fin-shaped channel with gates on three sides for tri-gate operation; the gate-all-around (GAA) structure, where the gate fully encircles a or nanosheet channel for superior control; and other forms like double-gate, Π-gate, and Ω-gate configurations built on silicon-on-insulator (SOI) substrates. These architectures offer significant advantages, including higher drive currents (up to 37% faster operation compared to planar devices at 22 nm), reduced power consumption (over 50% savings in field-programmable gate arrays), and minimized leakage currents, making them essential for , mobile devices, and advanced nodes in integrated circuits. Recent advancements have propelled multigate devices into production at sub-5 nm scales, with gate-all-around (GAA) transistor architectures adopted by major manufacturers for their 2 nm process nodes, including multi-bridge-channel FETs (MBCFETs) by for its SF2 process, nanosheet GAAFETs (in collaboration with IBM) by for N2, and RibbonFETs by for 18A, with production starting around 2025. These developments build on earlier adoptions, such as Samsung's MBCFETs for 3 nm processes since 2022, further enhancing electrostatic integrity while addressing fabrication challenges such as precise and high-k dielectric integration. Despite complexities in , including increased process steps and thermal management, these devices continue to drive innovations in energy-efficient electronics and hardware.

Principles and advantages

Basic operation

A multigate device is a variant of the () featuring two or more gates that surround the channel region, thereby enhancing electrostatic control over the channel potential compared to conventional single-gate . This structure allows for superior modulation of carrier flow in the channel by applying voltages to multiple gates simultaneously, which collectively influence the in the semiconductor body. In multigate devices, channel conduction occurs through a thin silicon body where the multiple gates modulate the potential distribution in three-dimensional space, contrasting with the primarily two-dimensional control in single-gate devices that limits gate influence to one surface. This 3D modulation enables more uniform field penetration into the channel volume, facilitating efficient inversion and transport of charge carriers from source to drain when the gate voltage exceeds the threshold. Short-channel effects, such as drain-induced barrier lowering and threshold voltage roll-off, are mitigated through volume inversion, where inversion charge carriers distribute throughout the channel volume rather than confining to the gate oxide interface, thereby strengthening gate dominance over the channel potential and reducing subthreshold leakage. The basic current-voltage (I-V) characteristics of multigate devices exhibit enhanced performance, particularly in the subthreshold region, where the subthreshold swing ideally approaches the of 60 mV/decade at due to improved electrostatic integrity and minimal short-channel perturbations. In the above-threshold regime, the drive current benefits from higher effective channel width without increasing the device footprint, leading to steeper I-V curves and better on-off ratios. For conceptual illustration, a double-gate configuration typically depicts a planar or fin-shaped channel film sandwiched between two parallel gates separated by thin gate oxides, enabling symmetric control from opposite sides; in contrast, a surround-gate (or gate-all-around) setup shows a cylindrical or channel fully enveloped by a conformal gate electrode on all sides, maximizing for the strongest short-channel effect suppression.

Performance benefits

Multigate devices provide superior electrostatic control over the channel compared to traditional single-gate MOSFETs, primarily by surrounding the channel with multiple , which effectively reduces off-state leakage current. This enhanced control suppresses subthreshold leakage paths, enabling significantly lower power consumption while maintaining performance. For instance, in simulations of 22 nm devices, double-gate MOSFETs exhibit an off-state current (Ioff) of 1.03 × 10^{-10} A/μm, over an lower than the 1.976 × 10^{-9} A/μm observed in conventional single-gate NMOS devices under similar conditions. The multi-gate configuration increases the effective channel width and improves carrier transport, leading to enhanced on-state drive current () and (gm). By distributing the control around the channel, source/drain series resistance is reduced, boosting overall current drive without increasing the device footprint. Representative simulations show values of 1.312 × 10^{-4} A/μm in double-gate structures, comparable to or exceeding single-gate devices while offering better efficiency. This results in higher , with multigate devices demonstrating up to 20-30% improvement over planar MOSFETs at equivalent leakage levels due to minimized and improved mobility. Multigate devices excel in mitigating short-channel effects (SCEs), including drain-induced barrier lowering (DIBL) and (Vth) roll-off, through volumetric gate control that confines the more effectively. DIBL, which degrades off-state performance in single-gate devices, is substantially reduced; for example, double-gate MOSFETs achieve a DIBL of 0.0422 V at 22 nm gate length, compared to 0.166 V in single-gate NMOS. Similarly, Vth roll-off is minimized, preserving device stability as dimensions shrink. The subthreshold swing (SS), a key indicator of switching , approaches the theoretical Boltzmann limit of 60 mV/dec more closely in multigate devices, with values around 70-80 mV/dec versus 90-140 mV/dec in single-gate counterparts for short channels. Electrostatic is quantified by a lower natural scaling length (λ), often 20-50% smaller in double-gate versus single-gate structures, enhancing SCE immunity. These improvements translate to superior on/off current ratios (/Ioff), a critical metric for low-power, high-speed applications. Multigate devices typically achieve ratios exceeding 10^6-10^7, far surpassing the 10^4-10^5 common in single-gate MOSFETs at sub-20 nm scales. The following table summarizes representative performance metrics from TCAD simulations of 22 nm n-channel devices with low channel doping (1 × 10^{15} cm^{-3}) and 1.1 nm oxide thickness:
ParameterSingle-Gate NMOSDouble-Gate
Subthreshold Swing (mV/dec)139.4127.2
DIBL (V)0.1660.0422
(A/μm)1.6 × 10^{-4}1.312 × 10^{-4}
Ioff (A/μm)1.976 × 10^{-9}1.03 × 10^{-10}
Ion/Ioff Ratio~8.1 × 10^4~1.3 × 10^6
Data adapted from Sentaurus TCAD simulations. For scaling below 10 nm nodes, multigate architectures enable higher transistor density and faster switching speeds by sustaining strong gate control amid aggressive dimension reduction. Structures like tri-gate FinFETs and gate-all-around FETs maintain low SCEs down to 5 nm gate lengths, supporting ITRS roadmap requirements for sub-10 nm performance with Ion/Ioff ratios above 10^7 and SS near 70 mV/dec, while single-gate devices suffer excessive leakage and degraded speed. Gate-all-around (GAA) transistors, a advanced multigate design, provide multi-directional gate control around the charge channel, offering superior advantages over previous designs such as FinFETs by improving speed, efficiency, and power consumption through enhanced electrostatic control and reduced leakage. This structure enables stacked designs like complementary FET (CFET) and integration with 2D materials such as MoS2, utilizing advanced gate stacks to achieve better performance in classical computing applications. This scalability positions multigate devices as essential for continued advancement in high-density, energy-efficient computing.

Historical development

Early concepts

The concept of multigate devices emerged in the late as researchers sought to improve gate control over the channel in to mitigate short-channel effects during scaling. In 1980, Toshihiro Sekigawa proposed a planar double-gate structure in a , envisioning two gates on opposite sides of a thin film to enhance electrostatic control without relying on a bulk substrate. This idea built on earlier concepts but focused on silicon-on-insulator (SOI) compatibility for better isolation and reduced . Theoretical foundations were further developed in the mid-1980s, with a seminal publication introducing the double-gate SOI MOSFET, characterized by its cross-shaped channel resembling an "X" under dual gates for improved volume inversion. The landmark paper by Francis Balestra and colleagues demonstrated through simulations and analysis that double-gate SOI transistors could achieve volume inversion, leading to significantly enhanced (up to 2.4 times higher) and reduced variability compared to single-gate devices, while suppressing short-channel effects in films thinner than 20 nm. These works highlighted the potential for multigate structures to maintain ideal subthreshold slopes near 60 mV/decade, a key advantage over conventional . Early patents and papers in the late also explored vertical and surround-gate configurations to enable better scaling. In 1988, a team led by Hiroshi Takato, Kazumasa Sunouchi, and Fujio Masuoka demonstrated the first gate-all-around (GAA) , termed the surrounding-gate (SGT), with a vertical cylindrical channel fully enveloped by the gate, achieving gate lengths as short as 0.1 μm and demonstrating superior immunity. The following year, , saw the experimental fabrication of the DELTA (fully DEpleted Lean-channel TrAnsistor) by Digh Hisamoto and colleagues at , a vertical double-gate SOI device with a fin-like silicon island standing on its edge, serving as an early prototype that operated with effective channel control in sub-100 nm regimes. Experimental demonstrations accelerated in the , with researchers achieving a milestone in 1997 through the fabrication of a self-aligned top-and-bottom double-gate SOI MOSFET featuring a 25 nm thick silicon channel. This prototype, developed by Hon-Sum Philip Wong and team, utilized and chemical-mechanical polishing to align gates precisely, yielding devices with gate lengths down to 50 nm, near-ideal subthreshold slopes of 65 mV/decade, and drive currents 20% higher than equivalent single-gate SOI transistors. Early research identified significant fabrication challenges, particularly precise gate alignment in planar double-gate structures, where misalignment could lead to asymmetric operation, increased off-state leakage, and degraded short-channel control. Vertical and surround-gate designs partially addressed this by inherent symmetry but introduced complexities in uniform channels and depositing conformal gate dielectrics. These hurdles limited initial implementations to research prototypes pre-2000, paving the way for 3D architectures like fin-based concepts that transitioned from planar double-gate ideas toward more scalable geometries.

Key advancements

The development of multigate devices accelerated in the early 2000s with the introduction of the FinFET architecture, pioneered by researchers at the under Chenming Hu, who demonstrated the first functional FinFET devices in 2000, enabling superior gate control over the channel compared to planar transistors. IBM followed with experimental demonstrations of FinFETs integrated into CMOS circuits around 2002, validating their scalability for sub-50 nm nodes through improved short-channel effects suppression. These efforts laid the groundwork for industry adoption, shifting from theoretical multi-gate concepts to practical implementations that addressed leakage and performance limits in scaling beyond 90 nm. Intel marked a pivotal commercial milestone in 2011 by adopting tri-gate transistors— an evolution of FinFETs— in its node for the Ivy Bridge , achieving up to 37% higher performance or 50% lower power than the prior 32 nm planar technology. By 2014, transitioned to second-generation FinFETs in its , incorporating optimized fin dimensions and high-k metal gates, which delivered 1.4x density and sustained drive currents for Broadwell processors. This adoption propelled multigate devices into high-volume production, influencing competitors like and to follow suit at similar nodes. Advancements in gate-all-around (GAA) architectures emerged as the next frontier, with announcing its multi-bridge-channel FET (MBCFET), a nanosheet-based GAA variant, in 2019 for the 3 nm node, promising 30% higher performance and 50% lower power than 5 nm FinFETs. initiated production of 3 nm GAA chips in 2022, utilizing stacked nanosheets for enhanced electrostatic control and enabling denser logic integration. revealed its RibbonFET, another nanosheet GAA implementation, in 2021 for the Intel 20A node (equivalent to ~2 nm), but later shelved 20A in favor of the 18A node, targeting volume production of 18A in 2025 with backside power delivery (PowerVia) for reduced resistance and improved scaling. In 2024-2025, innovations extended multigate concepts to novel materials and structures, including 2D multi-fin FETs using oxyselenide (Bi₂O₂Se) fins integrated via ledge-guided , which achieved high on/off ratios exceeding 10⁸ and drive currents over 500 μA/μm for ultra-scaled logic applications below 1 nm effective channel length. For power electronics, GaN-based GAAFETs advanced with high-k wrapped dielectrics, demonstrating cutoff frequencies above 1 THz and gains of 163% over conventional designs, suited for high-voltage RF and efficient switching in electric vehicles. Node scaling milestones underscore the evolution: tri-gate at 22 nm enabled 2x density over 32 nm, FinFET refinements at 14 nm and 7 nm pushed gate lengths below 20 nm with , while 5 nm marked the FinFET limit before GAA at 3 nm and sub-2 nm projections, forecasting continued density doubling through stacked nanosheets and complementary FETs by 2025. These advancements have driven multigate adoption across logic and memory, briefly referencing performance benefits like reduced variability for reliable circuit operation.

Device architectures

Double-gate MOSFETs

The planar double-gate (DGMOS) consists of a thin body sandwiched between two opposing gates, each separated by a layer, enabling superior electrostatic control over the channel potential from both sides compared to conventional single-gate structures. This configuration suppresses short-channel effects by confining the channel depletion regions and reducing leakage currents, making it suitable for nanoscale applications. Double-gate MOSFETs operate in two primary modes depending on gate connectivity. In the tied-gate mode, both gates are electrically connected and driven by the same voltage, providing symmetric control and effectively doubling the for enhanced drive current. Conversely, in the independent-gate mode, the gates are biased separately, allowing for multiple-independent-gate (MIGFET) operation where one gate can modulate the channel while the other adjusts performance parameters like . For symmetric structures, the threshold condition in both modes is governed by the gate voltage, expressed as: Vth=Vg1+Vg22V_{th} = \frac{V_{g1} + V_{g2}}{2} where VthV_{th} is the effective threshold voltage, and Vg1V_{g1}, Vg2V_{g2} are the voltages on the front and back gates, respectively; this simplifies to Vth=VgV_{th} = V_g when gates are tied (Vg1=Vg2=VgV_{g1} = V_{g2} = V_g). A notable variant is the FlexFET, an SOI-based planar independent double-gate MOSFET that employs back-gate bias to achieve flexible dynamic threshold voltage tuning, enabling reconfigurability for low-power and high-performance circuits without altering the front-gate drive. The simplicity of planar double-gate designs facilitated early scaling demonstrations, with prototypes in the 1990s and 2000s—such as those exploring ultrathin-body SOI integration—showcasing reduced subthreshold leakage and improved on-current densities for gate lengths down to 50 nm. However, these structures exhibit poor electrostatic control at the channel edges due to fringing fields and parasitic capacitances, limiting further width scaling and motivating the evolution toward three-dimensional architectures.

FinFETs

FinFETs feature a vertical silicon "fin" that serves as the channel, with the gate electrode wrapping around three sides of the fin in a tri-gate configuration, enabling superior electrostatic control over the channel compared to traditional planar MOSFETs. This 3D architecture, first conceptualized as a double-gate structure but evolved into tri-gate for enhanced performance, allows for effective scaling below 20 nm gate lengths by suppressing short-channel effects through improved gate-to-channel coupling. The tri-gate design specifically provides better control over the fin corners, mitigating leakage and variability issues that are more pronounced in double-gate fins. Key structural parameters of FinFETs include fin width (W_fin), fin height (H_fin), and fin pitch, which directly influence drive current, , and . The effective channel width (W_eff) in a tri-gate FinFET is calculated as W_eff = 2 H_fin + W_fin for a single fin, allowing designers to tune performance by adjusting these dimensions while maintaining aspect ratios suitable for fabrication. For instance, narrower fins (typically 5-10 nm) enhance gate control but require precise to avoid variability, while taller fins increase W_eff and current drive at the cost of higher parasitics. In logic applications, tri-gate FinFETs have been pivotal for , with widespread adoption in advanced nodes such as Intel's 14 nm, 10 nm, and 7 nm processes, TSMC's 16 nm and 7 nm technologies, and Samsung's 14 nm and 7 nm nodes, delivering up to 40-50% performance gains or power reductions over prior planar devices. These implementations leverage the tri-gate's ability to operate at lower voltages with reduced leakage, enabling denser integration in microprocessors and SoCs. Variations in FinFET design include single-, double-, and multi-fin configurations, where multiple parallel fins are used to scale drive current proportionally with the number of fins (n), as W_eff ≈ n (2 H_fin + W_fin), without significantly increasing the . Double-fin designs offer a balance for moderate current needs, while multi-fin setups (e.g., 3-4 fins) are employed in high-drive logic gates to boost on-state current by up to 2-4 times compared to single-fin devices. Despite these advantages, FinFETs face challenges from fin width variability, stemming from and non-uniformities, which can cause shifts of 50-100 mV and impact circuit yield in sub-10 nm nodes. Additionally, —particularly outer and inner fringing components—increases with fin height and pitch, potentially degrading switching speeds by 10-20% in high-frequency applications unless mitigated through optimized spacer dielectrics.

Gate-all-around FETs

Gate-all-around field-effect transistors (GAAFETs) enclose the channel on all four sides with the gate electrode, providing multi-directional gate control around the charge channel for enhanced electrostatic control, reduced short-channel effects, improved speed, efficiency, and lower power consumption compared to previous designs like FinFETs in nanoscale devices. This structure typically employs silicon nanowires or nanosheets as the channel material, where the gate dielectric and metal fully surround the channel to maximize gate-to-channel coupling. In nanowire GAAFETs, the cylindrical geometry leads to a specific expression for the gate capacitance, which is essential for understanding device performance and scaling. The gate capacitance CgC_g for a cylindrical nanowire is given by Cg=2πϵLln⁡(1+toxrch),C_g = \frac{2\pi \epsilon L}{\ln\left(1 + \frac{t_{\mathrm{ox}}}{r_{\mathrm{ch}}}\right)}, where ϵ\epsilon is the permittivity of the gate dielectric, LL is the gate length, toxt_{\mathrm{ox}} is the gate oxide thickness, and rchr_{\mathrm{ch}} is the channel radius. This formula highlights the logarithmic dependence on the oxide-to-channel radius ratio, allowing for precise modeling of capacitance in sub-5 nm regimes. Nanosheet FETs (NSFETs), a variant of GAAFETs, utilize multiple horizontal nanosheets stacked vertically as the channel, with the wrapping around each sheet individually. This stacked configuration increases the effective channel width, thereby boosting drive current while maintaining excellent gate control and suppressing leakage. For instance, NSFETs can achieve higher on-state currents per unit footprint compared to single-wire structures due to the parallel conduction paths provided by the sheets. The vertical stacking capability of GAAFETs enables advanced architectures like complementary field-effect transistors (CFETs), where n-type and p-type GAAFETs are stacked to deliver up to 30-50% area reduction and enhanced performance in classical computing applications. Samsung's multi-bridge-channel FET (MBCFET) implements GAAFET technology at the 3 nm node using multiple parallel horizontal nanosheets as bridges, enabling tunable channel widths for optimized performance in logic and applications. This allows for varied numbers of nanosheets in pull-up, pull-down, and pass-gate transistors, enhancing SRAM density and power efficiency. MBCFET production began in 2022, demonstrating up to 23% performance improvement and 45% power reduction over 5 nm FinFETs. This architecture is further evolved for Samsung's 2 nm SF2 process node, with risk production targeted for late 2025 and high-volume manufacturing in 2026. Intel's RibbonFET represents another GAAFET evolution, featuring wider ribbon-like channels instead of narrow nanowires or sheets to support higher drive currents at 2 nm-class nodes like Intel 18A. Introduced for production in 2025, RibbonFET provides improved electrostatics and scalability for , integrated with backside power delivery for reduced resistance. TSMC's N2 process employs nanosheet GAAFETs, building on pioneering research by IBM, as a successor to FinFETs, entering in the second half of 2025. This architecture offers enhanced drive current, lower leakage, and up to 15% area reduction compared to the prior 3 nm FinFET node, with strong adoption in mobile and applications. Recent advancements in 2024 and 2025 have focused on integrating two-dimensional (2D) materials, such as transition metal dichalcogenide (TMDC) nanosheets like MoS₂, into GAAFETs to overcome silicon's mobility limits at sub-3 nm scales. These 2D GAA structures, employing advanced gate stacks, exhibit on/off ratios exceeding 10⁸ and on-state currents over 400 μA/μm, with gate-first processes enabling scaling to 50 nm channels for future complementary FETs and better performance in classical computing. Additionally, GaN-based GAAFETs have emerged for RF and power applications, leveraging GaN's wide bandgap for high-frequency operation and efficiency, with designs incorporating high-k spacers achieving cutoff frequencies over 100 GHz and suitability for low-power RF circuitry.

Fabrication techniques

Structural formation

The structural formation of multigate devices involves precise patterning and etching processes to create three-dimensional channel geometries that enable multiple gates to surround the channel, enhancing electrostatic control. For FinFETs, which represent an early multigate architecture, fin formation begins with to define narrow fins on a bulk or silicon-on-insulator substrate. Advanced techniques such as () lithography are employed for sub-10 nm features, allowing high-resolution patterning of fin widths typically below 10 nm. Sidewall image transfer (SIT) is a key method to achieve dense, uniform fins by using sacrificial spacers to double the pattern density from a coarser lithographic mask, followed by selective etching to transfer the pattern into the silicon. , often via () with plasmas like O₂ or Cl₂-based chemistries, shapes the fins to high aspect ratios (up to 10:1 or more), ensuring vertical sidewalls while minimizing damage to the channel surface. In gate-all-around (GAA) FETs, such as nanosheet or nanowire variants, structural formation emphasizes vertical stacking of channel layers to maximize gate wrapping. Nanosheet stacking starts with epitaxial growth of alternating silicon (Si) and silicon-germanium (SiGe) layers on a substrate, where SiGe serves as sacrificial material due to its higher etch selectivity. This superlattice is formed via chemical vapor deposition (CVD) at temperatures around 600–700°C, achieving layer thicknesses of 5–10 nm for channels and 10–20 nm for sacrificial layers, enabling stacked heights of 50–100 nm for multi-channel devices. Channel release in GAA structures occurs after dummy gate removal, involving selective wet etching of the SiGe sacrificial layers using solutions like HCl or NH₄OH, which exploit the Ge content (typically 20–50%) for etch rates differing by over 100:1 compared to Si. Inner spacers are formed prior to channel release by laterally etching the sacrificial layers under the gate sidewall and filling the voids with a low-k dielectric via atomic layer deposition (ALD), preventing parasitic capacitance between channel and source/drain regions. Gate stack deposition in multigate devices universally adopts high-k/metal gate (HKMG) processes to replace conventional polysilicon gates, integrated via the replacement metal gate (RMG) flow. After fin or nanosheet patterning and source/drain , a dummy polysilicon gate is removed, exposing the channel for conformal deposition of high-k dielectrics (e.g., HfO₂, 1–2 nm equivalent oxide thickness) using ALD for uniform coverage on three or four sides. Metal work-function layers (e.g., TiN or TaN) and fill metals (e.g., W or Al) follow via (PVD) or ALD, ensuring low variability in 3D geometries. This RMG approach, critical for sub-10 nm nodes, avoids thermal budget issues from early high-k integration and supports gate lengths down to 20 nm. Key tools enabling these formations include EUV for patterning fins or stack templates with critical dimensions below 7 nm, offering resolutions unattainable by deep ultraviolet (DUV) alone, and ALD for precise, conformal deposition of dielectrics and metals with angstrom-level control. tools, such as (ICP) reactors, provide anisotropic profiles essential for high-aspect-ratio structures. Process flows for double-gate MOSFETs and GAA FETs diverge after initial substrate preparation but share RMG integration. In double-gate flows, typically on SOI, fins are patterned and etched similarly to FinFETs, followed by gate oxidation or deposition on top and bottom surfaces, with source/drain formation via implantation or . GAA flows extend this by adding epitaxial growth post-fin etch, inner spacer insertion, and multi-step selective etches for channel release, culminating in wider gate wrapping but requiring more complex for stack alignment. These differences allow GAA to achieve superior short-channel control at scaled nodes while inheriting FinFET-compatible early steps.

Material and process innovations

The integration of high-k dielectrics such as HfO₂ and ZrO₂ into multigate devices has significantly reduced gate leakage currents while maintaining (EOT) below 0.5 nm, enabling better electrostatic control in FinFETs and gate-all-around (GAA) structures. These materials replace traditional SiO₂, mitigating quantum tunneling effects in scaled channels and improving subthreshold swing in double-gate FinFETs. Channel materials in multigate devices have evolved from bulk to silicon-on-insulator (SOI) substrates for reduced , followed by strained SiGe nanowires to enhance hole mobility in p-type channels. In 2023 prototypes, two-dimensional dichalcogenides (TMDCs) like MoS₂, WS₂, and WSe₂ have been incorporated as channel materials in wafer-scale transistors, with mobilities around 7–30 cm²/V·s for low-power applications. Contact innovations, including raised source/drain regions formed via epitaxial growth of SiGe or followed by nickel silicide formation, have lowered specific contact resistivity to around 10⁻⁹ Ω·cm² in advanced FinFETs, minimizing series resistance. Recent fabrication processes leverage bottom-up vapor-liquid-solid (VLS) growth for precise nanowire alignment in multigate structures, achieving diameters as small as 10 nm with uniformity over large areas. Complementary FET (CFET) designs incorporate 3D stacking of n- and p-channel nanowires, reducing footprint while maintaining thermal budgets below 700°C. In 2025, hybrid III-V materials like GaN in GAA configurations have advanced RF and high-frequency applications. EUV-assisted patterning has enabled sub-20 nm pitch resolution for these stacked architectures, supporting single-exposure fabrication of complex multigate layouts. As of 2025, high-NA EUV has enabled sub-20 nm pitch resolutions for stacked GAA architectures. choices, particularly high-k dielectrics and TMDC channels, have improved fabrication yields by 25–40% through reduced defect densities and enhanced interface quality, as evidenced by reductions below 50 mV in 2D-based prototypes.

Integration and challenges

Circuit integration

In circuit integration, multigate devices such as FinFETs and gate-all-around (GAA) FETs require careful layout considerations to optimize performance and area efficiency. Fin pitch scaling enables higher drive current per unit footprint by allowing denser fin placement, though it introduces trade-offs like increased fringing between the gate and contacts. To achieve desired drive strength, multiple fins are connected in parallel within a , providing quantized width increments that enhance current capability while maintaining layout regularity. Interconnect integration poses significant challenges due to the dense three-dimensional structures of multigate devices, which complicate local and increase parasitic effects. As cell sizes scale, the number of connection pins remains high, demanding innovative local interconnect layers to manage and minimize resistance in the back-end-of-line (BEOL) stack. These 3D architectures exacerbate congestion, necessitating advanced rules for via placement and metal layer stacking to avoid delays from elevated and . The adoption of multigate devices has driven redesigns in SRAM and logic cells, particularly for nodes at 7 nm and beyond, enabling reduced cell heights through tighter or nanosheet pitches. In FinFET-based designs at 7 nm, heights are optimized to around 240-270 nm, facilitating up to 30% area savings compared to planar equivalents by aligning rows with consistent spacing. For GAA FETs, further height reductions to approximately 120 nm at sub-3 nm nodes support buried power rails, enhancing while preserving track utilization in place-and-route flows. Power delivery in multigate circuits benefits from dynamic voltage and (DVFS) compatibility, allowing workload-adaptive voltage adjustments to balance performance and consumption without compromising the devices' superior electrostatic control. Additionally, multi-threshold voltage (multi-Vt) options are implemented using independent gates in FinFETs, where separate front and back gate biases tune Vt dynamically, reducing leakage by up to 50% in logic paths while supporting granular power optimization. Practical examples illustrate these integration strategies. TSMC's 5 nm FinFET includes certified standard cell libraries with multi-Vt variants, enabling high-density designs for mobile and HPC applications through optimized fin parallelism and interconnect schemes. Samsung's 3 nm GAA standard cells, introduced in production from 2022, leverage nanosheet stacking for flexible SRAM layouts, achieving 16% area reduction over equivalent 5 nm FinFET cells via enhanced channel control and reduced cell heights. These advancements yield substantial density improvements, with TSMC's 5 nm FinFET nodes reaching approximately 171 million transistors per mm² through scaled layouts and efficient routing. Samsung's initial 3 nm GAA process (3GAE) achieves approximately 150 million transistors per mm², representing an 18% density gain over its 5 nm baseline, driven by GAA's superior scaling in logic and cells.

Scalability and reliability issues

In FinFETs, edge effects at the fin tips introduce variability in fin height and width, leading to threshold voltage (Vt) mismatch across devices due to uneven gate control and increased scattering. This variability exacerbates device-to-device inconsistencies, particularly in high-density circuits where precise Vt matching is essential for performance uniformity. Transitioning to gate-all-around (GAA) FETs, nanosheet structures face significant fabrication challenges during the release process, where selective of sacrificial layers can induce bending in the suspended nanosheets due to imbalances. This bending distorts channel dimensions, degrading electrostatic control and contributing to performance fluctuations. Additionally, inner spacer defects arise from incomplete or void formation at the source/drain interfaces, which compromise isolation and increase parasitic capacitances, thereby hindering scalability. Reliability in multigate devices is further compromised by bias temperature instability (BTI), which causes shifts under prolonged bias and elevated temperatures, particularly in high-k stacks where trap generation at the interface accelerates degradation. Hot carrier injection (HCI) exacerbates this by injecting high-energy carriers into the gate , leading to interface state creation and reduced drive current over time, with effects more pronounced in scaled high-k/metal gate configurations. These mechanisms limit long-term operational stability in dense multigate arrays. In complementary FETs (CFETs), integration issues manifest as severe self-heating due to confined paths in vertically n- and p-channel structures, resulting in localized temperature rises that amplify leakage and aging rates. Parasitic between gates and channels introduces unintended , increasing power consumption and signal in high-density layouts. These and electrical interactions pose barriers to further vertical scaling. As multigate devices approach sub-2 nm nodes in 2024-2025, quantum tunneling emerges as a critical hurdle, enabling band-to-band leakage that erodes subthreshold swing and off-state current control in GAA structures. As of late 2025, TSMC's N2 and Samsung's SF2 2 nm processes have entered , though challenges like yield optimization and quantum effects persist. In devices incorporating 2D materials like dichalcogenides, interface traps at the channel-dielectric boundary trap charge carriers, causing , mobility degradation, and instability under bias. These quantum and interfacial effects challenge the feasibility of continued aggressive scaling. To address these scalability and reliability hurdles, strain engineering applies tensile or to channels via epitaxial stressors or process-induced relaxation, enhancing carrier mobility and mitigating Vt variability while reducing defect densities in multigate architectures. Redundancy designs, such as in critical paths or error-correcting layouts in cells, provide against variability and aging-induced failures, ensuring robust operation in advanced multigate systems.

Modeling and applications

Compact modeling

Compact modeling of multigate devices involves developing mathematical frameworks that accurately capture their electrical characteristics for efficient circuit simulation in tools like , enabling designers to predict device without full-scale numerical simulations. These models must account for the unique of multigate structures, such as multiple interfaces and three-dimensional charge distributions, while maintaining computational efficiency for large-scale integrated circuits. Surface-potential-based approaches are prevalent, as they provide a physically grounded description of carrier transport from subthreshold to strong inversion regimes. The BSIM-MG (Berkeley Short-channel IGFET Model for Multi-Gate) and its successor BSIM-CMG (Common Multi-Gate) are industry-standard compact models adapted for multigate MOSFETs, including double-gate, tri-gate, and gate-all-around (GAA) configurations fabricated on SOI or bulk substrates. These models incorporate multi-gate formulations that treat the effective channel width as a function of fin height and number of gates, enhancing accuracy for short-channel effects like drain-induced barrier lowering. Mobility models in BSIM-CMG account for surface scattering and volume inversion in thin s, using empirical parameters calibrated to measured data to predict degradation due to interface traps. Similarly, the PSP (Princeton Surface Potential) model has been extended for symmetric FinFETs with thin, undoped bodies, featuring analytical expressions for charge density and current that scale with fin dimensions, ensuring continuity across operating regions. For GAA FETs, surface potential-based approaches solve the three-dimensional Poisson equation to model the electrostatics around the cylindrical or nanosheet channel, capturing radial potential variations that planar models overlook. The Poisson equation in cylindrical coordinates is discretized analytically, yielding the surface potential ϕs\phi_s as a function of gate voltage, channel radius, and doping, which serves as the core for deriving currents and capacitances. This method enables accurate prediction of volume inversion in ultra-narrow channels, where carriers distribute uniformly across the cross-section. Key equations in these models include the for FinFETs, which varies with fin (height-to-width) due to corner effects and depletion width variations. The subthreshold current is modeled exponentially as Isub∝μCoxWeffLexp⁡(q(Vgs−Vth)nkT)I_{sub} \propto \mu C_{ox} \frac{W_{eff}}{L} \exp\left(\frac{q(V_{gs} - V_{th})}{n k T}\right), incorporating effective width WeffW_{eff} scaled by the number of fins and gates, with mobility μ\mu adjusted for multi-surface scattering. These formulations ensure smooth transitions to above-threshold operation. Parameter extraction for these models typically bridges technology computer-aided design (TCAD) simulations with measured silicon data, optimizing parameters like VtV_t and mobility μ\mu through global fitting algorithms that minimize errors in I-V and C-V curves across multiple device geometries. Techniques such as or are employed to handle the high dimensionality of multigate parameters, achieving root-mean-square errors below 2% for FinFETs down to 10 nm nodes. TCAD provides initial estimates by solving full 3D drift-diffusion equations, refined against fabricated device measurements to capture process variations. Limitations arise in ultra-thin channels below 5 nm, where quantum confinement effects—such as sub-band energy shifts—increase effective bandgap and by 50-200 mV, necessitating ballistic transport models that replace diffusive assumptions with Landauer formalism to account for non-local . These quantum corrections, often implemented as density-gradient add-ons to Poisson solvers, are essential for GAA devices but increase model complexity, potentially slowing simulations by 10-20 times. The adoption of multigate devices began with Intel's introduction of tri-gate transistors in its node in 2011, marking the first commercial deployment of non-planar FinFET-like structures for improved performance and power efficiency in logic chips. This was followed by widespread FinFET adoption at the 7 nm node, with initiating volume production in 2018 to enable high-density, low-power applications in mobile processors. advanced to gate-all-around (GAA) architecture with its in 2022, achieving 23% higher performance and 45% lower power compared to prior 5 nm FinFET nodes through multi-bridge-channel FET (MBCFET) technology. progressed with RibbonFET, a GAA variant, in its 18A node (equivalent to ~1.8 nm class), entering production in 2025 for products such as Panther Lake processors. Key market drivers for multigate adoption include the demands of mobile system-on-chips (SoCs), high-performance computing (HPC), and AI accelerators, where these devices deliver superior electrostatic control for reduced leakage and higher drive currents at low voltages. In mobile SoCs, GAA structures enable compact designs with extended battery life, while in HPC and AI, they support dense integration for energy-efficient parallel processing in data centers and edge devices. As of November 2025, GAA transistors have entered production for 2 nm nodes across major foundries, with TSMC's N2 using nanosheet GAAFET beginning volume production in late 2025, Samsung's SF2 employing second-generation MBCFET achieving yields sufficient for commercial output, and Intel's 18A utilizing RibbonFET. The global FinFET and GAA market, encompassing multigate technologies, is projected to exceed USD 130 billion by 2030, driven by a of over 23% from applications in and computing. Future trends in multigate devices emphasize complementary FET (CFET) stacking to achieve effective 1 nm scaling through of n- and p-type transistors, potentially reducing footprint by 30-50% while maintaining performance. Hybrid approaches incorporating 2D materials like transition metal dichalcogenides with III-V compounds in GAA channels are emerging to enhance mobility and beyond limits for sub-1 nm equivalents. Additionally, designs are evolving to support quantum-resistant in secure HPC and AI systems, integrating hardened logic without compromising multigate efficiency. Representative case studies highlight practical impacts: Apple's A-series chips, such as the A12 Bionic in the 2018 iPhone XS using TSMC's 7 nm FinFET, achieved 67% higher transistor density over 10 nm for enhanced graphics and neural processing. Similarly, Samsung's processors leverage MBCFET in 3 nm GAA for models like the Exynos 2500 released in 2025, offering adjustable channel widths for optimized SRAM in mobile AI tasks.

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