Depletion-load NMOS logic

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS (n-type metal-oxide semiconductor) logic families that needed multiple power supply voltages. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with enhancement-load devices alone. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).

The inclusion of depletion-mode NMOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.

Although the CMOS process replaced most NMOS designs during the 1980s, some depletion-load NMOS designs are still produced, typically in parallel with newer CMOS counterparts. One example of this is the Z84015 and Z84C15.

Following the invention of the MOSFET by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, they demonstrated MOSFET technology in 1960. They fabricated both PMOS and NMOS devices with a 20 μm process. However, the NMOS devices were impractical, and only the PMOS type were practical working devices.

In 1965, Chih-Tang Sah, Otto Leistiko and A.S. Grove at Fairchild Semiconductor fabricated several NMOS devices with channel lengths between 8 μm and 65 μm. Dale L. Critchlow and Robert H. Dennard at IBM also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a memory chip with 1 kb data and 50–100 ns access time, which entered large-scale manufacturing in the early 1970s. This led to MOS semiconductor memory replacing earlier bipolar and ferrite-core memory technologies in the 1970s.

In the late 1960s, bipolar junction transistors were faster than (p-channel) MOS transistors then used and were more reliable, but they also consumed much more power, required more area, and demanded a more complicated manufacturing process. MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications. One of the reasons for the low speed was that MOS transistors had gates made of aluminum which led to considerable parasitic capacitances using the manufacturing processes of the time. The introduction of transistors with gates of polycrystalline silicon (that became the de facto standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap. This new self-aligned silicon-gate transistor was introduced by Federico Faggin at Fairchild Semiconductor in early 1968; it was a refinement (and the first working implementation) of ideas and work by John C. Sarace, Tom Klein and Robert W. Bower (around 1966–67) for a transistor with lower parasitic capacitances that could be manufactured as part of an IC (and not only as a discrete component). This new type of pMOS transistor was 3–5 times as fast (per watt) as the aluminum-gate pMOS transistor, and it needed less area, had much lower leakage and higher reliability. The same year, Faggin also built the first IC using the new transistor type, the Fairchild 3708 (8-bit analog multiplexer with decoder), which demonstrated a substantially improved performance over its metal-gate counterpart. In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.

There are a couple of drawbacks associated with PMOS: The electron holes that are the charge (current) carriers in PMOS transistors have lower mobility than the electrons that are the charge carriers in NMOS transistors (a ratio of approximately 2.5), furthermore PMOS circuits do not interface easily with low voltage positive logic such as DTL-logic and TTL-logic (the 7400-series). However, PMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from etching chemicals and other sources can very easily prevent (the electron based) NMOS transistors from switching off, while the effect in (the electron-hole based) PMOS transistors is much less severe. Fabrication of NMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices.